/*
* Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PDK2 PCB number: 516-400 or newer
*/
-
/dts-v1/;
-#include "imx6q-dhcom-som.dtsi"
-#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-pdk2.dtsi"
/ {
- model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
- compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- clk_ext_audio_codec: clock-codec {
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- compatible = "fixed-clock";
- };
-
- display_bl: display-bl {
- brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
- compatible = "pwm-backlight";
- default-brightness-level = <8>;
- enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
- pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
- status = "okay";
- };
-
- lcd_display: disp0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "rgb24";
- pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
- pinctrl-names = "default";
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di0_disp0>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- gpio-keys {
- #size-cells = <0>;
- compatible = "gpio-keys";
-
- button-0 {
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
- label = "TA1-GPIO-A";
- linux,code = <KEY_A>;
- pinctrl-0 = <&pinctrl_dhcom_a>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-1 {
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
- label = "TA2-GPIO-B";
- linux,code = <KEY_B>;
- pinctrl-0 = <&pinctrl_dhcom_b>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-2 {
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
- label = "TA3-GPIO-C";
- linux,code = <KEY_C>;
- pinctrl-0 = <&pinctrl_dhcom_c>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-3 {
- gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
- label = "TA4-GPIO-D";
- linux,code = <KEY_D>;
- pinctrl-0 = <&pinctrl_dhcom_d>;
- pinctrl-names = "default";
- wakeup-source;
- };
- };
-
- led {
- compatible = "gpio-leds";
-
- /*
- * Disable led-5, because GPIO E is
- * already used as touch interrupt.
- */
- led-5 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
- pinctrl-0 = <&pinctrl_dhcom_e>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- led-6 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
- pinctrl-0 = <&pinctrl_dhcom_f>;
- pinctrl-names = "default";
- };
-
- led-7 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
- pinctrl-0 = <&pinctrl_dhcom_h>;
- pinctrl-names = "default";
- };
-
- led-8 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
- pinctrl-0 = <&pinctrl_dhcom_i>;
- pinctrl-names = "default";
- };
- };
-
- panel {
- backlight = <&display_bl>;
- compatible = "edt,etm0700g0edh6";
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
- sound {
- audio-codec = <&sgtl5000>;
- audio-routing =
- "MIC_IN", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "LINE_IN", "Line In Jack",
- "Headphone Jack", "HP_OUT";
- compatible = "fsl,imx-audio-sgtl5000";
- model = "imx-sgtl5000";
- mux-ext-port = <3>;
- mux-int-port = <1>;
- ssi-controller = <&ssi1>;
- };
-};
-
-&audmux {
- pinctrl-0 = <&pinctrl_audmux_ext>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&can1 {
- status = "okay";
-};
-
-&can2 {
- status = "disabled";
-};
-
-/* 1G ethernet */
-/delete-node/ ðphy0;
-&fec {
- phy-mode = "rgmii";
- phy-handle = <ðphy7>;
- pinctrl-0 = <&pinctrl_enet_1G>;
- pinctrl-names = "default";
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy7: ethernet-phy@7 { /* KSZ 9021 */
- compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pinctrl_ethphy7>;
- pinctrl-names = "default";
- reg = <7>;
- reset-assert-us = <1000>;
- reset-deassert-us = <1000>;
- reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- rxdv-skew-ps = <0>;
- txc-skew-ps = <3000>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- };
- };
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
-};
-
-&i2c2 {
- sgtl5000: codec@a {
- #sound-dai-cells = <0>;
- clocks = <&clk_ext_audio_codec>;
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- VDDA-supply = <®_3p3v>;
- VDDIO-supply = <&sw2_reg>;
- };
-
- touchscreen@38 {
- compatible = "edt,edt-ft5406";
- interrupt-parent = <&gpio4>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
- pinctrl-0 = <&pinctrl_dhcom_e>;
- pinctrl-names = "default";
- reg = <0x38>;
- };
-};
-
-&ipu1_di0_disp0 {
- remote-endpoint = <&lcd_display_in>;
-};
-
-&pcie {
- pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
- reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
- status = "okay";
-};
-
-&pwm1 {
- pinctrl-0 = <&pinctrl_pwm1>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&ssi1 {
- status = "okay";
+ model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)";
+ compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
+ "fsl,imx6q";
};
&sata {
status = "okay";
};
-
-&usdhc3 { /* Micro SD card on module */
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-0 = <
- /*
- * The following DHCOM GPIOs are used on this board.
- * Therefore, they have been removed from the list below.
- * A: key TA1
- * B: key TA2
- * C: key TA3
- * D: key TA4
- * E: touchscreen
- * F: led6
- * G: backlight enable
- * H: led7
- * I: led8
- * J: PCIe reset
- */
- &pinctrl_hog_base
- &pinctrl_dhcom_k &pinctrl_dhcom_l
- &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
- &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
- >;
- pinctrl-names = "default";
-
- pinctrl_audmux_ext: audmux-ext-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- >;
- };
-
- pinctrl_enet_1G: enet-1G-grp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
- >;
- };
-
- pinctrl_ethphy7: ethphy7-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
- >;
- };
-
- pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
- >;
- };
-
- pinctrl_pwm1: pwm1-grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2021 DH electronics GmbH
- * Copyright (C) 2018 Marek Vasut <marex@denx.de>
- */
-
-#include "imx6q.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- aliases {
- i2c0 = &i2c2;
- i2c1 = &i2c1;
- i2c2 = &i2c3;
- mmc0 = &usdhc2;
- mmc1 = &usdhc3;
- mmc2 = &usdhc4;
- mmc3 = &usdhc1;
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- serial0 = &uart1;
- serial1 = &uart5;
- serial2 = &uart4;
- serial3 = &uart2;
- serial4 = &uart3;
- };
-
- memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
- device_type = "memory";
- reg = <0x10000000 0x20000000>;
- };
-
- reg_3p3v: regulator-3P3V {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "3P3V";
- };
-
- reg_eth_vio: regulator-eth-vio {
- compatible = "regulator-fixed";
- gpio = <&gpio1 7 0>;
- pinctrl-0 = <&pinctrl_enet_vio>;
- pinctrl-names = "default";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "eth_vio";
- vin-supply = <&sw2_reg>;
- };
-
- /* OE pin of the latch is low active */
- reg_latch_oe_on: regulator-latch-oe-on {
- compatible = "regulator-fixed";
- gpio = <&gpio3 22 0>;
- regulator-always-on;
- regulator-name = "latch_oe_on";
- };
-
- reg_usb_h1_vbus: regulator-usb-h1-vbus {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 31 0>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "usb_h1_vbus";
- };
-
- reg_usb_otg_vbus: regulator-usb-otg-vbus {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "usb_otg_vbus";
- };
-};
-
-&can1 {
- pinctrl-0 = <&pinctrl_flexcan1>;
- pinctrl-names = "default";
-};
-
-/*
- * Special hardware required which uses the pins from micro SD card. The pins
- * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx
- * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board
- * device tree file, you also need to disable the micro SD card and the uart1
- * rts/cts have to be disabled or output on other DHCOM pins.
- */
-&can2 {
- pinctrl-0 = <&pinctrl_flexcan2>;
- pinctrl-names = "default";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pinctrl_ecspi1>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 { /* S25FL116K */
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- m25p,fast-read;
- reg = <0>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&ecspi2 {
- cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pinctrl_ecspi2>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&fec {
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- pinctrl-0 = <&pinctrl_enet_100M>;
- pinctrl-names = "default";
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
- compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio4>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pinctrl_ethphy0>;
- pinctrl-names = "default";
- reg = <0>;
- reset-assert-us = <1000>;
- reset-deassert-us = <1000>;
- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- smsc,disable-energy-detect; /* Make plugin detection reliable */
- };
- };
-};
-
-&gpio1 {
- gpio-line-names =
- "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
- "", "", "", "", "", "", "", "",
- "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "DHCOM-G", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
- "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
- "", "", "", "", "DHCOM-F", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio6 {
- gpio-line-names =
- "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
- "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio7 {
- gpio-line-names =
- "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
- "", "", "", "", "", "DHCOM-P", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- /*
- * Info: According to erratum ERR007805 clock frequency limit is 375000.
- * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
- * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
- * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- pinctrl-names = "default", "gpio";
- scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&i2c2 {
- /* Info: Clock frequency limit is 375000 (for details see i2c1) */
- clock-frequency = <100000>;
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- pinctrl-names = "default", "gpio";
- scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&i2c3 {
- /* Info: Clock frequency limit is 375000 (for details see i2c1) */
- clock-frequency = <100000>;
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- pinctrl-names = "default", "gpio";
- scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- ltc3676: pmic@3c {
- compatible = "lltc,ltc3676";
- interrupt-parent = <&gpio5>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-0 = <&pinctrl_pmic>;
- pinctrl-names = "default";
- reg = <0x3c>;
-
- regulators {
- sw1_reg: sw1 {
- lltc,fb-voltage-divider = <100000 110000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1527272>;
- regulator-min-microvolt = <787500>;
- regulator-ramp-delay = <7000>;
- regulator-suspend-mem-microvolt = <1040000>;
- };
-
- sw2_reg: sw2 {
- lltc,fb-voltage-divider = <100000 28000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3657142>;
- regulator-min-microvolt = <1885714>;
- regulator-ramp-delay = <7000>;
- };
-
- sw3_reg: sw3 {
- lltc,fb-voltage-divider = <100000 110000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1527272>;
- regulator-min-microvolt = <787500>;
- regulator-ramp-delay = <7000>;
- regulator-suspend-mem-microvolt = <980000>;
- };
-
- sw4_reg: sw4 {
- lltc,fb-voltage-divider = <100000 93100>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1659291>;
- regulator-min-microvolt = <855571>;
- regulator-ramp-delay = <7000>;
- };
-
- ldo1_reg: ldo1 {
- lltc,fb-voltage-divider = <102000 29400>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3240306>;
- regulator-min-microvolt = <3240306>;
- };
-
- ldo2_reg: ldo2 {
- lltc,fb-voltage-divider = <100000 41200>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2484708>;
- regulator-min-microvolt = <2484708>;
- };
- };
- };
-
- touchscreen@49 { /* TSC2004 */
- compatible = "ti,tsc2004";
- interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-0 = <&pinctrl_tsc2004>;
- pinctrl-names = "default";
- reg = <0x49>;
- vio-supply = <®_3p3v>;
- status = "disabled";
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- pagesize = <16>;
- reg = <0x50>;
- };
-
- rtc_i2c: rtc@56 {
- compatible = "microcrystal,rv3029";
- interrupt-parent = <&gpio7>;
- interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-0 = <&pinctrl_rtc>;
- pinctrl-names = "default";
- reg = <0x56>;
- };
-};
-
-&pcie {
- pinctrl-0 = <&pinctrl_pcie>;
- pinctrl-names = "default";
-};
-
-®_arm {
- vin-supply = <&sw3_reg>;
-};
-
-®_pu {
- vin-supply = <&sw1_reg>;
-};
-
-®_soc {
- vin-supply = <&sw1_reg>;
-};
-
-®_vdd1p1 {
- vin-supply = <&sw2_reg>;
-};
-
-®_vdd2p5 {
- vin-supply = <&sw2_reg>;
-};
-
-&uart1 { /* DHCOM UART1 */
- dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
- dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
- rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pinctrl_uart1>;
- pinctrl-names = "default";
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 { /* DHCOM UART3 */
- pinctrl-0 = <&pinctrl_uart4>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&uart5 { /* DHCOM UART2 */
- pinctrl-0 = <&pinctrl_uart5>;
- pinctrl-names = "default";
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbh1 {
- dr_mode = "host";
- pinctrl-0 = <&pinctrl_usbh1>;
- pinctrl-names = "default";
- vbus-supply = <®_usb_h1_vbus>;
- status = "okay";
-};
-
-&usbotg {
- disable-over-current;
- dr_mode = "otg";
- pinctrl-0 = <&pinctrl_usbotg>;
- pinctrl-names = "default";
- vbus-supply = <®_usb_otg_vbus>;
- status = "okay";
-};
-
-&usdhc2 { /* External SD card via DHCOM */
- cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- keep-power-in-suspend;
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usdhc3 { /* Micro SD card on module */
- cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
- fsl,wp-controller;
- keep-power-in-suspend;
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-names = "default";
- status = "disabled";
-};
-
-&usdhc4 { /* eMMC on module */
- bus-width = <8>;
- keep-power-in-suspend;
- no-1-8-v;
- non-removable;
- pinctrl-0 = <&pinctrl_usdhc4>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&weim {
- #address-cells = <2>;
- #size-cells = <1>;
- fsl,weim-cs-gpr = <&gpr>;
- pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
- pinctrl-names = "default";
- /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
- ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
- <1 0 0x0c000000 0x04000000>; /* CS1 */
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl-0 = <
- &pinctrl_hog_base
- &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
- &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
- &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
- &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
- &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
- &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
- &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
- &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
- >;
- pinctrl-names = "default";
-
- pinctrl_hog_base: hog-base-grp {
- fsl,pins = <
- /* GPIOs for memory coding */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
- /* GPIOs for hardware coding */
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
- >;
- };
-
- /* DHCOM GPIOs */
- pinctrl_dhcom_a: dhcom-a-grp {
- fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
- };
-
- pinctrl_dhcom_b: dhcom-b-grp {
- fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
- };
-
- pinctrl_dhcom_c: dhcom-c-grp {
- fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
- };
-
- pinctrl_dhcom_d: dhcom-d-grp {
- fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
- };
-
- pinctrl_dhcom_e: dhcom-e-grp {
- fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
- };
-
- pinctrl_dhcom_f: dhcom-f-grp {
- fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
- };
-
- pinctrl_dhcom_g: dhcom-g-grp {
- fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
- };
-
- pinctrl_dhcom_h: dhcom-h-grp {
- fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
- };
-
- pinctrl_dhcom_i: dhcom-i-grp {
- fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
- };
-
- pinctrl_dhcom_j: dhcom-j-grp {
- fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
- };
-
- pinctrl_dhcom_k: dhcom-k-grp {
- fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
- };
-
- pinctrl_dhcom_l: dhcom-l-grp {
- fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
- };
-
- pinctrl_dhcom_m: dhcom-m-grp {
- fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
- };
-
- pinctrl_dhcom_n: dhcom-n-grp {
- fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
- };
-
- pinctrl_dhcom_o: dhcom-o-grp {
- fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
- };
-
- pinctrl_dhcom_p: dhcom-p-grp {
- fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
- };
-
- pinctrl_dhcom_q: dhcom-q-grp {
- fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
- };
-
- pinctrl_dhcom_r: dhcom-r-grp {
- fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
- };
-
- pinctrl_dhcom_s: dhcom-s-grp {
- fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
- };
-
- pinctrl_dhcom_t: dhcom-t-grp {
- fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
- };
-
- pinctrl_dhcom_u: dhcom-u-grp {
- fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
- };
-
- pinctrl_dhcom_v: dhcom-v-grp {
- fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
- };
-
- pinctrl_dhcom_w: dhcom-w-grp {
- fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
- };
-
- pinctrl_dhcom_int: dhcom-int-grp {
- fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
- };
-
- pinctrl_ecspi1: ecspi1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- >;
- };
-
- pinctrl_ecspi2: ecspi2-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
- >;
- };
-
- pinctrl_enet_100M: enet-100M-grp {
- fsl,pins = <
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- >;
- };
-
- pinctrl_enet_vio: enet-vio-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
- >;
- };
-
- pinctrl_ethphy0: ethphy0-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
- >;
- };
-
- pinctrl_flexcan1: flexcan1-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2-grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1-gpio-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2: i2c2-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2-gpio-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3-gpio-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
- >;
- };
-
- pinctrl_pcie: pcie-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
- >;
- };
-
- pinctrl_pmic: pmic-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
- >;
- };
-
- pinctrl_rtc: rtc-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
- >;
- };
-
- pinctrl_tsc2004: tsc2004-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
- >;
- };
-
- pinctrl_uart1: uart1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
- MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
- MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
- >;
- };
-
- pinctrl_usbh1: usbh1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
- >;
- };
-
- pinctrl_usbotg: usbotg-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usdhc2: usdhc2-grp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3: usdhc3-grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
- >;
- };
-
- pinctrl_usdhc4: usdhc4-grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
- >;
- };
-
- pinctrl_weim: weim-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
- MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
- >;
- };
-
- pinctrl_weim_cs0: weim-cs0-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
- >;
- };
-
- pinctrl_weim_cs1: weim-cs1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2021 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ compatible = "fixed-clock";
+ };
+
+ display_bl: display-bl {
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ compatible = "pwm-backlight";
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
+ pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
+ status = "okay";
+ };
+
+ lcd_display: disp0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb24";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ gpio-keys {
+ #size-cells = <0>;
+ compatible = "gpio-keys";
+
+ button-0 {
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
+ label = "TA1-GPIO-A";
+ linux,code = <KEY_A>;
+ pinctrl-0 = <&pinctrl_dhcom_a>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-1 {
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ pinctrl-0 = <&pinctrl_dhcom_b>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-2 {
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
+ label = "TA3-GPIO-C";
+ linux,code = <KEY_C>;
+ pinctrl-0 = <&pinctrl_dhcom_c>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-3 {
+ gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
+ label = "TA4-GPIO-D";
+ linux,code = <KEY_D>;
+ pinctrl-0 = <&pinctrl_dhcom_d>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ /*
+ * Disable led-5, because GPIO E is
+ * already used as touch interrupt.
+ */
+ led-5 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
+ pinctrl-0 = <&pinctrl_dhcom_f>;
+ pinctrl-names = "default";
+ };
+
+ led-7 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
+ pinctrl-0 = <&pinctrl_dhcom_h>;
+ pinctrl-names = "default";
+ };
+
+ led-8 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ pinctrl-0 = <&pinctrl_dhcom_i>;
+ pinctrl-names = "default";
+ };
+ };
+
+ panel {
+ backlight = <&display_bl>;
+ compatible = "edt,etm0700g0edh6";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ sound {
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx-sgtl5000";
+ mux-ext-port = <3>;
+ mux-int-port = <1>;
+ ssi-controller = <&ssi1>;
+ };
+};
+
+&audmux {
+ pinctrl-0 = <&pinctrl_audmux_ext>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
+/* 1G ethernet */
+/delete-node/ ðphy0;
+&fec {
+ phy-mode = "rgmii";
+ phy-handle = <ðphy7>;
+ pinctrl-0 = <&pinctrl_enet_1G>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy7: ethernet-phy@7 { /* KSZ 9021 */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy7>;
+ pinctrl-names = "default";
+ reg = <7>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+ rxc-skew-ps = <3000>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <3000>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c2 {
+ sgtl5000: codec@a {
+ #sound-dai-cells = <0>;
+ clocks = <&clk_ext_audio_codec>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <&sw2_reg>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ pinctrl-names = "default";
+ reg = <0x38>;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&pcie {
+ pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
+ reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&usdhc2 { /* SD card */
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * A: key TA1
+ * B: key TA2
+ * C: key TA3
+ * D: key TA4
+ * E: touchscreen
+ * F: led6
+ * G: backlight enable
+ * H: led7
+ * I: led8
+ * J: PCIe reset
+ */
+ &pinctrl_hog_base
+ &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+ >;
+ pinctrl-names = "default";
+
+ pinctrl_audmux_ext: audmux-ext-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_enet_1G: enet-1G-grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ >;
+ };
+
+ pinctrl_ethphy7: ethphy7-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
+ >;
+ };
+
+ pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2021 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ mmc3 = &usdhc1;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart5;
+ serial2 = &uart4;
+ serial3 = &uart2;
+ serial4 = &uart3;
+ };
+
+ memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ reg_3p3v: regulator-3P3V {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "3P3V";
+ };
+
+ reg_eth_vio: regulator-eth-vio {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 7 0>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_vio";
+ vin-supply = <&sw2_reg>;
+ };
+
+ /* OE pin of the latch is low active */
+ reg_latch_oe_on: regulator-latch-oe-on {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 22 0>;
+ regulator-always-on;
+ regulator-name = "latch_oe_on";
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 31 0>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "usb_h1_vbus";
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "usb_otg_vbus";
+ };
+};
+
+&can1 {
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
+ * the board device tree file, the micro SD card must be disabled and the uart1
+ * rts/cts must be disabled or output on other DHCOM pins.
+ */
+&can2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 { /* S25FL116K */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&fec {
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ pinctrl-0 = <&pinctrl_enet_100M>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio4>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy0>;
+ pinctrl-names = "default";
+ reg = <0>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
+ "", "", "", "", "", "", "", "",
+ "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "DHCOM-G", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
+ "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
+ "", "", "", "", "DHCOM-F", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
+ "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio7 {
+ gpio-line-names =
+ "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
+ "", "", "", "", "", "DHCOM-P", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ /*
+ * Info: According to erratum ERR007805 clock frequency limit is 375000.
+ * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
+ * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
+ * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c2 {
+ /* Info: Clock frequency limit is 375000 (for details see i2c1) */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ /* Info: Clock frequency limit is 375000 (for details see i2c1) */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ pinctrl-names = "default";
+ reg = <0x3c>;
+
+ regulators {
+ sw1_reg: sw1 {
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1527272>;
+ regulator-min-microvolt = <787500>;
+ regulator-ramp-delay = <7000>;
+ regulator-suspend-mem-microvolt = <1040000>;
+ };
+
+ sw2_reg: sw2 {
+ lltc,fb-voltage-divider = <100000 28000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3657142>;
+ regulator-min-microvolt = <1885714>;
+ regulator-ramp-delay = <7000>;
+ };
+
+ sw3_reg: sw3 {
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1527272>;
+ regulator-min-microvolt = <787500>;
+ regulator-ramp-delay = <7000>;
+ regulator-suspend-mem-microvolt = <980000>;
+ };
+
+ sw4_reg: sw4 {
+ lltc,fb-voltage-divider = <100000 93100>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1659291>;
+ regulator-min-microvolt = <855571>;
+ regulator-ramp-delay = <7000>;
+ };
+
+ ldo1_reg: ldo1 {
+ lltc,fb-voltage-divider = <102000 29400>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3240306>;
+ regulator-min-microvolt = <3240306>;
+ };
+
+ ldo2_reg: ldo2 {
+ lltc,fb-voltage-divider = <100000 41200>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2484708>;
+ regulator-min-microvolt = <2484708>;
+ };
+ };
+ };
+
+ touchscreen@49 { /* TSC2004 */
+ compatible = "ti,tsc2004";
+ interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_tsc2004>;
+ pinctrl-names = "default";
+ reg = <0x49>;
+ vio-supply = <®_3p3v>;
+ status = "disabled";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ rtc_i2c: rtc@56 {
+ compatible = "microcrystal,rv3029";
+ interrupt-parent = <&gpio7>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_rtc>;
+ pinctrl-names = "default";
+ reg = <0x56>;
+ };
+};
+
+&pcie {
+ pinctrl-0 = <&pinctrl_pcie>;
+ pinctrl-names = "default";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-names = "default";
+};
+
+®_arm {
+ vin-supply = <&sw3_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1_reg>;
+};
+
+®_vdd1p1 {
+ vin-supply = <&sw2_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&sw2_reg>;
+};
+
+&uart1 { /* DHCOM UART1 */
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 { /* DHCOM UART3 */
+ pinctrl-0 = <&pinctrl_uart4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart5 { /* DHCOM UART2 */
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ dr_mode = "host";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ pinctrl-names = "default";
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ dr_mode = "otg";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ pinctrl-names = "default";
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usdhc2 { /* External SD card via DHCOM */
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&usdhc3 { /* Micro SD card on module */
+ cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ fsl,wp-controller;
+ keep-power-in-suspend;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usdhc4 { /* eMMC on module */
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&weim {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ fsl,weim-cs-gpr = <&gpr>;
+ pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+ pinctrl-names = "default";
+ /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
+ ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
+ <1 0 0x0c000000 0x04000000>; /* CS1 */
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ &pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+ >;
+ pinctrl-names = "default";
+
+ pinctrl_hog_base: hog-base-grp {
+ fsl,pins = <
+ /* GPIOs for memory coding */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
+ /* GPIOs for hardware coding */
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
+ >;
+ };
+
+ /* DHCOM GPIOs */
+ pinctrl_dhcom_a: dhcom-a-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
+ };
+
+ pinctrl_dhcom_b: dhcom-b-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
+ };
+
+ pinctrl_dhcom_c: dhcom-c-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
+ };
+
+ pinctrl_dhcom_d: dhcom-d-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
+ };
+
+ pinctrl_dhcom_e: dhcom-e-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
+ };
+
+ pinctrl_dhcom_f: dhcom-f-grp {
+ fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
+ };
+
+ pinctrl_dhcom_g: dhcom-g-grp {
+ fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
+ };
+
+ pinctrl_dhcom_h: dhcom-h-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
+ };
+
+ pinctrl_dhcom_i: dhcom-i-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
+ };
+
+ pinctrl_dhcom_j: dhcom-j-grp {
+ fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
+ };
+
+ pinctrl_dhcom_k: dhcom-k-grp {
+ fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
+ };
+
+ pinctrl_dhcom_l: dhcom-l-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
+ };
+
+ pinctrl_dhcom_m: dhcom-m-grp {
+ fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
+ };
+
+ pinctrl_dhcom_n: dhcom-n-grp {
+ fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
+ };
+
+ pinctrl_dhcom_o: dhcom-o-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
+ };
+
+ pinctrl_dhcom_p: dhcom-p-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
+ };
+
+ pinctrl_dhcom_q: dhcom-q-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_r: dhcom-r-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
+ };
+
+ pinctrl_dhcom_s: dhcom-s-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
+ };
+
+ pinctrl_dhcom_t: dhcom-t-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
+ };
+
+ pinctrl_dhcom_u: dhcom-u-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
+ };
+
+ pinctrl_dhcom_v: dhcom-v-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_w: dhcom-w-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
+ };
+
+ pinctrl_dhcom_int: dhcom-int-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet_100M: enet-100M-grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_enet_vio: enet-vio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
+ >;
+ };
+
+ pinctrl_ethphy0: ethphy0-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pcie-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
+ >;
+ };
+
+ pinctrl_pmic: pmic-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
+ >;
+ };
+
+ pinctrl_tsc2004: tsc2004-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
+ MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotg-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_weim: weim-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
+ MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
+ >;
+ };
+
+ pinctrl_weim_cs0: weim-cs0-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs1: weim-cs1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
+ >;
+ };
+};
projects / linux-2.6-microblaze.git / commitdiff