arm64: dts: marvell: armada-37xx: Move PCIe comphy handle property

Move the comphy handle property of the PCIe node from board specific
device tree files (EspressoBin and Turris Mox) to the generic
armada-37xx.dtsi.

This is correct since this is the only possible PCIe PHY configuration
on Armada 37xx, so when PCIe is enabled on any board, this handle is
correct.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index c92ad66..b97218c 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -44,7 +44,6 @@
 /* J9 */
 &pcie0 {
        status = "okay";
-       phys = <&comphy1 0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
        reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index e496bd9..15c1cf5 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -134,7 +134,6 @@
        status = "okay";
        max-link-speed = <2>;
        reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-       phys = <&comphy1 0>;
 
        /* enabled by U-Boot if PCIe module is present */
        status = "disabled";

diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 7909c14..5aaad64 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -493,6 +493,7 @@
                                        <0 0 0 2 &pcie_intc 1>,
                                        <0 0 0 3 &pcie_intc 2>,
                                        <0 0 0 4 &pcie_intc 3>;
+                       phys = <&comphy1 0>;
                        pcie_intc: interrupt-controller {
                                interrupt-controller;
                                #interrupt-cells = <1>;