net/mlx5e: Fix setting of RS FEC mode
authorAya Levin <ayal@nvidia.com>
Sun, 11 Apr 2021 06:33:12 +0000 (09:33 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 14 Apr 2021 23:12:57 +0000 (16:12 -0700)
Change register setting from bit number to bit mask.

Fixes: b5ede32d3329 ("net/mlx5e: Add support for FEC modes based on 50G per lane links")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Eran Ben Elisha <eranbe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en/port.c

index 308fd27..89510ca 100644 (file)
@@ -387,21 +387,6 @@ enum mlx5e_fec_supported_link_mode {
                        *_policy = MLX5_GET(pplm_reg, _buf, fec_override_admin_##link); \
        } while (0)
 
-#define MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(buf, policy, write, link)                  \
-       do {                                                                            \
-               unsigned long policy_long;                                              \
-               u16 *__policy = &(policy);                                              \
-               bool _write = (write);                                                  \
-                                                                                       \
-               policy_long = *__policy;                                                \
-               if (_write && *__policy)                                                \
-                       *__policy = find_first_bit(&policy_long,                        \
-                                                  sizeof(policy_long) * BITS_PER_BYTE);\
-               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, *__policy, _write, link);          \
-               if (!_write && *__policy)                                               \
-                       *__policy = 1 << *__policy;                                     \
-       } while (0)
-
 /* get/set FEC admin field for a given speed */
 static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
                                 enum mlx5e_fec_supported_link_mode link_mode)
@@ -423,16 +408,16 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
                MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g);
                break;
        case MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X:
-               MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(pplm, *fec_policy, write, 50g_1x);
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 50g_1x);
                break;
        case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X:
-               MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(pplm, *fec_policy, write, 100g_2x);
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g_2x);
                break;
        case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X:
-               MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(pplm, *fec_policy, write, 200g_4x);
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_4x);
                break;
        case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X:
-               MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(pplm, *fec_policy, write, 400g_8x);
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_8x);
                break;
        default:
                return -EINVAL;