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(parent: 41bafb3) | patch
net/mlx5e: Fix setting of RS FEC mode
authorAya Levin <ayal@nvidia.com>
Sun, 11 Apr 2021 06:33:12 +0000 (09:33 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 14 Apr 2021 23:12:57 +0000 (16:12 -0700)
commit7a320c9db3e73fb6c4f9a331087df9df18767221
treee6d97004dd8e7f304b403c57b760b457fb976799tree | snapshot
parent41bafb31dcd58d834bdffa5db703f94fd2cec727commit | diff
net/mlx5e: Fix setting of RS FEC mode

Change register setting from bit number to bit mask.

Fixes: b5ede32d3329 ("net/mlx5e: Add support for FEC modes based on 50G per lane links")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Eran Ben Elisha <eranbe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en/port.c diff | blob | history
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