PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code

The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.

Link: https://lore.kernel.org/r/20200821035420.380495-36-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 62a6735..5240153 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -551,6 +551,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
 
        val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
        val &= ~PORT_LINK_FAST_LINK_MODE;
 
        val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
        val &= ~PORT_LINK_FAST_LINK_MODE;

+       val |= PORT_LINK_DLL_LINK_EN;

        dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
        of_property_read_u32(np, "num-lanes", &pci->num_lanes);
        dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
        of_property_read_u32(np, "num-lanes", &pci->num_lanes);

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 2c0d32f..d15e49b 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -164,10 +164,6 @@ static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp)
        val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) |
               FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts);
        pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val);
        val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) |
               FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts);
        pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val);

-
-       /* Port Link Control Register */
-       pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_LINK_CONTROL, PORT_LINK_DLL_LINK_EN,
-                           PORT_LINK_DLL_LINK_EN);

 }
 
 static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)
 }
 
 static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)