drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define ATOM_RATIOS             0x66a
  41 #define ATOM_VIDS               0x66b
  42 #define ATOM_TURBO_RATIOS       0x66c
  43 #define ATOM_TURBO_VIDS         0x66d
  44
  45 #ifdef CONFIG_ACPI
  46 #include <acpi/processor.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define EXT_BITS 6
  54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline u64 mul_ext_fp(u64 x, u64 y)
  78 {
  79         return (x * y) >> EXT_FRAC_BITS;
  80 }
  81
  82 static inline u64 div_ext_fp(u64 x, u64 y)
  83 {
  84         return div64_u64(x << EXT_FRAC_BITS, y);
  85 }
  86
  87 /**
  88  * struct sample -      Store performance sample
  89  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  90  *                      performance during last sample period
  91  * @busy_scaled:        Scaled busy value which is used to calculate next
  92  *                      P state. This can be different than core_avg_perf
  93  *                      to account for cpu idle period
  94  * @aperf:              Difference of actual performance frequency clock count
  95  *                      read from APERF MSR between last and current sample
  96  * @mperf:              Difference of maximum performance frequency clock count
  97  *                      read from MPERF MSR between last and current sample
  98  * @tsc:                Difference of time stamp counter between last and
  99  *                      current sample
 100  * @time:               Current time from scheduler
 101  *
 102  * This structure is used in the cpudata structure to store performance sample
 103  * data for choosing next P State.
 104  */
 105 struct sample {
 106         int32_t core_avg_perf;
 107         int32_t busy_scaled;
 108         u64 aperf;
 109         u64 mperf;
 110         u64 tsc;
 111         u64 time;
 112 };
 113
 114 /**
 115  * struct pstate_data - Store P state data
 116  * @current_pstate:     Current requested P state
 117  * @min_pstate:         Min P state possible for this platform
 118  * @max_pstate:         Max P state possible for this platform
 119  * @max_pstate_physical:This is physical Max P state for a processor
 120  *                      This can be higher than the max_pstate which can
 121  *                      be limited by platform thermal design power limits
 122  * @scaling:            Scaling factor to  convert frequency to cpufreq
 123  *                      frequency units
 124  * @turbo_pstate:       Max Turbo P state possible for this platform
 125  *
 126  * Stores the per cpu model P state limits and current P state.
 127  */
 128 struct pstate_data {
 129         int     current_pstate;
 130         int     min_pstate;
 131         int     max_pstate;
 132         int     max_pstate_physical;
 133         int     scaling;
 134         int     turbo_pstate;
 135 };
 136
 137 /**
 138  * struct vid_data -    Stores voltage information data
 139  * @min:                VID data for this platform corresponding to
 140  *                      the lowest P state
 141  * @max:                VID data corresponding to the highest P State.
 142  * @turbo:              VID data for turbo P state
 143  * @ratio:              Ratio of (vid max - vid min) /
 144  *                      (max P state - Min P State)
 145  *
 146  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 147  * This data is used in Atom platforms, where in addition to target P state,
 148  * the voltage data needs to be specified to select next P State.
 149  */
 150 struct vid_data {
 151         int min;
 152         int max;
 153         int turbo;
 154         int32_t ratio;
 155 };
 156
 157 /**
 158  * struct _pid -        Stores PID data
 159  * @setpoint:           Target set point for busyness or performance
 160  * @integral:           Storage for accumulated error values
 161  * @p_gain:             PID proportional gain
 162  * @i_gain:             PID integral gain
 163  * @d_gain:             PID derivative gain
 164  * @deadband:           PID deadband
 165  * @last_err:           Last error storage for integral part of PID calculation
 166  *
 167  * Stores PID coefficients and last error for PID controller.
 168  */
 169 struct _pid {
 170         int setpoint;
 171         int32_t integral;
 172         int32_t p_gain;
 173         int32_t i_gain;
 174         int32_t d_gain;
 175         int deadband;
 176         int32_t last_err;
 177 };
 178
 179 /**
 180  * struct cpudata -     Per CPU instance data storage
 181  * @cpu:                CPU number for this instance data
 182  * @policy:             CPUFreq policy value
 183  * @update_util:        CPUFreq utility callback information
 184  * @update_util_set:    CPUFreq utility callback is set
 185  * @iowait_boost:       iowait-related boost fraction
 186  * @last_update:        Time of the last update.
 187  * @pstate:             Stores P state limits for this CPU
 188  * @vid:                Stores VID limits for this CPU
 189  * @pid:                Stores PID parameters for this CPU
 190  * @last_sample_time:   Last Sample time
 191  * @prev_aperf:         Last APERF value read from APERF MSR
 192  * @prev_mperf:         Last MPERF value read from MPERF MSR
 193  * @prev_tsc:           Last timestamp counter (TSC) value
 194  * @prev_cummulative_iowait: IO Wait time difference from last and
 195  *                      current sample
 196  * @sample:             Storage for storing last Sample data
 197  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 198  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 199  *
 200  * This structure stores per CPU instance data for all CPUs.
 201  */
 202 struct cpudata {
 203         int cpu;
 204
 205         unsigned int policy;
 206         struct update_util_data update_util;
 207         bool   update_util_set;
 208
 209         struct pstate_data pstate;
 210         struct vid_data vid;
 211         struct _pid pid;
 212
 213         u64     last_update;
 214         u64     last_sample_time;
 215         u64     prev_aperf;
 216         u64     prev_mperf;
 217         u64     prev_tsc;
 218         u64     prev_cummulative_iowait;
 219         struct sample sample;
 220 #ifdef CONFIG_ACPI
 221         struct acpi_processor_performance acpi_perf_data;
 222         bool valid_pss_table;
 223 #endif
 224         unsigned int iowait_boost;
 225 };
 226
 227 static struct cpudata **all_cpu_data;
 228
 229 /**
 230  * struct pstate_adjust_policy - Stores static PID configuration data
 231  * @sample_rate_ms:     PID calculation sample rate in ms
 232  * @sample_rate_ns:     Sample rate calculation in ns
 233  * @deadband:           PID deadband
 234  * @setpoint:           PID Setpoint
 235  * @p_gain_pct:         PID proportional gain
 236  * @i_gain_pct:         PID integral gain
 237  * @d_gain_pct:         PID derivative gain
 238  *
 239  * Stores per CPU model static PID configuration data.
 240  */
 241 struct pstate_adjust_policy {
 242         int sample_rate_ms;
 243         s64 sample_rate_ns;
 244         int deadband;
 245         int setpoint;
 246         int p_gain_pct;
 247         int d_gain_pct;
 248         int i_gain_pct;
 249 };
 250
 251 /**
 252  * struct pstate_funcs - Per CPU model specific callbacks
 253  * @get_max:            Callback to get maximum non turbo effective P state
 254  * @get_max_physical:   Callback to get maximum non turbo physical P state
 255  * @get_min:            Callback to get minimum P state
 256  * @get_turbo:          Callback to get turbo P state
 257  * @get_scaling:        Callback to get frequency scaling factor
 258  * @get_val:            Callback to convert P state to actual MSR write value
 259  * @get_vid:            Callback to get VID data for Atom platforms
 260  * @get_target_pstate:  Callback to a function to calculate next P state to use
 261  *
 262  * Core and Atom CPU models have different way to get P State limits. This
 263  * structure is used to store those callbacks.
 264  */
 265 struct pstate_funcs {
 266         int (*get_max)(void);
 267         int (*get_max_physical)(void);
 268         int (*get_min)(void);
 269         int (*get_turbo)(void);
 270         int (*get_scaling)(void);
 271         u64 (*get_val)(struct cpudata*, int pstate);
 272         void (*get_vid)(struct cpudata *);
 273         int32_t (*get_target_pstate)(struct cpudata *);
 274 };
 275
 276 /**
 277  * struct cpu_defaults- Per CPU model default config data
 278  * @pid_policy: PID config data
 279  * @funcs:              Callback function data
 280  */
 281 struct cpu_defaults {
 282         struct pstate_adjust_policy pid_policy;
 283         struct pstate_funcs funcs;
 284 };
 285
 286 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 287 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 288
 289 static struct pstate_adjust_policy pid_params __read_mostly;
 290 static struct pstate_funcs pstate_funcs __read_mostly;
 291 static int hwp_active __read_mostly;
 292
 293 #ifdef CONFIG_ACPI
 294 static bool acpi_ppc;
 295 #endif
 296
 297 /**
 298  * struct perf_limits - Store user and policy limits
 299  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 300  * @turbo_disabled:     Platform turbo status either from msr
 301  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 302  *                      matches the maximum turbo pstate
 303  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 304  *                      is minimum of either limits enforced by cpufreq policy
 305  *                      or limits from user set limits via intel_pstate sysfs
 306  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 307  *                      is maximum of either limits enforced by cpufreq policy
 308  *                      or limits from user set limits via intel_pstate sysfs
 309  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 310  *                      This value is used to limit max pstate
 311  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 312  *                      This value is used to limit min pstate
 313  * @max_policy_pct:     The maximum performance in percentage enforced by
 314  *                      cpufreq setpolicy interface
 315  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 316  *                      intel pstate sysfs interface
 317  * @min_policy_pct:     The minimum performance in percentage enforced by
 318  *                      cpufreq setpolicy interface
 319  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 320  *                      intel pstate sysfs interface
 321  *
 322  * Storage for user and policy defined limits.
 323  */
 324 struct perf_limits {
 325         int no_turbo;
 326         int turbo_disabled;
 327         int max_perf_pct;
 328         int min_perf_pct;
 329         int32_t max_perf;
 330         int32_t min_perf;
 331         int max_policy_pct;
 332         int max_sysfs_pct;
 333         int min_policy_pct;
 334         int min_sysfs_pct;
 335 };
 336
 337 static struct perf_limits performance_limits = {
 338         .no_turbo = 0,
 339         .turbo_disabled = 0,
 340         .max_perf_pct = 100,
 341         .max_perf = int_tofp(1),
 342         .min_perf_pct = 100,
 343         .min_perf = int_tofp(1),
 344         .max_policy_pct = 100,
 345         .max_sysfs_pct = 100,
 346         .min_policy_pct = 0,
 347         .min_sysfs_pct = 0,
 348 };
 349
 350 static struct perf_limits powersave_limits = {
 351         .no_turbo = 0,
 352         .turbo_disabled = 0,
 353         .max_perf_pct = 100,
 354         .max_perf = int_tofp(1),
 355         .min_perf_pct = 0,
 356         .min_perf = 0,
 357         .max_policy_pct = 100,
 358         .max_sysfs_pct = 100,
 359         .min_policy_pct = 0,
 360         .min_sysfs_pct = 0,
 361 };
 362
 363 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 364 static struct perf_limits *limits = &performance_limits;
 365 #else
 366 static struct perf_limits *limits = &powersave_limits;
 367 #endif
 368
 369 #ifdef CONFIG_ACPI
 370
 371 static bool intel_pstate_get_ppc_enable_status(void)
 372 {
 373         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 374             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 375                 return true;
 376
 377         return acpi_ppc;
 378 }
 379
 380 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 381 {
 382         struct cpudata *cpu;
 383         int ret;
 384         int i;
 385
 386         if (hwp_active)
 387                 return;
 388
 389         if (!intel_pstate_get_ppc_enable_status())
 390                 return;
 391
 392         cpu = all_cpu_data[policy->cpu];
 393
 394         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 395                                                   policy->cpu);
 396         if (ret)
 397                 return;
 398
 399         /*
 400          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 401          * guarantee that the states returned by it map to the states in our
 402          * list directly.
 403          */
 404         if (cpu->acpi_perf_data.control_register.space_id !=
 405                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 406                 goto err;
 407
 408         /*
 409          * If there is only one entry _PSS, simply ignore _PSS and continue as
 410          * usual without taking _PSS into account
 411          */
 412         if (cpu->acpi_perf_data.state_count < 2)
 413                 goto err;
 414
 415         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 416         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 417                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 418                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 419                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 420                          (u32) cpu->acpi_perf_data.states[i].power,
 421                          (u32) cpu->acpi_perf_data.states[i].control);
 422         }
 423
 424         /*
 425          * The _PSS table doesn't contain whole turbo frequency range.
 426          * This just contains +1 MHZ above the max non turbo frequency,
 427          * with control value corresponding to max turbo ratio. But
 428          * when cpufreq set policy is called, it will call with this
 429          * max frequency, which will cause a reduced performance as
 430          * this driver uses real max turbo frequency as the max
 431          * frequency. So correct this frequency in _PSS table to
 432          * correct max turbo frequency based on the turbo state.
 433          * Also need to convert to MHz as _PSS freq is in MHz.
 434          */
 435         if (!limits->turbo_disabled)
 436                 cpu->acpi_perf_data.states[0].core_frequency =
 437                                         policy->cpuinfo.max_freq / 1000;
 438         cpu->valid_pss_table = true;
 439         pr_debug("_PPC limits will be enforced\n");
 440
 441         return;
 442
 443  err:
 444         cpu->valid_pss_table = false;
 445         acpi_processor_unregister_performance(policy->cpu);
 446 }
 447
 448 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 449 {
 450         struct cpudata *cpu;
 451
 452         cpu = all_cpu_data[policy->cpu];
 453         if (!cpu->valid_pss_table)
 454                 return;
 455
 456         acpi_processor_unregister_performance(policy->cpu);
 457 }
 458
 459 #else
 460 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 461 {
 462 }
 463
 464 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 465 {
 466 }
 467 #endif
 468
 469 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 470                              int deadband, int integral) {
 471         pid->setpoint = int_tofp(setpoint);
 472         pid->deadband  = int_tofp(deadband);
 473         pid->integral  = int_tofp(integral);
 474         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 475 }
 476
 477 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 478 {
 479         pid->p_gain = div_fp(percent, 100);
 480 }
 481
 482 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 483 {
 484         pid->i_gain = div_fp(percent, 100);
 485 }
 486
 487 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 488 {
 489         pid->d_gain = div_fp(percent, 100);
 490 }
 491
 492 static signed int pid_calc(struct _pid *pid, int32_t busy)
 493 {
 494         signed int result;
 495         int32_t pterm, dterm, fp_error;
 496         int32_t integral_limit;
 497
 498         fp_error = pid->setpoint - busy;
 499
 500         if (abs(fp_error) <= pid->deadband)
 501                 return 0;
 502
 503         pterm = mul_fp(pid->p_gain, fp_error);
 504
 505         pid->integral += fp_error;
 506
 507         /*
 508          * We limit the integral here so that it will never
 509          * get higher than 30.  This prevents it from becoming
 510          * too large an input over long periods of time and allows
 511          * it to get factored out sooner.
 512          *
 513          * The value of 30 was chosen through experimentation.
 514          */
 515         integral_limit = int_tofp(30);
 516         if (pid->integral > integral_limit)
 517                 pid->integral = integral_limit;
 518         if (pid->integral < -integral_limit)
 519                 pid->integral = -integral_limit;
 520
 521         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 522         pid->last_err = fp_error;
 523
 524         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 525         result = result + (1 << (FRAC_BITS-1));
 526         return (signed int)fp_toint(result);
 527 }
 528
 529 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 530 {
 531         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 532         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 533         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 534
 535         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 536 }
 537
 538 static inline void intel_pstate_reset_all_pid(void)
 539 {
 540         unsigned int cpu;
 541
 542         for_each_online_cpu(cpu) {
 543                 if (all_cpu_data[cpu])
 544                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 545         }
 546 }
 547
 548 static inline void update_turbo_state(void)
 549 {
 550         u64 misc_en;
 551         struct cpudata *cpu;
 552
 553         cpu = all_cpu_data[0];
 554         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 555         limits->turbo_disabled =
 556                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 557                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 558 }
 559
 560 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
 561 {
 562         int min, hw_min, max, hw_max, cpu, range, adj_range;
 563         u64 value, cap;
 564
 565         for_each_cpu(cpu, cpumask) {
 566                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 567                 hw_min = HWP_LOWEST_PERF(cap);
 568                 hw_max = HWP_HIGHEST_PERF(cap);
 569                 range = hw_max - hw_min;
 570
 571                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 572                 adj_range = limits->min_perf_pct * range / 100;
 573                 min = hw_min + adj_range;
 574                 value &= ~HWP_MIN_PERF(~0L);
 575                 value |= HWP_MIN_PERF(min);
 576
 577                 adj_range = limits->max_perf_pct * range / 100;
 578                 max = hw_min + adj_range;
 579                 if (limits->no_turbo) {
 580                         hw_max = HWP_GUARANTEED_PERF(cap);
 581                         if (hw_max < max)
 582                                 max = hw_max;
 583                 }
 584
 585                 value &= ~HWP_MAX_PERF(~0L);
 586                 value |= HWP_MAX_PERF(max);
 587                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 588         }
 589 }
 590
 591 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 592 {
 593         if (hwp_active)
 594                 intel_pstate_hwp_set(policy->cpus);
 595
 596         return 0;
 597 }
 598
 599 static void intel_pstate_hwp_set_online_cpus(void)
 600 {
 601         get_online_cpus();
 602         intel_pstate_hwp_set(cpu_online_mask);
 603         put_online_cpus();
 604 }
 605
 606 /************************** debugfs begin ************************/
 607 static int pid_param_set(void *data, u64 val)
 608 {
 609         *(u32 *)data = val;
 610         intel_pstate_reset_all_pid();
 611         return 0;
 612 }
 613
 614 static int pid_param_get(void *data, u64 *val)
 615 {
 616         *val = *(u32 *)data;
 617         return 0;
 618 }
 619 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 620
 621 struct pid_param {
 622         char *name;
 623         void *value;
 624 };
 625
 626 static struct pid_param pid_files[] = {
 627         {"sample_rate_ms", &pid_params.sample_rate_ms},
 628         {"d_gain_pct", &pid_params.d_gain_pct},
 629         {"i_gain_pct", &pid_params.i_gain_pct},
 630         {"deadband", &pid_params.deadband},
 631         {"setpoint", &pid_params.setpoint},
 632         {"p_gain_pct", &pid_params.p_gain_pct},
 633         {NULL, NULL}
 634 };
 635
 636 static void __init intel_pstate_debug_expose_params(void)
 637 {
 638         struct dentry *debugfs_parent;
 639         int i = 0;
 640
 641         if (hwp_active ||
 642             pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load)
 643                 return;
 644
 645         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 646         if (IS_ERR_OR_NULL(debugfs_parent))
 647                 return;
 648         while (pid_files[i].name) {
 649                 debugfs_create_file(pid_files[i].name, 0660,
 650                                     debugfs_parent, pid_files[i].value,
 651                                     &fops_pid_param);
 652                 i++;
 653         }
 654 }
 655
 656 /************************** debugfs end ************************/
 657
 658 /************************** sysfs begin ************************/
 659 #define show_one(file_name, object)                                     \
 660         static ssize_t show_##file_name                                 \
 661         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 662         {                                                               \
 663                 return sprintf(buf, "%u\n", limits->object);            \
 664         }
 665
 666 static ssize_t show_turbo_pct(struct kobject *kobj,
 667                                 struct attribute *attr, char *buf)
 668 {
 669         struct cpudata *cpu;
 670         int total, no_turbo, turbo_pct;
 671         uint32_t turbo_fp;
 672
 673         cpu = all_cpu_data[0];
 674
 675         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 676         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 677         turbo_fp = div_fp(no_turbo, total);
 678         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 679         return sprintf(buf, "%u\n", turbo_pct);
 680 }
 681
 682 static ssize_t show_num_pstates(struct kobject *kobj,
 683                                 struct attribute *attr, char *buf)
 684 {
 685         struct cpudata *cpu;
 686         int total;
 687
 688         cpu = all_cpu_data[0];
 689         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 690         return sprintf(buf, "%u\n", total);
 691 }
 692
 693 static ssize_t show_no_turbo(struct kobject *kobj,
 694                              struct attribute *attr, char *buf)
 695 {
 696         ssize_t ret;
 697
 698         update_turbo_state();
 699         if (limits->turbo_disabled)
 700                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
 701         else
 702                 ret = sprintf(buf, "%u\n", limits->no_turbo);
 703
 704         return ret;
 705 }
 706
 707 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
 708                               const char *buf, size_t count)
 709 {
 710         unsigned int input;
 711         int ret;
 712
 713         ret = sscanf(buf, "%u", &input);
 714         if (ret != 1)
 715                 return -EINVAL;
 716
 717         update_turbo_state();
 718         if (limits->turbo_disabled) {
 719                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
 720                 return -EPERM;
 721         }
 722
 723         limits->no_turbo = clamp_t(int, input, 0, 1);
 724
 725         if (hwp_active)
 726                 intel_pstate_hwp_set_online_cpus();
 727
 728         return count;
 729 }
 730
 731 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
 732                                   const char *buf, size_t count)
 733 {
 734         unsigned int input;
 735         int ret;
 736
 737         ret = sscanf(buf, "%u", &input);
 738         if (ret != 1)
 739                 return -EINVAL;
 740
 741         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
 742         limits->max_perf_pct = min(limits->max_policy_pct,
 743                                    limits->max_sysfs_pct);
 744         limits->max_perf_pct = max(limits->min_policy_pct,
 745                                    limits->max_perf_pct);
 746         limits->max_perf_pct = max(limits->min_perf_pct,
 747                                    limits->max_perf_pct);
 748         limits->max_perf = div_fp(limits->max_perf_pct, 100);
 749
 750         if (hwp_active)
 751                 intel_pstate_hwp_set_online_cpus();
 752         return count;
 753 }
 754
 755 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
 756                                   const char *buf, size_t count)
 757 {
 758         unsigned int input;
 759         int ret;
 760
 761         ret = sscanf(buf, "%u", &input);
 762         if (ret != 1)
 763                 return -EINVAL;
 764
 765         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
 766         limits->min_perf_pct = max(limits->min_policy_pct,
 767                                    limits->min_sysfs_pct);
 768         limits->min_perf_pct = min(limits->max_policy_pct,
 769                                    limits->min_perf_pct);
 770         limits->min_perf_pct = min(limits->max_perf_pct,
 771                                    limits->min_perf_pct);
 772         limits->min_perf = div_fp(limits->min_perf_pct, 100);
 773
 774         if (hwp_active)
 775                 intel_pstate_hwp_set_online_cpus();
 776         return count;
 777 }
 778
 779 show_one(max_perf_pct, max_perf_pct);
 780 show_one(min_perf_pct, min_perf_pct);
 781
 782 define_one_global_rw(no_turbo);
 783 define_one_global_rw(max_perf_pct);
 784 define_one_global_rw(min_perf_pct);
 785 define_one_global_ro(turbo_pct);
 786 define_one_global_ro(num_pstates);
 787
 788 static struct attribute *intel_pstate_attributes[] = {
 789         &no_turbo.attr,
 790         &max_perf_pct.attr,
 791         &min_perf_pct.attr,
 792         &turbo_pct.attr,
 793         &num_pstates.attr,
 794         NULL
 795 };
 796
 797 static struct attribute_group intel_pstate_attr_group = {
 798         .attrs = intel_pstate_attributes,
 799 };
 800
 801 static void __init intel_pstate_sysfs_expose_params(void)
 802 {
 803         struct kobject *intel_pstate_kobject;
 804         int rc;
 805
 806         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
 807                                                 &cpu_subsys.dev_root->kobj);
 808         BUG_ON(!intel_pstate_kobject);
 809         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
 810         BUG_ON(rc);
 811 }
 812 /************************** sysfs end ************************/
 813
 814 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
 815 {
 816         /* First disable HWP notification interrupt as we don't process them */
 817         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
 818                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
 819
 820         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
 821 }
 822
 823 static int atom_get_min_pstate(void)
 824 {
 825         u64 value;
 826
 827         rdmsrl(ATOM_RATIOS, value);
 828         return (value >> 8) & 0x7F;
 829 }
 830
 831 static int atom_get_max_pstate(void)
 832 {
 833         u64 value;
 834
 835         rdmsrl(ATOM_RATIOS, value);
 836         return (value >> 16) & 0x7F;
 837 }
 838
 839 static int atom_get_turbo_pstate(void)
 840 {
 841         u64 value;
 842
 843         rdmsrl(ATOM_TURBO_RATIOS, value);
 844         return value & 0x7F;
 845 }
 846
 847 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
 848 {
 849         u64 val;
 850         int32_t vid_fp;
 851         u32 vid;
 852
 853         val = (u64)pstate << 8;
 854         if (limits->no_turbo && !limits->turbo_disabled)
 855                 val |= (u64)1 << 32;
 856
 857         vid_fp = cpudata->vid.min + mul_fp(
 858                 int_tofp(pstate - cpudata->pstate.min_pstate),
 859                 cpudata->vid.ratio);
 860
 861         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
 862         vid = ceiling_fp(vid_fp);
 863
 864         if (pstate > cpudata->pstate.max_pstate)
 865                 vid = cpudata->vid.turbo;
 866
 867         return val | vid;
 868 }
 869
 870 static int silvermont_get_scaling(void)
 871 {
 872         u64 value;
 873         int i;
 874         /* Defined in Table 35-6 from SDM (Sept 2015) */
 875         static int silvermont_freq_table[] = {
 876                 83300, 100000, 133300, 116700, 80000};
 877
 878         rdmsrl(MSR_FSB_FREQ, value);
 879         i = value & 0x7;
 880         WARN_ON(i > 4);
 881
 882         return silvermont_freq_table[i];
 883 }
 884
 885 static int airmont_get_scaling(void)
 886 {
 887         u64 value;
 888         int i;
 889         /* Defined in Table 35-10 from SDM (Sept 2015) */
 890         static int airmont_freq_table[] = {
 891                 83300, 100000, 133300, 116700, 80000,
 892                 93300, 90000, 88900, 87500};
 893
 894         rdmsrl(MSR_FSB_FREQ, value);
 895         i = value & 0xF;
 896         WARN_ON(i > 8);
 897
 898         return airmont_freq_table[i];
 899 }
 900
 901 static void atom_get_vid(struct cpudata *cpudata)
 902 {
 903         u64 value;
 904
 905         rdmsrl(ATOM_VIDS, value);
 906         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
 907         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
 908         cpudata->vid.ratio = div_fp(
 909                 cpudata->vid.max - cpudata->vid.min,
 910                 int_tofp(cpudata->pstate.max_pstate -
 911                         cpudata->pstate.min_pstate));
 912
 913         rdmsrl(ATOM_TURBO_VIDS, value);
 914         cpudata->vid.turbo = value & 0x7f;
 915 }
 916
 917 static int core_get_min_pstate(void)
 918 {
 919         u64 value;
 920
 921         rdmsrl(MSR_PLATFORM_INFO, value);
 922         return (value >> 40) & 0xFF;
 923 }
 924
 925 static int core_get_max_pstate_physical(void)
 926 {
 927         u64 value;
 928
 929         rdmsrl(MSR_PLATFORM_INFO, value);
 930         return (value >> 8) & 0xFF;
 931 }
 932
 933 static int core_get_max_pstate(void)
 934 {
 935         u64 tar;
 936         u64 plat_info;
 937         int max_pstate;
 938         int err;
 939
 940         rdmsrl(MSR_PLATFORM_INFO, plat_info);
 941         max_pstate = (plat_info >> 8) & 0xFF;
 942
 943         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
 944         if (!err) {
 945                 /* Do some sanity checking for safety */
 946                 if (plat_info & 0x600000000) {
 947                         u64 tdp_ctrl;
 948                         u64 tdp_ratio;
 949                         int tdp_msr;
 950
 951                         err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
 952                         if (err)
 953                                 goto skip_tar;
 954
 955                         tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
 956                         err = rdmsrl_safe(tdp_msr, &tdp_ratio);
 957                         if (err)
 958                                 goto skip_tar;
 959
 960                         /* For level 1 and 2, bits[23:16] contain the ratio */
 961                         if (tdp_ctrl)
 962                                 tdp_ratio >>= 16;
 963
 964                         tdp_ratio &= 0xff; /* ratios are only 8 bits long */
 965                         if (tdp_ratio - 1 == tar) {
 966                                 max_pstate = tar;
 967                                 pr_debug("max_pstate=TAC %x\n", max_pstate);
 968                         } else {
 969                                 goto skip_tar;
 970                         }
 971                 }
 972         }
 973
 974 skip_tar:
 975         return max_pstate;
 976 }
 977
 978 static int core_get_turbo_pstate(void)
 979 {
 980         u64 value;
 981         int nont, ret;
 982
 983         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
 984         nont = core_get_max_pstate();
 985         ret = (value) & 255;
 986         if (ret <= nont)
 987                 ret = nont;
 988         return ret;
 989 }
 990
 991 static inline int core_get_scaling(void)
 992 {
 993         return 100000;
 994 }
 995
 996 static u64 core_get_val(struct cpudata *cpudata, int pstate)
 997 {
 998         u64 val;
 999
1000         val = (u64)pstate << 8;
1001         if (limits->no_turbo && !limits->turbo_disabled)
1002                 val |= (u64)1 << 32;
1003
1004         return val;
1005 }
1006
1007 static int knl_get_turbo_pstate(void)
1008 {
1009         u64 value;
1010         int nont, ret;
1011
1012         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1013         nont = core_get_max_pstate();
1014         ret = (((value) >> 8) & 0xFF);
1015         if (ret <= nont)
1016                 ret = nont;
1017         return ret;
1018 }
1019
1020 static struct cpu_defaults core_params = {
1021         .pid_policy = {
1022                 .sample_rate_ms = 10,
1023                 .deadband = 0,
1024                 .setpoint = 97,
1025                 .p_gain_pct = 20,
1026                 .d_gain_pct = 0,
1027                 .i_gain_pct = 0,
1028         },
1029         .funcs = {
1030                 .get_max = core_get_max_pstate,
1031                 .get_max_physical = core_get_max_pstate_physical,
1032                 .get_min = core_get_min_pstate,
1033                 .get_turbo = core_get_turbo_pstate,
1034                 .get_scaling = core_get_scaling,
1035                 .get_val = core_get_val,
1036                 .get_target_pstate = get_target_pstate_use_performance,
1037         },
1038 };
1039
1040 static const struct cpu_defaults silvermont_params = {
1041         .pid_policy = {
1042                 .sample_rate_ms = 10,
1043                 .deadband = 0,
1044                 .setpoint = 60,
1045                 .p_gain_pct = 14,
1046                 .d_gain_pct = 0,
1047                 .i_gain_pct = 4,
1048         },
1049         .funcs = {
1050                 .get_max = atom_get_max_pstate,
1051                 .get_max_physical = atom_get_max_pstate,
1052                 .get_min = atom_get_min_pstate,
1053                 .get_turbo = atom_get_turbo_pstate,
1054                 .get_val = atom_get_val,
1055                 .get_scaling = silvermont_get_scaling,
1056                 .get_vid = atom_get_vid,
1057                 .get_target_pstate = get_target_pstate_use_cpu_load,
1058         },
1059 };
1060
1061 static const struct cpu_defaults airmont_params = {
1062         .pid_policy = {
1063                 .sample_rate_ms = 10,
1064                 .deadband = 0,
1065                 .setpoint = 60,
1066                 .p_gain_pct = 14,
1067                 .d_gain_pct = 0,
1068                 .i_gain_pct = 4,
1069         },
1070         .funcs = {
1071                 .get_max = atom_get_max_pstate,
1072                 .get_max_physical = atom_get_max_pstate,
1073                 .get_min = atom_get_min_pstate,
1074                 .get_turbo = atom_get_turbo_pstate,
1075                 .get_val = atom_get_val,
1076                 .get_scaling = airmont_get_scaling,
1077                 .get_vid = atom_get_vid,
1078                 .get_target_pstate = get_target_pstate_use_cpu_load,
1079         },
1080 };
1081
1082 static const struct cpu_defaults knl_params = {
1083         .pid_policy = {
1084                 .sample_rate_ms = 10,
1085                 .deadband = 0,
1086                 .setpoint = 97,
1087                 .p_gain_pct = 20,
1088                 .d_gain_pct = 0,
1089                 .i_gain_pct = 0,
1090         },
1091         .funcs = {
1092                 .get_max = core_get_max_pstate,
1093                 .get_max_physical = core_get_max_pstate_physical,
1094                 .get_min = core_get_min_pstate,
1095                 .get_turbo = knl_get_turbo_pstate,
1096                 .get_scaling = core_get_scaling,
1097                 .get_val = core_get_val,
1098                 .get_target_pstate = get_target_pstate_use_performance,
1099         },
1100 };
1101
1102 static const struct cpu_defaults bxt_params = {
1103         .pid_policy = {
1104                 .sample_rate_ms = 10,
1105                 .deadband = 0,
1106                 .setpoint = 60,
1107                 .p_gain_pct = 14,
1108                 .d_gain_pct = 0,
1109                 .i_gain_pct = 4,
1110         },
1111         .funcs = {
1112                 .get_max = core_get_max_pstate,
1113                 .get_max_physical = core_get_max_pstate_physical,
1114                 .get_min = core_get_min_pstate,
1115                 .get_turbo = core_get_turbo_pstate,
1116                 .get_scaling = core_get_scaling,
1117                 .get_val = core_get_val,
1118                 .get_target_pstate = get_target_pstate_use_cpu_load,
1119         },
1120 };
1121
1122 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1123 {
1124         int max_perf = cpu->pstate.turbo_pstate;
1125         int max_perf_adj;
1126         int min_perf;
1127
1128         if (limits->no_turbo || limits->turbo_disabled)
1129                 max_perf = cpu->pstate.max_pstate;
1130
1131         /*
1132          * performance can be limited by user through sysfs, by cpufreq
1133          * policy, or by cpu specific default values determined through
1134          * experimentation.
1135          */
1136         max_perf_adj = fp_toint(max_perf * limits->max_perf);
1137         *max = clamp_t(int, max_perf_adj,
1138                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1139
1140         min_perf = fp_toint(max_perf * limits->min_perf);
1141         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1142 }
1143
1144 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1145 {
1146         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1147         cpu->pstate.current_pstate = pstate;
1148         /*
1149          * Generally, there is no guarantee that this code will always run on
1150          * the CPU being updated, so force the register update to run on the
1151          * right CPU.
1152          */
1153         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1154                       pstate_funcs.get_val(cpu, pstate));
1155 }
1156
1157 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1158 {
1159         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1160 }
1161
1162 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1163 {
1164         int min_pstate, max_pstate;
1165
1166         update_turbo_state();
1167         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1168         intel_pstate_set_pstate(cpu, max_pstate);
1169 }
1170
1171 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1172 {
1173         cpu->pstate.min_pstate = pstate_funcs.get_min();
1174         cpu->pstate.max_pstate = pstate_funcs.get_max();
1175         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1176         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1177         cpu->pstate.scaling = pstate_funcs.get_scaling();
1178
1179         if (pstate_funcs.get_vid)
1180                 pstate_funcs.get_vid(cpu);
1181
1182         intel_pstate_set_min_pstate(cpu);
1183 }
1184
1185 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1186 {
1187         struct sample *sample = &cpu->sample;
1188
1189         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1190 }
1191
1192 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1193 {
1194         u64 aperf, mperf;
1195         unsigned long flags;
1196         u64 tsc;
1197
1198         local_irq_save(flags);
1199         rdmsrl(MSR_IA32_APERF, aperf);
1200         rdmsrl(MSR_IA32_MPERF, mperf);
1201         tsc = rdtsc();
1202         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1203                 local_irq_restore(flags);
1204                 return false;
1205         }
1206         local_irq_restore(flags);
1207
1208         cpu->last_sample_time = cpu->sample.time;
1209         cpu->sample.time = time;
1210         cpu->sample.aperf = aperf;
1211         cpu->sample.mperf = mperf;
1212         cpu->sample.tsc =  tsc;
1213         cpu->sample.aperf -= cpu->prev_aperf;
1214         cpu->sample.mperf -= cpu->prev_mperf;
1215         cpu->sample.tsc -= cpu->prev_tsc;
1216
1217         cpu->prev_aperf = aperf;
1218         cpu->prev_mperf = mperf;
1219         cpu->prev_tsc = tsc;
1220         /*
1221          * First time this function is invoked in a given cycle, all of the
1222          * previous sample data fields are equal to zero or stale and they must
1223          * be populated with meaningful numbers for things to work, so assume
1224          * that sample.time will always be reset before setting the utilization
1225          * update hook and make the caller skip the sample then.
1226          */
1227         return !!cpu->last_sample_time;
1228 }
1229
1230 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1231 {
1232         return mul_ext_fp(cpu->sample.core_avg_perf,
1233                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1234 }
1235
1236 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1237 {
1238         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1239                           cpu->sample.core_avg_perf);
1240 }
1241
1242 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1243 {
1244         struct sample *sample = &cpu->sample;
1245         int32_t busy_frac, boost;
1246         int target, avg_pstate;
1247
1248         busy_frac = div_fp(sample->mperf, sample->tsc);
1249
1250         boost = cpu->iowait_boost;
1251         cpu->iowait_boost >>= 1;
1252
1253         if (busy_frac < boost)
1254                 busy_frac = boost;
1255
1256         sample->busy_scaled = busy_frac * 100;
1257
1258         target = limits->no_turbo || limits->turbo_disabled ?
1259                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1260         target += target >> 2;
1261         target = mul_fp(target, busy_frac);
1262         if (target < cpu->pstate.min_pstate)
1263                 target = cpu->pstate.min_pstate;
1264
1265         /*
1266          * If the average P-state during the previous cycle was higher than the
1267          * current target, add 50% of the difference to the target to reduce
1268          * possible performance oscillations and offset possible performance
1269          * loss related to moving the workload from one CPU to another within
1270          * a package/module.
1271          */
1272         avg_pstate = get_avg_pstate(cpu);
1273         if (avg_pstate > target)
1274                 target += (avg_pstate - target) >> 1;
1275
1276         return target;
1277 }
1278
1279 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1280 {
1281         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1282         u64 duration_ns;
1283
1284         /*
1285          * perf_scaled is the ratio of the average P-state during the last
1286          * sampling period to the P-state requested last time (in percent).
1287          *
1288          * That measures the system's response to the previous P-state
1289          * selection.
1290          */
1291         max_pstate = cpu->pstate.max_pstate_physical;
1292         current_pstate = cpu->pstate.current_pstate;
1293         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1294                                div_fp(100 * max_pstate, current_pstate));
1295
1296         /*
1297          * Since our utilization update callback will not run unless we are
1298          * in C0, check if the actual elapsed time is significantly greater (3x)
1299          * than our sample interval.  If it is, then we were idle for a long
1300          * enough period of time to adjust our performance metric.
1301          */
1302         duration_ns = cpu->sample.time - cpu->last_sample_time;
1303         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1304                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1305                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1306         } else {
1307                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1308                 if (sample_ratio < int_tofp(1))
1309                         perf_scaled = 0;
1310         }
1311
1312         cpu->sample.busy_scaled = perf_scaled;
1313         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1314 }
1315
1316 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1317 {
1318         int max_perf, min_perf;
1319
1320         update_turbo_state();
1321
1322         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1323         pstate = clamp_t(int, pstate, min_perf, max_perf);
1324         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1325         if (pstate == cpu->pstate.current_pstate)
1326                 return;
1327
1328         cpu->pstate.current_pstate = pstate;
1329         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1330 }
1331
1332 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1333 {
1334         int from, target_pstate;
1335         struct sample *sample;
1336
1337         from = cpu->pstate.current_pstate;
1338
1339         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1340                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1341
1342         intel_pstate_update_pstate(cpu, target_pstate);
1343
1344         sample = &cpu->sample;
1345         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1346                 fp_toint(sample->busy_scaled),
1347                 from,
1348                 cpu->pstate.current_pstate,
1349                 sample->mperf,
1350                 sample->aperf,
1351                 sample->tsc,
1352                 get_avg_frequency(cpu),
1353                 fp_toint(cpu->iowait_boost * 100));
1354 }
1355
1356 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1357                                      unsigned int flags)
1358 {
1359         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1360         u64 delta_ns;
1361
1362         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1363                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1364                         cpu->iowait_boost = int_tofp(1);
1365                 } else if (cpu->iowait_boost) {
1366                         /* Clear iowait_boost if the CPU may have been idle. */
1367                         delta_ns = time - cpu->last_update;
1368                         if (delta_ns > TICK_NSEC)
1369                                 cpu->iowait_boost = 0;
1370                 }
1371                 cpu->last_update = time;
1372         }
1373
1374         delta_ns = time - cpu->sample.time;
1375         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1376                 bool sample_taken = intel_pstate_sample(cpu, time);
1377
1378                 if (sample_taken) {
1379                         intel_pstate_calc_avg_perf(cpu);
1380                         if (!hwp_active)
1381                                 intel_pstate_adjust_busy_pstate(cpu);
1382                 }
1383         }
1384 }
1385
1386 #define ICPU(model, policy) \
1387         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1388                         (unsigned long)&policy }
1389
1390 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1391         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1392         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1393         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1394         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1395         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1396         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1397         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1398         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1399         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1400         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1401         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1402         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1403         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1404         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1405         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1406         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1407         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1408         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1409         {}
1410 };
1411 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1412
1413 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1414         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1415         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1416         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1417         {}
1418 };
1419
1420 static int intel_pstate_init_cpu(unsigned int cpunum)
1421 {
1422         struct cpudata *cpu;
1423
1424         if (!all_cpu_data[cpunum])
1425                 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
1426                                                GFP_KERNEL);
1427         if (!all_cpu_data[cpunum])
1428                 return -ENOMEM;
1429
1430         cpu = all_cpu_data[cpunum];
1431
1432         cpu->cpu = cpunum;
1433
1434         if (hwp_active) {
1435                 intel_pstate_hwp_enable(cpu);
1436                 pid_params.sample_rate_ms = 50;
1437                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1438         }
1439
1440         intel_pstate_get_cpu_pstates(cpu);
1441
1442         intel_pstate_busy_pid_reset(cpu);
1443
1444         pr_debug("controlling: cpu %d\n", cpunum);
1445
1446         return 0;
1447 }
1448
1449 static unsigned int intel_pstate_get(unsigned int cpu_num)
1450 {
1451         struct cpudata *cpu = all_cpu_data[cpu_num];
1452
1453         return cpu ? get_avg_frequency(cpu) : 0;
1454 }
1455
1456 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1457 {
1458         struct cpudata *cpu = all_cpu_data[cpu_num];
1459
1460         if (cpu->update_util_set)
1461                 return;
1462
1463         /* Prevent intel_pstate_update_util() from using stale data. */
1464         cpu->sample.time = 0;
1465         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1466                                      intel_pstate_update_util);
1467         cpu->update_util_set = true;
1468 }
1469
1470 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1471 {
1472         struct cpudata *cpu_data = all_cpu_data[cpu];
1473
1474         if (!cpu_data->update_util_set)
1475                 return;
1476
1477         cpufreq_remove_update_util_hook(cpu);
1478         cpu_data->update_util_set = false;
1479         synchronize_sched();
1480 }
1481
1482 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1483 {
1484         limits->no_turbo = 0;
1485         limits->turbo_disabled = 0;
1486         limits->max_perf_pct = 100;
1487         limits->max_perf = int_tofp(1);
1488         limits->min_perf_pct = 100;
1489         limits->min_perf = int_tofp(1);
1490         limits->max_policy_pct = 100;
1491         limits->max_sysfs_pct = 100;
1492         limits->min_policy_pct = 0;
1493         limits->min_sysfs_pct = 0;
1494 }
1495
1496 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1497 {
1498         struct cpudata *cpu;
1499
1500         if (!policy->cpuinfo.max_freq)
1501                 return -ENODEV;
1502
1503         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1504                  policy->cpuinfo.max_freq, policy->max);
1505
1506         cpu = all_cpu_data[policy->cpu];
1507         cpu->policy = policy->policy;
1508
1509         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1510             policy->max < policy->cpuinfo.max_freq &&
1511             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1512                 pr_debug("policy->max > max non turbo frequency\n");
1513                 policy->max = policy->cpuinfo.max_freq;
1514         }
1515
1516         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1517                 limits = &performance_limits;
1518                 if (policy->max >= policy->cpuinfo.max_freq) {
1519                         pr_debug("set performance\n");
1520                         intel_pstate_set_performance_limits(limits);
1521                         goto out;
1522                 }
1523         } else {
1524                 pr_debug("set powersave\n");
1525                 limits = &powersave_limits;
1526         }
1527
1528         limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
1529         limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
1530         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1531                                               policy->cpuinfo.max_freq);
1532         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100);
1533
1534         /* Normalize user input to [min_policy_pct, max_policy_pct] */
1535         limits->min_perf_pct = max(limits->min_policy_pct,
1536                                    limits->min_sysfs_pct);
1537         limits->min_perf_pct = min(limits->max_policy_pct,
1538                                    limits->min_perf_pct);
1539         limits->max_perf_pct = min(limits->max_policy_pct,
1540                                    limits->max_sysfs_pct);
1541         limits->max_perf_pct = max(limits->min_policy_pct,
1542                                    limits->max_perf_pct);
1543
1544         /* Make sure min_perf_pct <= max_perf_pct */
1545         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1546
1547         limits->min_perf = div_fp(limits->min_perf_pct, 100);
1548         limits->max_perf = div_fp(limits->max_perf_pct, 100);
1549         limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
1550
1551  out:
1552         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1553                 /*
1554                  * NOHZ_FULL CPUs need this as the governor callback may not
1555                  * be invoked on them.
1556                  */
1557                 intel_pstate_clear_update_util_hook(policy->cpu);
1558                 intel_pstate_max_within_limits(cpu);
1559         }
1560
1561         intel_pstate_set_update_util_hook(policy->cpu);
1562
1563         intel_pstate_hwp_set_policy(policy);
1564
1565         return 0;
1566 }
1567
1568 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1569 {
1570         cpufreq_verify_within_cpu_limits(policy);
1571
1572         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1573             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1574                 return -EINVAL;
1575
1576         return 0;
1577 }
1578
1579 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1580 {
1581         int cpu_num = policy->cpu;
1582         struct cpudata *cpu = all_cpu_data[cpu_num];
1583
1584         pr_debug("CPU %d exiting\n", cpu_num);
1585
1586         intel_pstate_clear_update_util_hook(cpu_num);
1587
1588         if (hwp_active)
1589                 return;
1590
1591         intel_pstate_set_min_pstate(cpu);
1592 }
1593
1594 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1595 {
1596         struct cpudata *cpu;
1597         int rc;
1598
1599         rc = intel_pstate_init_cpu(policy->cpu);
1600         if (rc)
1601                 return rc;
1602
1603         cpu = all_cpu_data[policy->cpu];
1604
1605         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
1606                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1607         else
1608                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1609
1610         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1611         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1612
1613         /* cpuinfo and default policy values */
1614         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1615         update_turbo_state();
1616         policy->cpuinfo.max_freq = limits->turbo_disabled ?
1617                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1618         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1619
1620         intel_pstate_init_acpi_perf_limits(policy);
1621         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1622         cpumask_set_cpu(policy->cpu, policy->cpus);
1623
1624         return 0;
1625 }
1626
1627 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1628 {
1629         intel_pstate_exit_perf_limits(policy);
1630
1631         return 0;
1632 }
1633
1634 static struct cpufreq_driver intel_pstate_driver = {
1635         .flags          = CPUFREQ_CONST_LOOPS,
1636         .verify         = intel_pstate_verify_policy,
1637         .setpolicy      = intel_pstate_set_policy,
1638         .resume         = intel_pstate_hwp_set_policy,
1639         .get            = intel_pstate_get,
1640         .init           = intel_pstate_cpu_init,
1641         .exit           = intel_pstate_cpu_exit,
1642         .stop_cpu       = intel_pstate_stop_cpu,
1643         .name           = "intel_pstate",
1644 };
1645
1646 static int no_load __initdata;
1647 static int no_hwp __initdata;
1648 static int hwp_only __initdata;
1649 static unsigned int force_load __initdata;
1650
1651 static int __init intel_pstate_msrs_not_valid(void)
1652 {
1653         if (!pstate_funcs.get_max() ||
1654             !pstate_funcs.get_min() ||
1655             !pstate_funcs.get_turbo())
1656                 return -ENODEV;
1657
1658         return 0;
1659 }
1660
1661 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
1662 {
1663         pid_params.sample_rate_ms = policy->sample_rate_ms;
1664         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
1665         pid_params.p_gain_pct = policy->p_gain_pct;
1666         pid_params.i_gain_pct = policy->i_gain_pct;
1667         pid_params.d_gain_pct = policy->d_gain_pct;
1668         pid_params.deadband = policy->deadband;
1669         pid_params.setpoint = policy->setpoint;
1670 }
1671
1672 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
1673 {
1674         pstate_funcs.get_max   = funcs->get_max;
1675         pstate_funcs.get_max_physical = funcs->get_max_physical;
1676         pstate_funcs.get_min   = funcs->get_min;
1677         pstate_funcs.get_turbo = funcs->get_turbo;
1678         pstate_funcs.get_scaling = funcs->get_scaling;
1679         pstate_funcs.get_val   = funcs->get_val;
1680         pstate_funcs.get_vid   = funcs->get_vid;
1681         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
1682
1683 }
1684
1685 #ifdef CONFIG_ACPI
1686
1687 static bool __init intel_pstate_no_acpi_pss(void)
1688 {
1689         int i;
1690
1691         for_each_possible_cpu(i) {
1692                 acpi_status status;
1693                 union acpi_object *pss;
1694                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1695                 struct acpi_processor *pr = per_cpu(processors, i);
1696
1697                 if (!pr)
1698                         continue;
1699
1700                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1701                 if (ACPI_FAILURE(status))
1702                         continue;
1703
1704                 pss = buffer.pointer;
1705                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1706                         kfree(pss);
1707                         return false;
1708                 }
1709
1710                 kfree(pss);
1711         }
1712
1713         return true;
1714 }
1715
1716 static bool __init intel_pstate_has_acpi_ppc(void)
1717 {
1718         int i;
1719
1720         for_each_possible_cpu(i) {
1721                 struct acpi_processor *pr = per_cpu(processors, i);
1722
1723                 if (!pr)
1724                         continue;
1725                 if (acpi_has_method(pr->handle, "_PPC"))
1726                         return true;
1727         }
1728         return false;
1729 }
1730
1731 enum {
1732         PSS,
1733         PPC,
1734 };
1735
1736 struct hw_vendor_info {
1737         u16  valid;
1738         char oem_id[ACPI_OEM_ID_SIZE];
1739         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1740         int  oem_pwr_table;
1741 };
1742
1743 /* Hardware vendor-specific info that has its own power management modes */
1744 static struct hw_vendor_info vendor_info[] __initdata = {
1745         {1, "HP    ", "ProLiant", PSS},
1746         {1, "ORACLE", "X4-2    ", PPC},
1747         {1, "ORACLE", "X4-2L   ", PPC},
1748         {1, "ORACLE", "X4-2B   ", PPC},
1749         {1, "ORACLE", "X3-2    ", PPC},
1750         {1, "ORACLE", "X3-2L   ", PPC},
1751         {1, "ORACLE", "X3-2B   ", PPC},
1752         {1, "ORACLE", "X4470M2 ", PPC},
1753         {1, "ORACLE", "X4270M3 ", PPC},
1754         {1, "ORACLE", "X4270M2 ", PPC},
1755         {1, "ORACLE", "X4170M2 ", PPC},
1756         {1, "ORACLE", "X4170 M3", PPC},
1757         {1, "ORACLE", "X4275 M3", PPC},
1758         {1, "ORACLE", "X6-2    ", PPC},
1759         {1, "ORACLE", "Sudbury ", PPC},
1760         {0, "", ""},
1761 };
1762
1763 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
1764 {
1765         struct acpi_table_header hdr;
1766         struct hw_vendor_info *v_info;
1767         const struct x86_cpu_id *id;
1768         u64 misc_pwr;
1769
1770         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1771         if (id) {
1772                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1773                 if ( misc_pwr & (1 << 8))
1774                         return true;
1775         }
1776
1777         if (acpi_disabled ||
1778             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1779                 return false;
1780
1781         for (v_info = vendor_info; v_info->valid; v_info++) {
1782                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1783                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1784                                                 ACPI_OEM_TABLE_ID_SIZE))
1785                         switch (v_info->oem_pwr_table) {
1786                         case PSS:
1787                                 return intel_pstate_no_acpi_pss();
1788                         case PPC:
1789                                 return intel_pstate_has_acpi_ppc() &&
1790                                         (!force_load);
1791                         }
1792         }
1793
1794         return false;
1795 }
1796 #else /* CONFIG_ACPI not enabled */
1797 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1798 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1799 #endif /* CONFIG_ACPI */
1800
1801 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
1802         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
1803         {}
1804 };
1805
1806 static int __init intel_pstate_init(void)
1807 {
1808         int cpu, rc = 0;
1809         const struct x86_cpu_id *id;
1810         struct cpu_defaults *cpu_def;
1811
1812         if (no_load)
1813                 return -ENODEV;
1814
1815         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
1816                 copy_cpu_funcs(&core_params.funcs);
1817                 hwp_active++;
1818                 goto hwp_cpu_matched;
1819         }
1820
1821         id = x86_match_cpu(intel_pstate_cpu_ids);
1822         if (!id)
1823                 return -ENODEV;
1824
1825         cpu_def = (struct cpu_defaults *)id->driver_data;
1826
1827         copy_pid_params(&cpu_def->pid_policy);
1828         copy_cpu_funcs(&cpu_def->funcs);
1829
1830         if (intel_pstate_msrs_not_valid())
1831                 return -ENODEV;
1832
1833 hwp_cpu_matched:
1834         /*
1835          * The Intel pstate driver will be ignored if the platform
1836          * firmware has its own power management modes.
1837          */
1838         if (intel_pstate_platform_pwr_mgmt_exists())
1839                 return -ENODEV;
1840
1841         pr_info("Intel P-state driver initializing\n");
1842
1843         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1844         if (!all_cpu_data)
1845                 return -ENOMEM;
1846
1847         if (!hwp_active && hwp_only)
1848                 goto out;
1849
1850         rc = cpufreq_register_driver(&intel_pstate_driver);
1851         if (rc)
1852                 goto out;
1853
1854         intel_pstate_debug_expose_params();
1855         intel_pstate_sysfs_expose_params();
1856
1857         if (hwp_active)
1858                 pr_info("HWP enabled\n");
1859
1860         return rc;
1861 out:
1862         get_online_cpus();
1863         for_each_online_cpu(cpu) {
1864                 if (all_cpu_data[cpu]) {
1865                         intel_pstate_clear_update_util_hook(cpu);
1866                         kfree(all_cpu_data[cpu]);
1867                 }
1868         }
1869
1870         put_online_cpus();
1871         vfree(all_cpu_data);
1872         return -ENODEV;
1873 }
1874 device_initcall(intel_pstate_init);
1875
1876 static int __init intel_pstate_setup(char *str)
1877 {
1878         if (!str)
1879                 return -EINVAL;
1880
1881         if (!strcmp(str, "disable"))
1882                 no_load = 1;
1883         if (!strcmp(str, "no_hwp")) {
1884                 pr_info("HWP disabled\n");
1885                 no_hwp = 1;
1886         }
1887         if (!strcmp(str, "force"))
1888                 force_load = 1;
1889         if (!strcmp(str, "hwp_only"))
1890                 hwp_only = 1;
1891
1892 #ifdef CONFIG_ACPI
1893         if (!strcmp(str, "support_acpi_ppc"))
1894                 acpi_ppc = true;
1895 #endif
1896
1897         return 0;
1898 }
1899 early_param("intel_pstate", intel_pstate_setup);
1900
1901 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1902 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1903 MODULE_LICENSE("GPL");