arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47
  48 MODULE_AUTHOR("Qumranet");
  49 MODULE_LICENSE("GPL");
  50
  51 #ifdef MODULE
  52 static const struct x86_cpu_id svm_cpu_id[] = {
  53         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  54         {}
  55 };
  56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  57 #endif
  58
  59 #define IOPM_ALLOC_ORDER 2
  60 #define MSRPM_ALLOC_ORDER 1
  61
  62 #define SEG_TYPE_LDT 2
  63 #define SEG_TYPE_BUSY_TSS16 3
  64
  65 #define SVM_FEATURE_LBRV           (1 <<  1)
  66 #define SVM_FEATURE_SVML           (1 <<  2)
  67 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  68 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  69 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  70 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  71 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  82
  83 /*
  84  * Set osvw_len to higher value when updated Revision Guides
  85  * are published and we know what the new status bits are
  86  */
  87 static uint64_t osvw_len = 4, osvw_status;
  88
  89 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  90 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  91
  92 static const struct svm_direct_access_msrs {
  93         u32 index;   /* Index of the MSR */
  94         bool always; /* True if intercept is initially cleared */
  95 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  96         { .index = MSR_STAR,                            .always = true  },
  97         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  98 #ifdef CONFIG_X86_64
  99         { .index = MSR_GS_BASE,                         .always = true  },
 100         { .index = MSR_FS_BASE,                         .always = true  },
 101         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 102         { .index = MSR_LSTAR,                           .always = true  },
 103         { .index = MSR_CSTAR,                           .always = true  },
 104         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 105 #endif
 106         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 107         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 108         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 109         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 110         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 111         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 112         { .index = MSR_EFER,                            .always = false },
 113         { .index = MSR_IA32_CR_PAT,                     .always = false },
 114         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 115         { .index = MSR_INVALID,                         .always = false },
 116 };
 117
 118 /*
 119  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 120  * pause_filter_count: On processors that support Pause filtering(indicated
 121  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 122  *      count value. On VMRUN this value is loaded into an internal counter.
 123  *      Each time a pause instruction is executed, this counter is decremented
 124  *      until it reaches zero at which time a #VMEXIT is generated if pause
 125  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 126  *      Intercept Filtering for more details.
 127  *      This also indicate if ple logic enabled.
 128  *
 129  * pause_filter_thresh: In addition, some processor families support advanced
 130  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 131  *      the amount of time a guest is allowed to execute in a pause loop.
 132  *      In this mode, a 16-bit pause filter threshold field is added in the
 133  *      VMCB. The threshold value is a cycle count that is used to reset the
 134  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 135  *      count value from VMCB into an internal counter. Then, on each pause
 136  *      instruction the hardware checks the elapsed number of cycles since
 137  *      the most recent pause instruction against the pause filter threshold.
 138  *      If the elapsed cycle count is greater than the pause filter threshold,
 139  *      then the internal pause count is reloaded from the VMCB and execution
 140  *      continues. If the elapsed cycle count is less than the pause filter
 141  *      threshold, then the internal pause count is decremented. If the count
 142  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 143  *      triggered. If advanced pause filtering is supported and pause filter
 144  *      threshold field is set to zero, the filter will operate in the simpler,
 145  *      count only mode.
 146  */
 147
 148 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 149 module_param(pause_filter_thresh, ushort, 0444);
 150
 151 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 152 module_param(pause_filter_count, ushort, 0444);
 153
 154 /* Default doubles per-vcpu window every exit. */
 155 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 156 module_param(pause_filter_count_grow, ushort, 0444);
 157
 158 /* Default resets per-vcpu window every exit to pause_filter_count. */
 159 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 160 module_param(pause_filter_count_shrink, ushort, 0444);
 161
 162 /* Default is to compute the maximum so we can never overflow. */
 163 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 164 module_param(pause_filter_count_max, ushort, 0444);
 165
 166 /*
 167  * Use nested page tables by default.  Note, NPT may get forced off by
 168  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 169  */
 170 bool npt_enabled = true;
 171 module_param_named(npt, npt_enabled, bool, 0444);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 /* enable/disable SEV-ES support */
 194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 195 module_param(sev_es, int, 0444);
 196
 197 bool __read_mostly dump_invalid_vmcb;
 198 module_param(dump_invalid_vmcb, bool, 0644);
 199
 200 static bool svm_gp_erratum_intercept = true;
 201
 202 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 203
 204 static unsigned long iopm_base;
 205
 206 struct kvm_ldttss_desc {
 207         u16 limit0;
 208         u16 base0;
 209         unsigned base1:8, type:5, dpl:2, p:1;
 210         unsigned limit1:4, zero0:3, g:1, base2:8;
 211         u32 base3;
 212         u32 zero1;
 213 } __attribute__((packed));
 214
 215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 216
 217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 218
 219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 220 #define MSRS_RANGE_SIZE 2048
 221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 222
 223 u32 svm_msrpm_offset(u32 msr)
 224 {
 225         u32 offset;
 226         int i;
 227
 228         for (i = 0; i < NUM_MSR_MAPS; i++) {
 229                 if (msr < msrpm_ranges[i] ||
 230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 231                         continue;
 232
 233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 235
 236                 /* Now we have the u8 offset - but need the u32 offset */
 237                 return offset / 4;
 238         }
 239
 240         /* MSR not in any range */
 241         return MSR_INVALID;
 242 }
 243
 244 #define MAX_INST_SIZE 15
 245
 246 static int get_max_npt_level(void)
 247 {
 248 #ifdef CONFIG_X86_64
 249         return PT64_ROOT_4LEVEL;
 250 #else
 251         return PT32E_ROOT_LEVEL;
 252 #endif
 253 }
 254
 255 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 256 {
 257         struct vcpu_svm *svm = to_svm(vcpu);
 258         u64 old_efer = vcpu->arch.efer;
 259         vcpu->arch.efer = efer;
 260
 261         if (!npt_enabled) {
 262                 /* Shadow paging assumes NX to be available.  */
 263                 efer |= EFER_NX;
 264
 265                 if (!(efer & EFER_LMA))
 266                         efer &= ~EFER_LME;
 267         }
 268
 269         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 270                 if (!(efer & EFER_SVME)) {
 271                         svm_leave_nested(svm);
 272                         svm_set_gif(svm, true);
 273                         /* #GP intercept is still needed for vmware backdoor */
 274                         if (!enable_vmware_backdoor)
 275                                 clr_exception_intercept(svm, GP_VECTOR);
 276
 277                         /*
 278                          * Free the nested guest state, unless we are in SMM.
 279                          * In this case we will return to the nested guest
 280                          * as soon as we leave SMM.
 281                          */
 282                         if (!is_smm(&svm->vcpu))
 283                                 svm_free_nested(svm);
 284
 285                 } else {
 286                         int ret = svm_allocate_nested(svm);
 287
 288                         if (ret) {
 289                                 vcpu->arch.efer = old_efer;
 290                                 return ret;
 291                         }
 292
 293                         if (svm_gp_erratum_intercept)
 294                                 set_exception_intercept(svm, GP_VECTOR);
 295                 }
 296         }
 297
 298         svm->vmcb->save.efer = efer | EFER_SVME;
 299         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 300         return 0;
 301 }
 302
 303 static int is_external_interrupt(u32 info)
 304 {
 305         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 306         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 307 }
 308
 309 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 310 {
 311         struct vcpu_svm *svm = to_svm(vcpu);
 312         u32 ret = 0;
 313
 314         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 315                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 316         return ret;
 317 }
 318
 319 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (mask == 0)
 324                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 325         else
 326                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 327
 328 }
 329
 330 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 331 {
 332         struct vcpu_svm *svm = to_svm(vcpu);
 333
 334         /*
 335          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 336          * the type of exit and the #VC handler in the guest.
 337          */
 338         if (sev_es_guest(vcpu->kvm))
 339                 goto done;
 340
 341         if (nrips && svm->vmcb->control.next_rip != 0) {
 342                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 343                 svm->next_rip = svm->vmcb->control.next_rip;
 344         }
 345
 346         if (!svm->next_rip) {
 347                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 348                         return 0;
 349         } else {
 350                 kvm_rip_write(vcpu, svm->next_rip);
 351         }
 352
 353 done:
 354         svm_set_interrupt_shadow(vcpu, 0);
 355
 356         return 1;
 357 }
 358
 359 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 360 {
 361         struct vcpu_svm *svm = to_svm(vcpu);
 362         unsigned nr = vcpu->arch.exception.nr;
 363         bool has_error_code = vcpu->arch.exception.has_error_code;
 364         u32 error_code = vcpu->arch.exception.error_code;
 365
 366         kvm_deliver_exception_payload(&svm->vcpu);
 367
 368         if (nr == BP_VECTOR && !nrips) {
 369                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 370
 371                 /*
 372                  * For guest debugging where we have to reinject #BP if some
 373                  * INT3 is guest-owned:
 374                  * Emulate nRIP by moving RIP forward. Will fail if injection
 375                  * raises a fault that is not intercepted. Still better than
 376                  * failing in all cases.
 377                  */
 378                 (void)skip_emulated_instruction(&svm->vcpu);
 379                 rip = kvm_rip_read(&svm->vcpu);
 380                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 381                 svm->int3_injected = rip - old_rip;
 382         }
 383
 384         svm->vmcb->control.event_inj = nr
 385                 | SVM_EVTINJ_VALID
 386                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 387                 | SVM_EVTINJ_TYPE_EXEPT;
 388         svm->vmcb->control.event_inj_err = error_code;
 389 }
 390
 391 static void svm_init_erratum_383(void)
 392 {
 393         u32 low, high;
 394         int err;
 395         u64 val;
 396
 397         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 398                 return;
 399
 400         /* Use _safe variants to not break nested virtualization */
 401         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 402         if (err)
 403                 return;
 404
 405         val |= (1ULL << 47);
 406
 407         low  = lower_32_bits(val);
 408         high = upper_32_bits(val);
 409
 410         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 411
 412         erratum_383_found = true;
 413 }
 414
 415 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 416 {
 417         /*
 418          * Guests should see errata 400 and 415 as fixed (assuming that
 419          * HLT and IO instructions are intercepted).
 420          */
 421         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 422         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 423
 424         /*
 425          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 426          * all osvw.status bits inside that length, including bit 0 (which is
 427          * reserved for erratum 298), are valid. However, if host processor's
 428          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 429          * be conservative here and therefore we tell the guest that erratum 298
 430          * is present (because we really don't know).
 431          */
 432         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 433                 vcpu->arch.osvw.status |= 1;
 434 }
 435
 436 static int has_svm(void)
 437 {
 438         const char *msg;
 439
 440         if (!cpu_has_svm(&msg)) {
 441                 printk(KERN_INFO "has_svm: %s\n", msg);
 442                 return 0;
 443         }
 444
 445         if (sev_active()) {
 446                 pr_info("KVM is unsupported when running as an SEV guest\n");
 447                 return 0;
 448         }
 449
 450         return 1;
 451 }
 452
 453 static void svm_hardware_disable(void)
 454 {
 455         /* Make sure we clean up behind us */
 456         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 457                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 458
 459         cpu_svm_disable();
 460
 461         amd_pmu_disable_virt();
 462 }
 463
 464 static int svm_hardware_enable(void)
 465 {
 466
 467         struct svm_cpu_data *sd;
 468         uint64_t efer;
 469         struct desc_struct *gdt;
 470         int me = raw_smp_processor_id();
 471
 472         rdmsrl(MSR_EFER, efer);
 473         if (efer & EFER_SVME)
 474                 return -EBUSY;
 475
 476         if (!has_svm()) {
 477                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 478                 return -EINVAL;
 479         }
 480         sd = per_cpu(svm_data, me);
 481         if (!sd) {
 482                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 483                 return -EINVAL;
 484         }
 485
 486         sd->asid_generation = 1;
 487         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 488         sd->next_asid = sd->max_asid + 1;
 489         sd->min_asid = max_sev_asid + 1;
 490
 491         gdt = get_current_gdt_rw();
 492         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 493
 494         wrmsrl(MSR_EFER, efer | EFER_SVME);
 495
 496         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 497
 498         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 499                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 500                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 501         }
 502
 503
 504         /*
 505          * Get OSVW bits.
 506          *
 507          * Note that it is possible to have a system with mixed processor
 508          * revisions and therefore different OSVW bits. If bits are not the same
 509          * on different processors then choose the worst case (i.e. if erratum
 510          * is present on one processor and not on another then assume that the
 511          * erratum is present everywhere).
 512          */
 513         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 514                 uint64_t len, status = 0;
 515                 int err;
 516
 517                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 518                 if (!err)
 519                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 520                                                       &err);
 521
 522                 if (err)
 523                         osvw_status = osvw_len = 0;
 524                 else {
 525                         if (len < osvw_len)
 526                                 osvw_len = len;
 527                         osvw_status |= status;
 528                         osvw_status &= (1ULL << osvw_len) - 1;
 529                 }
 530         } else
 531                 osvw_status = osvw_len = 0;
 532
 533         svm_init_erratum_383();
 534
 535         amd_pmu_enable_virt();
 536
 537         return 0;
 538 }
 539
 540 static void svm_cpu_uninit(int cpu)
 541 {
 542         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 543
 544         if (!sd)
 545                 return;
 546
 547         per_cpu(svm_data, cpu) = NULL;
 548         kfree(sd->sev_vmcbs);
 549         __free_page(sd->save_area);
 550         kfree(sd);
 551 }
 552
 553 static int svm_cpu_init(int cpu)
 554 {
 555         struct svm_cpu_data *sd;
 556
 557         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 558         if (!sd)
 559                 return -ENOMEM;
 560         sd->cpu = cpu;
 561         sd->save_area = alloc_page(GFP_KERNEL);
 562         if (!sd->save_area)
 563                 goto free_cpu_data;
 564         clear_page(page_address(sd->save_area));
 565
 566         if (svm_sev_enabled()) {
 567                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 568                                               sizeof(void *),
 569                                               GFP_KERNEL);
 570                 if (!sd->sev_vmcbs)
 571                         goto free_save_area;
 572         }
 573
 574         per_cpu(svm_data, cpu) = sd;
 575
 576         return 0;
 577
 578 free_save_area:
 579         __free_page(sd->save_area);
 580 free_cpu_data:
 581         kfree(sd);
 582         return -ENOMEM;
 583
 584 }
 585
 586 static int direct_access_msr_slot(u32 msr)
 587 {
 588         u32 i;
 589
 590         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 591                 if (direct_access_msrs[i].index == msr)
 592                         return i;
 593
 594         return -ENOENT;
 595 }
 596
 597 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 598                                      int write)
 599 {
 600         struct vcpu_svm *svm = to_svm(vcpu);
 601         int slot = direct_access_msr_slot(msr);
 602
 603         if (slot == -ENOENT)
 604                 return;
 605
 606         /* Set the shadow bitmaps to the desired intercept states */
 607         if (read)
 608                 set_bit(slot, svm->shadow_msr_intercept.read);
 609         else
 610                 clear_bit(slot, svm->shadow_msr_intercept.read);
 611
 612         if (write)
 613                 set_bit(slot, svm->shadow_msr_intercept.write);
 614         else
 615                 clear_bit(slot, svm->shadow_msr_intercept.write);
 616 }
 617
 618 static bool valid_msr_intercept(u32 index)
 619 {
 620         return direct_access_msr_slot(index) != -ENOENT;
 621 }
 622
 623 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 624 {
 625         u8 bit_write;
 626         unsigned long tmp;
 627         u32 offset;
 628         u32 *msrpm;
 629
 630         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 631                                       to_svm(vcpu)->msrpm;
 632
 633         offset    = svm_msrpm_offset(msr);
 634         bit_write = 2 * (msr & 0x0f) + 1;
 635         tmp       = msrpm[offset];
 636
 637         BUG_ON(offset == MSR_INVALID);
 638
 639         return !!test_bit(bit_write,  &tmp);
 640 }
 641
 642 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 643                                         u32 msr, int read, int write)
 644 {
 645         u8 bit_read, bit_write;
 646         unsigned long tmp;
 647         u32 offset;
 648
 649         /*
 650          * If this warning triggers extend the direct_access_msrs list at the
 651          * beginning of the file
 652          */
 653         WARN_ON(!valid_msr_intercept(msr));
 654
 655         /* Enforce non allowed MSRs to trap */
 656         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 657                 read = 0;
 658
 659         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 660                 write = 0;
 661
 662         offset    = svm_msrpm_offset(msr);
 663         bit_read  = 2 * (msr & 0x0f);
 664         bit_write = 2 * (msr & 0x0f) + 1;
 665         tmp       = msrpm[offset];
 666
 667         BUG_ON(offset == MSR_INVALID);
 668
 669         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 670         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 671
 672         msrpm[offset] = tmp;
 673 }
 674
 675 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 676                           int read, int write)
 677 {
 678         set_shadow_msr_intercept(vcpu, msr, read, write);
 679         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 680 }
 681
 682 u32 *svm_vcpu_alloc_msrpm(void)
 683 {
 684         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 685         u32 *msrpm;
 686
 687         if (!pages)
 688                 return NULL;
 689
 690         msrpm = page_address(pages);
 691         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 692
 693         return msrpm;
 694 }
 695
 696 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 697 {
 698         int i;
 699
 700         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 701                 if (!direct_access_msrs[i].always)
 702                         continue;
 703                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 704         }
 705 }
 706
 707
 708 void svm_vcpu_free_msrpm(u32 *msrpm)
 709 {
 710         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 711 }
 712
 713 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 714 {
 715         struct vcpu_svm *svm = to_svm(vcpu);
 716         u32 i;
 717
 718         /*
 719          * Set intercept permissions for all direct access MSRs again. They
 720          * will automatically get filtered through the MSR filter, so we are
 721          * back in sync after this.
 722          */
 723         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 724                 u32 msr = direct_access_msrs[i].index;
 725                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 726                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 727
 728                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 729         }
 730 }
 731
 732 static void add_msr_offset(u32 offset)
 733 {
 734         int i;
 735
 736         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 737
 738                 /* Offset already in list? */
 739                 if (msrpm_offsets[i] == offset)
 740                         return;
 741
 742                 /* Slot used by another offset? */
 743                 if (msrpm_offsets[i] != MSR_INVALID)
 744                         continue;
 745
 746                 /* Add offset to list */
 747                 msrpm_offsets[i] = offset;
 748
 749                 return;
 750         }
 751
 752         /*
 753          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 754          * increase MSRPM_OFFSETS in this case.
 755          */
 756         BUG();
 757 }
 758
 759 static void init_msrpm_offsets(void)
 760 {
 761         int i;
 762
 763         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 764
 765         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 766                 u32 offset;
 767
 768                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 769                 BUG_ON(offset == MSR_INVALID);
 770
 771                 add_msr_offset(offset);
 772         }
 773 }
 774
 775 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 776 {
 777         struct vcpu_svm *svm = to_svm(vcpu);
 778
 779         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 780         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 781         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 782         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 783         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 784 }
 785
 786 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 787 {
 788         struct vcpu_svm *svm = to_svm(vcpu);
 789
 790         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 791         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 792         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 793         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 794         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 795 }
 796
 797 void disable_nmi_singlestep(struct vcpu_svm *svm)
 798 {
 799         svm->nmi_singlestep = false;
 800
 801         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 802                 /* Clear our flags if they were not set by the guest */
 803                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 804                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 805                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 806                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 807         }
 808 }
 809
 810 static void grow_ple_window(struct kvm_vcpu *vcpu)
 811 {
 812         struct vcpu_svm *svm = to_svm(vcpu);
 813         struct vmcb_control_area *control = &svm->vmcb->control;
 814         int old = control->pause_filter_count;
 815
 816         control->pause_filter_count = __grow_ple_window(old,
 817                                                         pause_filter_count,
 818                                                         pause_filter_count_grow,
 819                                                         pause_filter_count_max);
 820
 821         if (control->pause_filter_count != old) {
 822                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 823                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 824                                             control->pause_filter_count, old);
 825         }
 826 }
 827
 828 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 829 {
 830         struct vcpu_svm *svm = to_svm(vcpu);
 831         struct vmcb_control_area *control = &svm->vmcb->control;
 832         int old = control->pause_filter_count;
 833
 834         control->pause_filter_count =
 835                                 __shrink_ple_window(old,
 836                                                     pause_filter_count,
 837                                                     pause_filter_count_shrink,
 838                                                     pause_filter_count);
 839         if (control->pause_filter_count != old) {
 840                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 841                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 842                                             control->pause_filter_count, old);
 843         }
 844 }
 845
 846 /*
 847  * The default MMIO mask is a single bit (excluding the present bit),
 848  * which could conflict with the memory encryption bit. Check for
 849  * memory encryption support and override the default MMIO mask if
 850  * memory encryption is enabled.
 851  */
 852 static __init void svm_adjust_mmio_mask(void)
 853 {
 854         unsigned int enc_bit, mask_bit;
 855         u64 msr, mask;
 856
 857         /* If there is no memory encryption support, use existing mask */
 858         if (cpuid_eax(0x80000000) < 0x8000001f)
 859                 return;
 860
 861         /* If memory encryption is not enabled, use existing mask */
 862         rdmsrl(MSR_K8_SYSCFG, msr);
 863         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 864                 return;
 865
 866         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 867         mask_bit = boot_cpu_data.x86_phys_bits;
 868
 869         /* Increment the mask bit if it is the same as the encryption bit */
 870         if (enc_bit == mask_bit)
 871                 mask_bit++;
 872
 873         /*
 874          * If the mask bit location is below 52, then some bits above the
 875          * physical addressing limit will always be reserved, so use the
 876          * rsvd_bits() function to generate the mask. This mask, along with
 877          * the present bit, will be used to generate a page fault with
 878          * PFER.RSV = 1.
 879          *
 880          * If the mask bit location is 52 (or above), then clear the mask.
 881          */
 882         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 883
 884         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 885 }
 886
 887 static void svm_hardware_teardown(void)
 888 {
 889         int cpu;
 890
 891         if (svm_sev_enabled())
 892                 sev_hardware_teardown();
 893
 894         for_each_possible_cpu(cpu)
 895                 svm_cpu_uninit(cpu);
 896
 897         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 898         iopm_base = 0;
 899 }
 900
 901 static __init void svm_set_cpu_caps(void)
 902 {
 903         kvm_set_cpu_caps();
 904
 905         supported_xss = 0;
 906
 907         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 908         if (nested) {
 909                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 910
 911                 if (nrips)
 912                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 913
 914                 if (npt_enabled)
 915                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 916
 917                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 918                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 919         }
 920
 921         /* CPUID 0x80000008 */
 922         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 923             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 924                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 925 }
 926
 927 static __init int svm_hardware_setup(void)
 928 {
 929         int cpu;
 930         struct page *iopm_pages;
 931         void *iopm_va;
 932         int r;
 933
 934         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 935
 936         if (!iopm_pages)
 937                 return -ENOMEM;
 938
 939         iopm_va = page_address(iopm_pages);
 940         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 941         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 942
 943         init_msrpm_offsets();
 944
 945         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 946
 947         if (boot_cpu_has(X86_FEATURE_NX))
 948                 kvm_enable_efer_bits(EFER_NX);
 949
 950         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 951                 kvm_enable_efer_bits(EFER_FFXSR);
 952
 953         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 954                 kvm_has_tsc_control = true;
 955                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 956                 kvm_tsc_scaling_ratio_frac_bits = 32;
 957         }
 958
 959         /* Check for pause filtering support */
 960         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 961                 pause_filter_count = 0;
 962                 pause_filter_thresh = 0;
 963         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 964                 pause_filter_thresh = 0;
 965         }
 966
 967         if (nested) {
 968                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 969                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 970         }
 971
 972         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 973                 sev_hardware_setup();
 974         } else {
 975                 sev = false;
 976                 sev_es = false;
 977         }
 978
 979         svm_adjust_mmio_mask();
 980
 981         for_each_possible_cpu(cpu) {
 982                 r = svm_cpu_init(cpu);
 983                 if (r)
 984                         goto err;
 985         }
 986
 987         /*
 988          * KVM's MMU doesn't support using 2-level paging for itself, and thus
 989          * NPT isn't supported if the host is using 2-level paging since host
 990          * CR4 is unchanged on VMRUN.
 991          */
 992         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
 993                 npt_enabled = false;
 994
 995         if (!boot_cpu_has(X86_FEATURE_NPT))
 996                 npt_enabled = false;
 997
 998         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 999         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1000
1001         if (nrips) {
1002                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1003                         nrips = false;
1004         }
1005
1006         if (avic) {
1007                 if (!npt_enabled ||
1008                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1009                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1010                         avic = false;
1011                 } else {
1012                         pr_info("AVIC enabled\n");
1013
1014                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1015                 }
1016         }
1017
1018         if (vls) {
1019                 if (!npt_enabled ||
1020                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1021                     !IS_ENABLED(CONFIG_X86_64)) {
1022                         vls = false;
1023                 } else {
1024                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1025                 }
1026         }
1027
1028         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1029                 svm_gp_erratum_intercept = false;
1030
1031         if (vgif) {
1032                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1033                         vgif = false;
1034                 else
1035                         pr_info("Virtual GIF supported\n");
1036         }
1037
1038         svm_set_cpu_caps();
1039
1040         /*
1041          * It seems that on AMD processors PTE's accessed bit is
1042          * being set by the CPU hardware before the NPF vmexit.
1043          * This is not expected behaviour and our tests fail because
1044          * of it.
1045          * A workaround here is to disable support for
1046          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1047          * In this case userspace can know if there is support using
1048          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1049          * it
1050          * If future AMD CPU models change the behaviour described above,
1051          * this variable can be changed accordingly
1052          */
1053         allow_smaller_maxphyaddr = !npt_enabled;
1054
1055         return 0;
1056
1057 err:
1058         svm_hardware_teardown();
1059         return r;
1060 }
1061
1062 static void init_seg(struct vmcb_seg *seg)
1063 {
1064         seg->selector = 0;
1065         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1066                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1067         seg->limit = 0xffff;
1068         seg->base = 0;
1069 }
1070
1071 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1072 {
1073         seg->selector = 0;
1074         seg->attrib = SVM_SELECTOR_P_MASK | type;
1075         seg->limit = 0xffff;
1076         seg->base = 0;
1077 }
1078
1079 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1080 {
1081         struct vcpu_svm *svm = to_svm(vcpu);
1082         u64 g_tsc_offset = 0;
1083
1084         if (is_guest_mode(vcpu)) {
1085                 /* Write L1's TSC offset.  */
1086                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1087                                svm->nested.hsave->control.tsc_offset;
1088                 svm->nested.hsave->control.tsc_offset = offset;
1089         }
1090
1091         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1092                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1093                                    offset);
1094
1095         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1096
1097         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1098         return svm->vmcb->control.tsc_offset;
1099 }
1100
1101 static void svm_check_invpcid(struct vcpu_svm *svm)
1102 {
1103         /*
1104          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1105          * roots, or if INVPCID is disabled in the guest to inject #UD.
1106          */
1107         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1108                 if (!npt_enabled ||
1109                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1110                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1111                 else
1112                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1113         }
1114 }
1115
1116 static void init_vmcb(struct vcpu_svm *svm)
1117 {
1118         struct vmcb_control_area *control = &svm->vmcb->control;
1119         struct vmcb_save_area *save = &svm->vmcb->save;
1120
1121         svm->vcpu.arch.hflags = 0;
1122
1123         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1124         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1125         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1126         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1127         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1128         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1129         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1130                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1131
1132         set_dr_intercepts(svm);
1133
1134         set_exception_intercept(svm, PF_VECTOR);
1135         set_exception_intercept(svm, UD_VECTOR);
1136         set_exception_intercept(svm, MC_VECTOR);
1137         set_exception_intercept(svm, AC_VECTOR);
1138         set_exception_intercept(svm, DB_VECTOR);
1139         /*
1140          * Guest access to VMware backdoor ports could legitimately
1141          * trigger #GP because of TSS I/O permission bitmap.
1142          * We intercept those #GP and allow access to them anyway
1143          * as VMware does.
1144          */
1145         if (enable_vmware_backdoor)
1146                 set_exception_intercept(svm, GP_VECTOR);
1147
1148         svm_set_intercept(svm, INTERCEPT_INTR);
1149         svm_set_intercept(svm, INTERCEPT_NMI);
1150         svm_set_intercept(svm, INTERCEPT_SMI);
1151         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1152         svm_set_intercept(svm, INTERCEPT_RDPMC);
1153         svm_set_intercept(svm, INTERCEPT_CPUID);
1154         svm_set_intercept(svm, INTERCEPT_INVD);
1155         svm_set_intercept(svm, INTERCEPT_INVLPG);
1156         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1157         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1158         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1159         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1160         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1161         svm_set_intercept(svm, INTERCEPT_VMRUN);
1162         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1163         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1164         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1165         svm_set_intercept(svm, INTERCEPT_STGI);
1166         svm_set_intercept(svm, INTERCEPT_CLGI);
1167         svm_set_intercept(svm, INTERCEPT_SKINIT);
1168         svm_set_intercept(svm, INTERCEPT_WBINVD);
1169         svm_set_intercept(svm, INTERCEPT_XSETBV);
1170         svm_set_intercept(svm, INTERCEPT_RDPRU);
1171         svm_set_intercept(svm, INTERCEPT_RSM);
1172
1173         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1174                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1175                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1176         }
1177
1178         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1179                 svm_set_intercept(svm, INTERCEPT_HLT);
1180
1181         control->iopm_base_pa = __sme_set(iopm_base);
1182         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1183         control->int_ctl = V_INTR_MASKING_MASK;
1184
1185         init_seg(&save->es);
1186         init_seg(&save->ss);
1187         init_seg(&save->ds);
1188         init_seg(&save->fs);
1189         init_seg(&save->gs);
1190
1191         save->cs.selector = 0xf000;
1192         save->cs.base = 0xffff0000;
1193         /* Executable/Readable Code Segment */
1194         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1195                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1196         save->cs.limit = 0xffff;
1197
1198         save->gdtr.limit = 0xffff;
1199         save->idtr.limit = 0xffff;
1200
1201         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1202         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1203
1204         svm_set_cr4(&svm->vcpu, 0);
1205         svm_set_efer(&svm->vcpu, 0);
1206         save->dr6 = 0xffff0ff0;
1207         kvm_set_rflags(&svm->vcpu, X86_EFLAGS_FIXED);
1208         save->rip = 0x0000fff0;
1209         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1210
1211         /*
1212          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1213          * It also updates the guest-visible cr0 value.
1214          */
1215         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1216         kvm_mmu_reset_context(&svm->vcpu);
1217
1218         save->cr4 = X86_CR4_PAE;
1219         /* rdx = ?? */
1220
1221         if (npt_enabled) {
1222                 /* Setup VMCB for Nested Paging */
1223                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1224                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1225                 clr_exception_intercept(svm, PF_VECTOR);
1226                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1227                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1228                 save->g_pat = svm->vcpu.arch.pat;
1229                 save->cr3 = 0;
1230                 save->cr4 = 0;
1231         }
1232         svm->asid_generation = 0;
1233         svm->asid = 0;
1234
1235         svm->nested.vmcb12_gpa = 0;
1236         svm->vcpu.arch.hflags = 0;
1237
1238         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1239                 control->pause_filter_count = pause_filter_count;
1240                 if (pause_filter_thresh)
1241                         control->pause_filter_thresh = pause_filter_thresh;
1242                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1243         } else {
1244                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1245         }
1246
1247         svm_check_invpcid(svm);
1248
1249         if (kvm_vcpu_apicv_active(&svm->vcpu))
1250                 avic_init_vmcb(svm);
1251
1252         /*
1253          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1254          * in VMCB and clear intercepts to avoid #VMEXIT.
1255          */
1256         if (vls) {
1257                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1258                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1259                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1260         }
1261
1262         if (vgif) {
1263                 svm_clr_intercept(svm, INTERCEPT_STGI);
1264                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1265                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1266         }
1267
1268         if (sev_guest(svm->vcpu.kvm)) {
1269                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1270                 clr_exception_intercept(svm, UD_VECTOR);
1271
1272                 if (sev_es_guest(svm->vcpu.kvm)) {
1273                         /* Perform SEV-ES specific VMCB updates */
1274                         sev_es_init_vmcb(svm);
1275                 }
1276         }
1277
1278         vmcb_mark_all_dirty(svm->vmcb);
1279
1280         enable_gif(svm);
1281
1282 }
1283
1284 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1285 {
1286         struct vcpu_svm *svm = to_svm(vcpu);
1287         u32 dummy;
1288         u32 eax = 1;
1289
1290         svm->spec_ctrl = 0;
1291         svm->virt_spec_ctrl = 0;
1292
1293         if (!init_event) {
1294                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1295                                            MSR_IA32_APICBASE_ENABLE;
1296                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1297                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1298         }
1299         init_vmcb(svm);
1300
1301         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1302         kvm_rdx_write(vcpu, eax);
1303
1304         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1305                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1306 }
1307
1308 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1309 {
1310         struct vcpu_svm *svm;
1311         struct page *vmcb_page;
1312         struct page *vmsa_page = NULL;
1313         int err;
1314
1315         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1316         svm = to_svm(vcpu);
1317
1318         err = -ENOMEM;
1319         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1320         if (!vmcb_page)
1321                 goto out;
1322
1323         if (sev_es_guest(svm->vcpu.kvm)) {
1324                 /*
1325                  * SEV-ES guests require a separate VMSA page used to contain
1326                  * the encrypted register state of the guest.
1327                  */
1328                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1329                 if (!vmsa_page)
1330                         goto error_free_vmcb_page;
1331
1332                 /*
1333                  * SEV-ES guests maintain an encrypted version of their FPU
1334                  * state which is restored and saved on VMRUN and VMEXIT.
1335                  * Free the fpu structure to prevent KVM from attempting to
1336                  * access the FPU state.
1337                  */
1338                 kvm_free_guest_fpu(vcpu);
1339         }
1340
1341         err = avic_init_vcpu(svm);
1342         if (err)
1343                 goto error_free_vmsa_page;
1344
1345         /* We initialize this flag to true to make sure that the is_running
1346          * bit would be set the first time the vcpu is loaded.
1347          */
1348         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1349                 svm->avic_is_running = true;
1350
1351         svm->msrpm = svm_vcpu_alloc_msrpm();
1352         if (!svm->msrpm) {
1353                 err = -ENOMEM;
1354                 goto error_free_vmsa_page;
1355         }
1356
1357         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1358
1359         svm->vmcb = page_address(vmcb_page);
1360         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1361
1362         if (vmsa_page)
1363                 svm->vmsa = page_address(vmsa_page);
1364
1365         svm->asid_generation = 0;
1366         svm->guest_state_loaded = false;
1367         init_vmcb(svm);
1368
1369         svm_init_osvw(vcpu);
1370         vcpu->arch.microcode_version = 0x01000065;
1371
1372         if (sev_es_guest(svm->vcpu.kvm))
1373                 /* Perform SEV-ES specific VMCB creation updates */
1374                 sev_es_create_vcpu(svm);
1375
1376         return 0;
1377
1378 error_free_vmsa_page:
1379         if (vmsa_page)
1380                 __free_page(vmsa_page);
1381 error_free_vmcb_page:
1382         __free_page(vmcb_page);
1383 out:
1384         return err;
1385 }
1386
1387 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1388 {
1389         int i;
1390
1391         for_each_online_cpu(i)
1392                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1393 }
1394
1395 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1396 {
1397         struct vcpu_svm *svm = to_svm(vcpu);
1398
1399         /*
1400          * The vmcb page can be recycled, causing a false negative in
1401          * svm_vcpu_load(). So, ensure that no logical CPU has this
1402          * vmcb page recorded as its current vmcb.
1403          */
1404         svm_clear_current_vmcb(svm->vmcb);
1405
1406         svm_free_nested(svm);
1407
1408         sev_free_vcpu(vcpu);
1409
1410         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1411         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1412 }
1413
1414 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1415 {
1416         struct vcpu_svm *svm = to_svm(vcpu);
1417         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1418         unsigned int i;
1419
1420         if (svm->guest_state_loaded)
1421                 return;
1422
1423         /*
1424          * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1425          * area (non-sev-es). Save ones that aren't so we can restore them
1426          * individually later.
1427          */
1428         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1429                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1430
1431         /*
1432          * Save additional host state that will be restored on VMEXIT (sev-es)
1433          * or subsequent vmload of host save area.
1434          */
1435         if (sev_es_guest(svm->vcpu.kvm)) {
1436                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1437         } else {
1438                 vmsave(__sme_page_pa(sd->save_area));
1439         }
1440
1441         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1442                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1443                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1444                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1445                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1446                 }
1447         }
1448
1449         /* This assumes that the kernel never uses MSR_TSC_AUX */
1450         if (static_cpu_has(X86_FEATURE_RDTSCP))
1451                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1452
1453         svm->guest_state_loaded = true;
1454 }
1455
1456 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1457 {
1458         struct vcpu_svm *svm = to_svm(vcpu);
1459         unsigned int i;
1460
1461         if (!svm->guest_state_loaded)
1462                 return;
1463
1464         /*
1465          * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1466          * area (non-sev-es). Restore the ones that weren't.
1467          */
1468         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1469                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1470
1471         svm->guest_state_loaded = false;
1472 }
1473
1474 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1475 {
1476         struct vcpu_svm *svm = to_svm(vcpu);
1477         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1478
1479         if (unlikely(cpu != vcpu->cpu)) {
1480                 svm->asid_generation = 0;
1481                 vmcb_mark_all_dirty(svm->vmcb);
1482         }
1483
1484         if (sd->current_vmcb != svm->vmcb) {
1485                 sd->current_vmcb = svm->vmcb;
1486                 indirect_branch_prediction_barrier();
1487         }
1488         avic_vcpu_load(vcpu, cpu);
1489 }
1490
1491 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1492 {
1493         avic_vcpu_put(vcpu);
1494         svm_prepare_host_switch(vcpu);
1495
1496         ++vcpu->stat.host_state_reload;
1497 }
1498
1499 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1500 {
1501         struct vcpu_svm *svm = to_svm(vcpu);
1502         unsigned long rflags = svm->vmcb->save.rflags;
1503
1504         if (svm->nmi_singlestep) {
1505                 /* Hide our flags if they were not set by the guest */
1506                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1507                         rflags &= ~X86_EFLAGS_TF;
1508                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1509                         rflags &= ~X86_EFLAGS_RF;
1510         }
1511         return rflags;
1512 }
1513
1514 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1515 {
1516         if (to_svm(vcpu)->nmi_singlestep)
1517                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1518
1519        /*
1520         * Any change of EFLAGS.VM is accompanied by a reload of SS
1521         * (caused by either a task switch or an inter-privilege IRET),
1522         * so we do not need to update the CPL here.
1523         */
1524         to_svm(vcpu)->vmcb->save.rflags = rflags;
1525 }
1526
1527 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1528 {
1529         switch (reg) {
1530         case VCPU_EXREG_PDPTR:
1531                 BUG_ON(!npt_enabled);
1532                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1533                 break;
1534         default:
1535                 WARN_ON_ONCE(1);
1536         }
1537 }
1538
1539 static void svm_set_vintr(struct vcpu_svm *svm)
1540 {
1541         struct vmcb_control_area *control;
1542
1543         /* The following fields are ignored when AVIC is enabled */
1544         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1545         svm_set_intercept(svm, INTERCEPT_VINTR);
1546
1547         /*
1548          * This is just a dummy VINTR to actually cause a vmexit to happen.
1549          * Actual injection of virtual interrupts happens through EVENTINJ.
1550          */
1551         control = &svm->vmcb->control;
1552         control->int_vector = 0x0;
1553         control->int_ctl &= ~V_INTR_PRIO_MASK;
1554         control->int_ctl |= V_IRQ_MASK |
1555                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1556         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1557 }
1558
1559 static void svm_clear_vintr(struct vcpu_svm *svm)
1560 {
1561         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1562         svm_clr_intercept(svm, INTERCEPT_VINTR);
1563
1564         /* Drop int_ctl fields related to VINTR injection.  */
1565         svm->vmcb->control.int_ctl &= mask;
1566         if (is_guest_mode(&svm->vcpu)) {
1567                 svm->nested.hsave->control.int_ctl &= mask;
1568
1569                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1570                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1571                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1572         }
1573
1574         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1575 }
1576
1577 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1578 {
1579         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1580
1581         switch (seg) {
1582         case VCPU_SREG_CS: return &save->cs;
1583         case VCPU_SREG_DS: return &save->ds;
1584         case VCPU_SREG_ES: return &save->es;
1585         case VCPU_SREG_FS: return &save->fs;
1586         case VCPU_SREG_GS: return &save->gs;
1587         case VCPU_SREG_SS: return &save->ss;
1588         case VCPU_SREG_TR: return &save->tr;
1589         case VCPU_SREG_LDTR: return &save->ldtr;
1590         }
1591         BUG();
1592         return NULL;
1593 }
1594
1595 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1596 {
1597         struct vmcb_seg *s = svm_seg(vcpu, seg);
1598
1599         return s->base;
1600 }
1601
1602 static void svm_get_segment(struct kvm_vcpu *vcpu,
1603                             struct kvm_segment *var, int seg)
1604 {
1605         struct vmcb_seg *s = svm_seg(vcpu, seg);
1606
1607         var->base = s->base;
1608         var->limit = s->limit;
1609         var->selector = s->selector;
1610         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1611         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1612         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1613         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1614         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1615         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1616         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1617
1618         /*
1619          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1620          * However, the SVM spec states that the G bit is not observed by the
1621          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1622          * So let's synthesize a legal G bit for all segments, this helps
1623          * running KVM nested. It also helps cross-vendor migration, because
1624          * Intel's vmentry has a check on the 'G' bit.
1625          */
1626         var->g = s->limit > 0xfffff;
1627
1628         /*
1629          * AMD's VMCB does not have an explicit unusable field, so emulate it
1630          * for cross vendor migration purposes by "not present"
1631          */
1632         var->unusable = !var->present;
1633
1634         switch (seg) {
1635         case VCPU_SREG_TR:
1636                 /*
1637                  * Work around a bug where the busy flag in the tr selector
1638                  * isn't exposed
1639                  */
1640                 var->type |= 0x2;
1641                 break;
1642         case VCPU_SREG_DS:
1643         case VCPU_SREG_ES:
1644         case VCPU_SREG_FS:
1645         case VCPU_SREG_GS:
1646                 /*
1647                  * The accessed bit must always be set in the segment
1648                  * descriptor cache, although it can be cleared in the
1649                  * descriptor, the cached bit always remains at 1. Since
1650                  * Intel has a check on this, set it here to support
1651                  * cross-vendor migration.
1652                  */
1653                 if (!var->unusable)
1654                         var->type |= 0x1;
1655                 break;
1656         case VCPU_SREG_SS:
1657                 /*
1658                  * On AMD CPUs sometimes the DB bit in the segment
1659                  * descriptor is left as 1, although the whole segment has
1660                  * been made unusable. Clear it here to pass an Intel VMX
1661                  * entry check when cross vendor migrating.
1662                  */
1663                 if (var->unusable)
1664                         var->db = 0;
1665                 /* This is symmetric with svm_set_segment() */
1666                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1667                 break;
1668         }
1669 }
1670
1671 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1672 {
1673         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1674
1675         return save->cpl;
1676 }
1677
1678 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1679 {
1680         struct vcpu_svm *svm = to_svm(vcpu);
1681
1682         dt->size = svm->vmcb->save.idtr.limit;
1683         dt->address = svm->vmcb->save.idtr.base;
1684 }
1685
1686 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1687 {
1688         struct vcpu_svm *svm = to_svm(vcpu);
1689
1690         svm->vmcb->save.idtr.limit = dt->size;
1691         svm->vmcb->save.idtr.base = dt->address ;
1692         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1693 }
1694
1695 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1696 {
1697         struct vcpu_svm *svm = to_svm(vcpu);
1698
1699         dt->size = svm->vmcb->save.gdtr.limit;
1700         dt->address = svm->vmcb->save.gdtr.base;
1701 }
1702
1703 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1704 {
1705         struct vcpu_svm *svm = to_svm(vcpu);
1706
1707         svm->vmcb->save.gdtr.limit = dt->size;
1708         svm->vmcb->save.gdtr.base = dt->address ;
1709         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1710 }
1711
1712 static void update_cr0_intercept(struct vcpu_svm *svm)
1713 {
1714         ulong gcr0;
1715         u64 *hcr0;
1716
1717         /*
1718          * SEV-ES guests must always keep the CR intercepts cleared. CR
1719          * tracking is done using the CR write traps.
1720          */
1721         if (sev_es_guest(svm->vcpu.kvm))
1722                 return;
1723
1724         gcr0 = svm->vcpu.arch.cr0;
1725         hcr0 = &svm->vmcb->save.cr0;
1726         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1727                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1728
1729         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1730
1731         if (gcr0 == *hcr0) {
1732                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1733                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1734         } else {
1735                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1736                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1737         }
1738 }
1739
1740 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1741 {
1742         struct vcpu_svm *svm = to_svm(vcpu);
1743
1744 #ifdef CONFIG_X86_64
1745         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1746                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1747                         vcpu->arch.efer |= EFER_LMA;
1748                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1749                 }
1750
1751                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1752                         vcpu->arch.efer &= ~EFER_LMA;
1753                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1754                 }
1755         }
1756 #endif
1757         vcpu->arch.cr0 = cr0;
1758
1759         if (!npt_enabled)
1760                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1761
1762         /*
1763          * re-enable caching here because the QEMU bios
1764          * does not do it - this results in some delay at
1765          * reboot
1766          */
1767         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1768                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1769         svm->vmcb->save.cr0 = cr0;
1770         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1771         update_cr0_intercept(svm);
1772 }
1773
1774 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1775 {
1776         return true;
1777 }
1778
1779 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1780 {
1781         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1782         unsigned long old_cr4 = vcpu->arch.cr4;
1783
1784         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1785                 svm_flush_tlb(vcpu);
1786
1787         vcpu->arch.cr4 = cr4;
1788         if (!npt_enabled)
1789                 cr4 |= X86_CR4_PAE;
1790         cr4 |= host_cr4_mce;
1791         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1792         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1793
1794         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1795                 kvm_update_cpuid_runtime(vcpu);
1796 }
1797
1798 static void svm_set_segment(struct kvm_vcpu *vcpu,
1799                             struct kvm_segment *var, int seg)
1800 {
1801         struct vcpu_svm *svm = to_svm(vcpu);
1802         struct vmcb_seg *s = svm_seg(vcpu, seg);
1803
1804         s->base = var->base;
1805         s->limit = var->limit;
1806         s->selector = var->selector;
1807         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1808         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1809         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1810         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1811         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1812         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1813         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1814         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1815
1816         /*
1817          * This is always accurate, except if SYSRET returned to a segment
1818          * with SS.DPL != 3.  Intel does not have this quirk, and always
1819          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1820          * would entail passing the CPL to userspace and back.
1821          */
1822         if (seg == VCPU_SREG_SS)
1823                 /* This is symmetric with svm_get_segment() */
1824                 svm->vmcb->save.cpl = (var->dpl & 3);
1825
1826         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1827 }
1828
1829 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1830 {
1831         struct vcpu_svm *svm = to_svm(vcpu);
1832
1833         clr_exception_intercept(svm, BP_VECTOR);
1834
1835         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1836                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1837                         set_exception_intercept(svm, BP_VECTOR);
1838         }
1839 }
1840
1841 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1842 {
1843         if (sd->next_asid > sd->max_asid) {
1844                 ++sd->asid_generation;
1845                 sd->next_asid = sd->min_asid;
1846                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1847                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1848         }
1849
1850         svm->asid_generation = sd->asid_generation;
1851         svm->asid = sd->next_asid++;
1852 }
1853
1854 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1855 {
1856         struct vmcb *vmcb = svm->vmcb;
1857
1858         if (svm->vcpu.arch.guest_state_protected)
1859                 return;
1860
1861         if (unlikely(value != vmcb->save.dr6)) {
1862                 vmcb->save.dr6 = value;
1863                 vmcb_mark_dirty(vmcb, VMCB_DR);
1864         }
1865 }
1866
1867 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1868 {
1869         struct vcpu_svm *svm = to_svm(vcpu);
1870
1871         if (vcpu->arch.guest_state_protected)
1872                 return;
1873
1874         get_debugreg(vcpu->arch.db[0], 0);
1875         get_debugreg(vcpu->arch.db[1], 1);
1876         get_debugreg(vcpu->arch.db[2], 2);
1877         get_debugreg(vcpu->arch.db[3], 3);
1878         /*
1879          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1880          * because db_interception might need it.  We can do it before vmentry.
1881          */
1882         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1883         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1884         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1885         set_dr_intercepts(svm);
1886 }
1887
1888 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1889 {
1890         struct vcpu_svm *svm = to_svm(vcpu);
1891
1892         if (vcpu->arch.guest_state_protected)
1893                 return;
1894
1895         svm->vmcb->save.dr7 = value;
1896         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1897 }
1898
1899 static int pf_interception(struct vcpu_svm *svm)
1900 {
1901         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1902         u64 error_code = svm->vmcb->control.exit_info_1;
1903
1904         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1905                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1906                         svm->vmcb->control.insn_bytes : NULL,
1907                         svm->vmcb->control.insn_len);
1908 }
1909
1910 static int npf_interception(struct vcpu_svm *svm)
1911 {
1912         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1913         u64 error_code = svm->vmcb->control.exit_info_1;
1914
1915         trace_kvm_page_fault(fault_address, error_code);
1916         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1917                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1918                         svm->vmcb->control.insn_bytes : NULL,
1919                         svm->vmcb->control.insn_len);
1920 }
1921
1922 static int db_interception(struct vcpu_svm *svm)
1923 {
1924         struct kvm_run *kvm_run = svm->vcpu.run;
1925         struct kvm_vcpu *vcpu = &svm->vcpu;
1926
1927         if (!(svm->vcpu.guest_debug &
1928               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1929                 !svm->nmi_singlestep) {
1930                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1931                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1932                 return 1;
1933         }
1934
1935         if (svm->nmi_singlestep) {
1936                 disable_nmi_singlestep(svm);
1937                 /* Make sure we check for pending NMIs upon entry */
1938                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1939         }
1940
1941         if (svm->vcpu.guest_debug &
1942             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1943                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1944                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1945                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1946                 kvm_run->debug.arch.pc =
1947                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1948                 kvm_run->debug.arch.exception = DB_VECTOR;
1949                 return 0;
1950         }
1951
1952         return 1;
1953 }
1954
1955 static int bp_interception(struct vcpu_svm *svm)
1956 {
1957         struct kvm_run *kvm_run = svm->vcpu.run;
1958
1959         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1960         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1961         kvm_run->debug.arch.exception = BP_VECTOR;
1962         return 0;
1963 }
1964
1965 static int ud_interception(struct vcpu_svm *svm)
1966 {
1967         return handle_ud(&svm->vcpu);
1968 }
1969
1970 static int ac_interception(struct vcpu_svm *svm)
1971 {
1972         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1973         return 1;
1974 }
1975
1976 static bool is_erratum_383(void)
1977 {
1978         int err, i;
1979         u64 value;
1980
1981         if (!erratum_383_found)
1982                 return false;
1983
1984         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1985         if (err)
1986                 return false;
1987
1988         /* Bit 62 may or may not be set for this mce */
1989         value &= ~(1ULL << 62);
1990
1991         if (value != 0xb600000000010015ULL)
1992                 return false;
1993
1994         /* Clear MCi_STATUS registers */
1995         for (i = 0; i < 6; ++i)
1996                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1997
1998         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1999         if (!err) {
2000                 u32 low, high;
2001
2002                 value &= ~(1ULL << 2);
2003                 low    = lower_32_bits(value);
2004                 high   = upper_32_bits(value);
2005
2006                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2007         }
2008
2009         /* Flush tlb to evict multi-match entries */
2010         __flush_tlb_all();
2011
2012         return true;
2013 }
2014
2015 static void svm_handle_mce(struct vcpu_svm *svm)
2016 {
2017         if (is_erratum_383()) {
2018                 /*
2019                  * Erratum 383 triggered. Guest state is corrupt so kill the
2020                  * guest.
2021                  */
2022                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2023
2024                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2025
2026                 return;
2027         }
2028
2029         /*
2030          * On an #MC intercept the MCE handler is not called automatically in
2031          * the host. So do it by hand here.
2032          */
2033         kvm_machine_check();
2034 }
2035
2036 static int mc_interception(struct vcpu_svm *svm)
2037 {
2038         return 1;
2039 }
2040
2041 static int shutdown_interception(struct vcpu_svm *svm)
2042 {
2043         struct kvm_run *kvm_run = svm->vcpu.run;
2044
2045         /*
2046          * The VM save area has already been encrypted so it
2047          * cannot be reinitialized - just terminate.
2048          */
2049         if (sev_es_guest(svm->vcpu.kvm))
2050                 return -EINVAL;
2051
2052         /*
2053          * VMCB is undefined after a SHUTDOWN intercept
2054          * so reinitialize it.
2055          */
2056         clear_page(svm->vmcb);
2057         init_vmcb(svm);
2058
2059         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2060         return 0;
2061 }
2062
2063 static int io_interception(struct vcpu_svm *svm)
2064 {
2065         struct kvm_vcpu *vcpu = &svm->vcpu;
2066         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2067         int size, in, string;
2068         unsigned port;
2069
2070         ++svm->vcpu.stat.io_exits;
2071         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2072         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2073         port = io_info >> 16;
2074         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2075
2076         if (string) {
2077                 if (sev_es_guest(vcpu->kvm))
2078                         return sev_es_string_io(svm, size, port, in);
2079                 else
2080                         return kvm_emulate_instruction(vcpu, 0);
2081         }
2082
2083         svm->next_rip = svm->vmcb->control.exit_info_2;
2084
2085         return kvm_fast_pio(&svm->vcpu, size, port, in);
2086 }
2087
2088 static int nmi_interception(struct vcpu_svm *svm)
2089 {
2090         return 1;
2091 }
2092
2093 static int intr_interception(struct vcpu_svm *svm)
2094 {
2095         ++svm->vcpu.stat.irq_exits;
2096         return 1;
2097 }
2098
2099 static int nop_on_interception(struct vcpu_svm *svm)
2100 {
2101         return 1;
2102 }
2103
2104 static int halt_interception(struct vcpu_svm *svm)
2105 {
2106         return kvm_emulate_halt(&svm->vcpu);
2107 }
2108
2109 static int vmmcall_interception(struct vcpu_svm *svm)
2110 {
2111         return kvm_emulate_hypercall(&svm->vcpu);
2112 }
2113
2114 static int vmload_interception(struct vcpu_svm *svm)
2115 {
2116         struct vmcb *nested_vmcb;
2117         struct kvm_host_map map;
2118         int ret;
2119
2120         if (nested_svm_check_permissions(svm))
2121                 return 1;
2122
2123         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2124         if (ret) {
2125                 if (ret == -EINVAL)
2126                         kvm_inject_gp(&svm->vcpu, 0);
2127                 return 1;
2128         }
2129
2130         nested_vmcb = map.hva;
2131
2132         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2133
2134         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2135         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2136
2137         return ret;
2138 }
2139
2140 static int vmsave_interception(struct vcpu_svm *svm)
2141 {
2142         struct vmcb *nested_vmcb;
2143         struct kvm_host_map map;
2144         int ret;
2145
2146         if (nested_svm_check_permissions(svm))
2147                 return 1;
2148
2149         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2150         if (ret) {
2151                 if (ret == -EINVAL)
2152                         kvm_inject_gp(&svm->vcpu, 0);
2153                 return 1;
2154         }
2155
2156         nested_vmcb = map.hva;
2157
2158         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2159
2160         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2161         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2162
2163         return ret;
2164 }
2165
2166 static int vmrun_interception(struct vcpu_svm *svm)
2167 {
2168         if (nested_svm_check_permissions(svm))
2169                 return 1;
2170
2171         return nested_svm_vmrun(svm);
2172 }
2173
2174 enum {
2175         NONE_SVM_INSTR,
2176         SVM_INSTR_VMRUN,
2177         SVM_INSTR_VMLOAD,
2178         SVM_INSTR_VMSAVE,
2179 };
2180
2181 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2182 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2183 {
2184         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2185
2186         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2187                 return NONE_SVM_INSTR;
2188
2189         switch (ctxt->modrm) {
2190         case 0xd8: /* VMRUN */
2191                 return SVM_INSTR_VMRUN;
2192         case 0xda: /* VMLOAD */
2193                 return SVM_INSTR_VMLOAD;
2194         case 0xdb: /* VMSAVE */
2195                 return SVM_INSTR_VMSAVE;
2196         default:
2197                 break;
2198         }
2199
2200         return NONE_SVM_INSTR;
2201 }
2202
2203 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2204 {
2205         const int guest_mode_exit_codes[] = {
2206                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2207                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2208                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2209         };
2210         int (*const svm_instr_handlers[])(struct vcpu_svm *svm) = {
2211                 [SVM_INSTR_VMRUN] = vmrun_interception,
2212                 [SVM_INSTR_VMLOAD] = vmload_interception,
2213                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2214         };
2215         struct vcpu_svm *svm = to_svm(vcpu);
2216         int ret;
2217
2218         if (is_guest_mode(vcpu)) {
2219                 svm->vmcb->control.exit_code = guest_mode_exit_codes[opcode];
2220                 svm->vmcb->control.exit_info_1 = 0;
2221                 svm->vmcb->control.exit_info_2 = 0;
2222
2223                 /* Returns '1' or -errno on failure, '0' on success. */
2224                 ret = nested_svm_vmexit(svm);
2225                 if (ret)
2226                         return ret;
2227                 return 1;
2228         }
2229         return svm_instr_handlers[opcode](svm);
2230 }
2231
2232 /*
2233  * #GP handling code. Note that #GP can be triggered under the following two
2234  * cases:
2235  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2236  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2237  *      regions (e.g. SMM memory on host).
2238  *   2) VMware backdoor
2239  */
2240 static int gp_interception(struct vcpu_svm *svm)
2241 {
2242         struct kvm_vcpu *vcpu = &svm->vcpu;
2243         u32 error_code = svm->vmcb->control.exit_info_1;
2244         int opcode;
2245
2246         /* Both #GP cases have zero error_code */
2247         if (error_code)
2248                 goto reinject;
2249
2250         /* Decode the instruction for usage later */
2251         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2252                 goto reinject;
2253
2254         opcode = svm_instr_opcode(vcpu);
2255
2256         if (opcode == NONE_SVM_INSTR) {
2257                 if (!enable_vmware_backdoor)
2258                         goto reinject;
2259
2260                 /*
2261                  * VMware backdoor emulation on #GP interception only handles
2262                  * IN{S}, OUT{S}, and RDPMC.
2263                  */
2264                 if (!is_guest_mode(vcpu))
2265                         return kvm_emulate_instruction(vcpu,
2266                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2267         } else
2268                 return emulate_svm_instr(vcpu, opcode);
2269
2270 reinject:
2271         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2272         return 1;
2273 }
2274
2275 void svm_set_gif(struct vcpu_svm *svm, bool value)
2276 {
2277         if (value) {
2278                 /*
2279                  * If VGIF is enabled, the STGI intercept is only added to
2280                  * detect the opening of the SMI/NMI window; remove it now.
2281                  * Likewise, clear the VINTR intercept, we will set it
2282                  * again while processing KVM_REQ_EVENT if needed.
2283                  */
2284                 if (vgif_enabled(svm))
2285                         svm_clr_intercept(svm, INTERCEPT_STGI);
2286                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2287                         svm_clear_vintr(svm);
2288
2289                 enable_gif(svm);
2290                 if (svm->vcpu.arch.smi_pending ||
2291                     svm->vcpu.arch.nmi_pending ||
2292                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2293                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2294         } else {
2295                 disable_gif(svm);
2296
2297                 /*
2298                  * After a CLGI no interrupts should come.  But if vGIF is
2299                  * in use, we still rely on the VINTR intercept (rather than
2300                  * STGI) to detect an open interrupt window.
2301                 */
2302                 if (!vgif_enabled(svm))
2303                         svm_clear_vintr(svm);
2304         }
2305 }
2306
2307 static int stgi_interception(struct vcpu_svm *svm)
2308 {
2309         int ret;
2310
2311         if (nested_svm_check_permissions(svm))
2312                 return 1;
2313
2314         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2315         svm_set_gif(svm, true);
2316         return ret;
2317 }
2318
2319 static int clgi_interception(struct vcpu_svm *svm)
2320 {
2321         int ret;
2322
2323         if (nested_svm_check_permissions(svm))
2324                 return 1;
2325
2326         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2327         svm_set_gif(svm, false);
2328         return ret;
2329 }
2330
2331 static int invlpga_interception(struct vcpu_svm *svm)
2332 {
2333         struct kvm_vcpu *vcpu = &svm->vcpu;
2334
2335         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2336                           kvm_rax_read(&svm->vcpu));
2337
2338         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2339         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2340
2341         return kvm_skip_emulated_instruction(&svm->vcpu);
2342 }
2343
2344 static int skinit_interception(struct vcpu_svm *svm)
2345 {
2346         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2347
2348         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2349         return 1;
2350 }
2351
2352 static int wbinvd_interception(struct vcpu_svm *svm)
2353 {
2354         return kvm_emulate_wbinvd(&svm->vcpu);
2355 }
2356
2357 static int xsetbv_interception(struct vcpu_svm *svm)
2358 {
2359         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2360         u32 index = kvm_rcx_read(&svm->vcpu);
2361
2362         int err = kvm_set_xcr(&svm->vcpu, index, new_bv);
2363         return kvm_complete_insn_gp(&svm->vcpu, err);
2364 }
2365
2366 static int rdpru_interception(struct vcpu_svm *svm)
2367 {
2368         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2369         return 1;
2370 }
2371
2372 static int task_switch_interception(struct vcpu_svm *svm)
2373 {
2374         u16 tss_selector;
2375         int reason;
2376         int int_type = svm->vmcb->control.exit_int_info &
2377                 SVM_EXITINTINFO_TYPE_MASK;
2378         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2379         uint32_t type =
2380                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2381         uint32_t idt_v =
2382                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2383         bool has_error_code = false;
2384         u32 error_code = 0;
2385
2386         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2387
2388         if (svm->vmcb->control.exit_info_2 &
2389             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2390                 reason = TASK_SWITCH_IRET;
2391         else if (svm->vmcb->control.exit_info_2 &
2392                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2393                 reason = TASK_SWITCH_JMP;
2394         else if (idt_v)
2395                 reason = TASK_SWITCH_GATE;
2396         else
2397                 reason = TASK_SWITCH_CALL;
2398
2399         if (reason == TASK_SWITCH_GATE) {
2400                 switch (type) {
2401                 case SVM_EXITINTINFO_TYPE_NMI:
2402                         svm->vcpu.arch.nmi_injected = false;
2403                         break;
2404                 case SVM_EXITINTINFO_TYPE_EXEPT:
2405                         if (svm->vmcb->control.exit_info_2 &
2406                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2407                                 has_error_code = true;
2408                                 error_code =
2409                                         (u32)svm->vmcb->control.exit_info_2;
2410                         }
2411                         kvm_clear_exception_queue(&svm->vcpu);
2412                         break;
2413                 case SVM_EXITINTINFO_TYPE_INTR:
2414                         kvm_clear_interrupt_queue(&svm->vcpu);
2415                         break;
2416                 default:
2417                         break;
2418                 }
2419         }
2420
2421         if (reason != TASK_SWITCH_GATE ||
2422             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2423             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2424              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2425                 if (!skip_emulated_instruction(&svm->vcpu))
2426                         return 0;
2427         }
2428
2429         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2430                 int_vec = -1;
2431
2432         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2433                                has_error_code, error_code);
2434 }
2435
2436 static int cpuid_interception(struct vcpu_svm *svm)
2437 {
2438         return kvm_emulate_cpuid(&svm->vcpu);
2439 }
2440
2441 static int iret_interception(struct vcpu_svm *svm)
2442 {
2443         ++svm->vcpu.stat.nmi_window_exits;
2444         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2445         if (!sev_es_guest(svm->vcpu.kvm)) {
2446                 svm_clr_intercept(svm, INTERCEPT_IRET);
2447                 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2448         }
2449         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2450         return 1;
2451 }
2452
2453 static int invd_interception(struct vcpu_svm *svm)
2454 {
2455         /* Treat an INVD instruction as a NOP and just skip it. */
2456         return kvm_skip_emulated_instruction(&svm->vcpu);
2457 }
2458
2459 static int invlpg_interception(struct vcpu_svm *svm)
2460 {
2461         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2462                 return kvm_emulate_instruction(&svm->vcpu, 0);
2463
2464         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2465         return kvm_skip_emulated_instruction(&svm->vcpu);
2466 }
2467
2468 static int emulate_on_interception(struct vcpu_svm *svm)
2469 {
2470         return kvm_emulate_instruction(&svm->vcpu, 0);
2471 }
2472
2473 static int rsm_interception(struct vcpu_svm *svm)
2474 {
2475         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2476 }
2477
2478 static int rdpmc_interception(struct vcpu_svm *svm)
2479 {
2480         int err;
2481
2482         if (!nrips)
2483                 return emulate_on_interception(svm);
2484
2485         err = kvm_rdpmc(&svm->vcpu);
2486         return kvm_complete_insn_gp(&svm->vcpu, err);
2487 }
2488
2489 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2490                                             unsigned long val)
2491 {
2492         unsigned long cr0 = svm->vcpu.arch.cr0;
2493         bool ret = false;
2494
2495         if (!is_guest_mode(&svm->vcpu) ||
2496             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2497                 return false;
2498
2499         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2500         val &= ~SVM_CR0_SELECTIVE_MASK;
2501
2502         if (cr0 ^ val) {
2503                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2504                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2505         }
2506
2507         return ret;
2508 }
2509
2510 #define CR_VALID (1ULL << 63)
2511
2512 static int cr_interception(struct vcpu_svm *svm)
2513 {
2514         int reg, cr;
2515         unsigned long val;
2516         int err;
2517
2518         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2519                 return emulate_on_interception(svm);
2520
2521         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2522                 return emulate_on_interception(svm);
2523
2524         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2525         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2526                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2527         else
2528                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2529
2530         err = 0;
2531         if (cr >= 16) { /* mov to cr */
2532                 cr -= 16;
2533                 val = kvm_register_read(&svm->vcpu, reg);
2534                 trace_kvm_cr_write(cr, val);
2535                 switch (cr) {
2536                 case 0:
2537                         if (!check_selective_cr0_intercepted(svm, val))
2538                                 err = kvm_set_cr0(&svm->vcpu, val);
2539                         else
2540                                 return 1;
2541
2542                         break;
2543                 case 3:
2544                         err = kvm_set_cr3(&svm->vcpu, val);
2545                         break;
2546                 case 4:
2547                         err = kvm_set_cr4(&svm->vcpu, val);
2548                         break;
2549                 case 8:
2550                         err = kvm_set_cr8(&svm->vcpu, val);
2551                         break;
2552                 default:
2553                         WARN(1, "unhandled write to CR%d", cr);
2554                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2555                         return 1;
2556                 }
2557         } else { /* mov from cr */
2558                 switch (cr) {
2559                 case 0:
2560                         val = kvm_read_cr0(&svm->vcpu);
2561                         break;
2562                 case 2:
2563                         val = svm->vcpu.arch.cr2;
2564                         break;
2565                 case 3:
2566                         val = kvm_read_cr3(&svm->vcpu);
2567                         break;
2568                 case 4:
2569                         val = kvm_read_cr4(&svm->vcpu);
2570                         break;
2571                 case 8:
2572                         val = kvm_get_cr8(&svm->vcpu);
2573                         break;
2574                 default:
2575                         WARN(1, "unhandled read from CR%d", cr);
2576                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2577                         return 1;
2578                 }
2579                 kvm_register_write(&svm->vcpu, reg, val);
2580                 trace_kvm_cr_read(cr, val);
2581         }
2582         return kvm_complete_insn_gp(&svm->vcpu, err);
2583 }
2584
2585 static int cr_trap(struct vcpu_svm *svm)
2586 {
2587         struct kvm_vcpu *vcpu = &svm->vcpu;
2588         unsigned long old_value, new_value;
2589         unsigned int cr;
2590         int ret = 0;
2591
2592         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2593
2594         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2595         switch (cr) {
2596         case 0:
2597                 old_value = kvm_read_cr0(vcpu);
2598                 svm_set_cr0(vcpu, new_value);
2599
2600                 kvm_post_set_cr0(vcpu, old_value, new_value);
2601                 break;
2602         case 4:
2603                 old_value = kvm_read_cr4(vcpu);
2604                 svm_set_cr4(vcpu, new_value);
2605
2606                 kvm_post_set_cr4(vcpu, old_value, new_value);
2607                 break;
2608         case 8:
2609                 ret = kvm_set_cr8(&svm->vcpu, new_value);
2610                 break;
2611         default:
2612                 WARN(1, "unhandled CR%d write trap", cr);
2613                 kvm_queue_exception(vcpu, UD_VECTOR);
2614                 return 1;
2615         }
2616
2617         return kvm_complete_insn_gp(vcpu, ret);
2618 }
2619
2620 static int dr_interception(struct vcpu_svm *svm)
2621 {
2622         int reg, dr;
2623         unsigned long val;
2624         int err = 0;
2625
2626         if (svm->vcpu.guest_debug == 0) {
2627                 /*
2628                  * No more DR vmexits; force a reload of the debug registers
2629                  * and reenter on this instruction.  The next vmexit will
2630                  * retrieve the full state of the debug registers.
2631                  */
2632                 clr_dr_intercepts(svm);
2633                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2634                 return 1;
2635         }
2636
2637         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2638                 return emulate_on_interception(svm);
2639
2640         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2641         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2642         if (dr >= 16) { /* mov to DRn  */
2643                 dr -= 16;
2644                 val = kvm_register_read(&svm->vcpu, reg);
2645                 err = kvm_set_dr(&svm->vcpu, dr, val);
2646         } else {
2647                 kvm_get_dr(&svm->vcpu, dr, &val);
2648                 kvm_register_write(&svm->vcpu, reg, val);
2649         }
2650
2651         return kvm_complete_insn_gp(&svm->vcpu, err);
2652 }
2653
2654 static int cr8_write_interception(struct vcpu_svm *svm)
2655 {
2656         struct kvm_run *kvm_run = svm->vcpu.run;
2657         int r;
2658
2659         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2660         /* instruction emulation calls kvm_set_cr8() */
2661         r = cr_interception(svm);
2662         if (lapic_in_kernel(&svm->vcpu))
2663                 return r;
2664         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2665                 return r;
2666         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2667         return 0;
2668 }
2669
2670 static int efer_trap(struct vcpu_svm *svm)
2671 {
2672         struct msr_data msr_info;
2673         int ret;
2674
2675         /*
2676          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2677          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2678          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2679          * the guest doesn't have X86_FEATURE_SVM.
2680          */
2681         msr_info.host_initiated = false;
2682         msr_info.index = MSR_EFER;
2683         msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2684         ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2685
2686         return kvm_complete_insn_gp(&svm->vcpu, ret);
2687 }
2688
2689 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2690 {
2691         msr->data = 0;
2692
2693         switch (msr->index) {
2694         case MSR_F10H_DECFG:
2695                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2696                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2697                 break;
2698         case MSR_IA32_PERF_CAPABILITIES:
2699                 return 0;
2700         default:
2701                 return KVM_MSR_RET_INVALID;
2702         }
2703
2704         return 0;
2705 }
2706
2707 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2708 {
2709         struct vcpu_svm *svm = to_svm(vcpu);
2710
2711         switch (msr_info->index) {
2712         case MSR_STAR:
2713                 msr_info->data = svm->vmcb->save.star;
2714                 break;
2715 #ifdef CONFIG_X86_64
2716         case MSR_LSTAR:
2717                 msr_info->data = svm->vmcb->save.lstar;
2718                 break;
2719         case MSR_CSTAR:
2720                 msr_info->data = svm->vmcb->save.cstar;
2721                 break;
2722         case MSR_KERNEL_GS_BASE:
2723                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2724                 break;
2725         case MSR_SYSCALL_MASK:
2726                 msr_info->data = svm->vmcb->save.sfmask;
2727                 break;
2728 #endif
2729         case MSR_IA32_SYSENTER_CS:
2730                 msr_info->data = svm->vmcb->save.sysenter_cs;
2731                 break;
2732         case MSR_IA32_SYSENTER_EIP:
2733                 msr_info->data = svm->sysenter_eip;
2734                 break;
2735         case MSR_IA32_SYSENTER_ESP:
2736                 msr_info->data = svm->sysenter_esp;
2737                 break;
2738         case MSR_TSC_AUX:
2739                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2740                         return 1;
2741                 msr_info->data = svm->tsc_aux;
2742                 break;
2743         /*
2744          * Nobody will change the following 5 values in the VMCB so we can
2745          * safely return them on rdmsr. They will always be 0 until LBRV is
2746          * implemented.
2747          */
2748         case MSR_IA32_DEBUGCTLMSR:
2749                 msr_info->data = svm->vmcb->save.dbgctl;
2750                 break;
2751         case MSR_IA32_LASTBRANCHFROMIP:
2752                 msr_info->data = svm->vmcb->save.br_from;
2753                 break;
2754         case MSR_IA32_LASTBRANCHTOIP:
2755                 msr_info->data = svm->vmcb->save.br_to;
2756                 break;
2757         case MSR_IA32_LASTINTFROMIP:
2758                 msr_info->data = svm->vmcb->save.last_excp_from;
2759                 break;
2760         case MSR_IA32_LASTINTTOIP:
2761                 msr_info->data = svm->vmcb->save.last_excp_to;
2762                 break;
2763         case MSR_VM_HSAVE_PA:
2764                 msr_info->data = svm->nested.hsave_msr;
2765                 break;
2766         case MSR_VM_CR:
2767                 msr_info->data = svm->nested.vm_cr_msr;
2768                 break;
2769         case MSR_IA32_SPEC_CTRL:
2770                 if (!msr_info->host_initiated &&
2771                     !guest_has_spec_ctrl_msr(vcpu))
2772                         return 1;
2773
2774                 msr_info->data = svm->spec_ctrl;
2775                 break;
2776         case MSR_AMD64_VIRT_SPEC_CTRL:
2777                 if (!msr_info->host_initiated &&
2778                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2779                         return 1;
2780
2781                 msr_info->data = svm->virt_spec_ctrl;
2782                 break;
2783         case MSR_F15H_IC_CFG: {
2784
2785                 int family, model;
2786
2787                 family = guest_cpuid_family(vcpu);
2788                 model  = guest_cpuid_model(vcpu);
2789
2790                 if (family < 0 || model < 0)
2791                         return kvm_get_msr_common(vcpu, msr_info);
2792
2793                 msr_info->data = 0;
2794
2795                 if (family == 0x15 &&
2796                     (model >= 0x2 && model < 0x20))
2797                         msr_info->data = 0x1E;
2798                 }
2799                 break;
2800         case MSR_F10H_DECFG:
2801                 msr_info->data = svm->msr_decfg;
2802                 break;
2803         default:
2804                 return kvm_get_msr_common(vcpu, msr_info);
2805         }
2806         return 0;
2807 }
2808
2809 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2810 {
2811         struct vcpu_svm *svm = to_svm(vcpu);
2812         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2813                 return kvm_complete_insn_gp(&svm->vcpu, err);
2814
2815         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2816         ghcb_set_sw_exit_info_2(svm->ghcb,
2817                                 X86_TRAP_GP |
2818                                 SVM_EVTINJ_TYPE_EXEPT |
2819                                 SVM_EVTINJ_VALID);
2820         return 1;
2821 }
2822
2823 static int rdmsr_interception(struct vcpu_svm *svm)
2824 {
2825         return kvm_emulate_rdmsr(&svm->vcpu);
2826 }
2827
2828 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2829 {
2830         struct vcpu_svm *svm = to_svm(vcpu);
2831         int svm_dis, chg_mask;
2832
2833         if (data & ~SVM_VM_CR_VALID_MASK)
2834                 return 1;
2835
2836         chg_mask = SVM_VM_CR_VALID_MASK;
2837
2838         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2839                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2840
2841         svm->nested.vm_cr_msr &= ~chg_mask;
2842         svm->nested.vm_cr_msr |= (data & chg_mask);
2843
2844         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2845
2846         /* check for svm_disable while efer.svme is set */
2847         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2848                 return 1;
2849
2850         return 0;
2851 }
2852
2853 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2854 {
2855         struct vcpu_svm *svm = to_svm(vcpu);
2856
2857         u32 ecx = msr->index;
2858         u64 data = msr->data;
2859         switch (ecx) {
2860         case MSR_IA32_CR_PAT:
2861                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2862                         return 1;
2863                 vcpu->arch.pat = data;
2864                 svm->vmcb->save.g_pat = data;
2865                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2866                 break;
2867         case MSR_IA32_SPEC_CTRL:
2868                 if (!msr->host_initiated &&
2869                     !guest_has_spec_ctrl_msr(vcpu))
2870                         return 1;
2871
2872                 if (kvm_spec_ctrl_test_value(data))
2873                         return 1;
2874
2875                 svm->spec_ctrl = data;
2876                 if (!data)
2877                         break;
2878
2879                 /*
2880                  * For non-nested:
2881                  * When it's written (to non-zero) for the first time, pass
2882                  * it through.
2883                  *
2884                  * For nested:
2885                  * The handling of the MSR bitmap for L2 guests is done in
2886                  * nested_svm_vmrun_msrpm.
2887                  * We update the L1 MSR bit as well since it will end up
2888                  * touching the MSR anyway now.
2889                  */
2890                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2891                 break;
2892         case MSR_IA32_PRED_CMD:
2893                 if (!msr->host_initiated &&
2894                     !guest_has_pred_cmd_msr(vcpu))
2895                         return 1;
2896
2897                 if (data & ~PRED_CMD_IBPB)
2898                         return 1;
2899                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2900                         return 1;
2901                 if (!data)
2902                         break;
2903
2904                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2905                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2906                 break;
2907         case MSR_AMD64_VIRT_SPEC_CTRL:
2908                 if (!msr->host_initiated &&
2909                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2910                         return 1;
2911
2912                 if (data & ~SPEC_CTRL_SSBD)
2913                         return 1;
2914
2915                 svm->virt_spec_ctrl = data;
2916                 break;
2917         case MSR_STAR:
2918                 svm->vmcb->save.star = data;
2919                 break;
2920 #ifdef CONFIG_X86_64
2921         case MSR_LSTAR:
2922                 svm->vmcb->save.lstar = data;
2923                 break;
2924         case MSR_CSTAR:
2925                 svm->vmcb->save.cstar = data;
2926                 break;
2927         case MSR_KERNEL_GS_BASE:
2928                 svm->vmcb->save.kernel_gs_base = data;
2929                 break;
2930         case MSR_SYSCALL_MASK:
2931                 svm->vmcb->save.sfmask = data;
2932                 break;
2933 #endif
2934         case MSR_IA32_SYSENTER_CS:
2935                 svm->vmcb->save.sysenter_cs = data;
2936                 break;
2937         case MSR_IA32_SYSENTER_EIP:
2938                 svm->sysenter_eip = data;
2939                 svm->vmcb->save.sysenter_eip = data;
2940                 break;
2941         case MSR_IA32_SYSENTER_ESP:
2942                 svm->sysenter_esp = data;
2943                 svm->vmcb->save.sysenter_esp = data;
2944                 break;
2945         case MSR_TSC_AUX:
2946                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2947                         return 1;
2948
2949                 /*
2950                  * This is rare, so we update the MSR here instead of using
2951                  * direct_access_msrs.  Doing that would require a rdmsr in
2952                  * svm_vcpu_put.
2953                  */
2954                 svm->tsc_aux = data;
2955                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2956                 break;
2957         case MSR_IA32_DEBUGCTLMSR:
2958                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2959                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2960                                     __func__, data);
2961                         break;
2962                 }
2963                 if (data & DEBUGCTL_RESERVED_BITS)
2964                         return 1;
2965
2966                 svm->vmcb->save.dbgctl = data;
2967                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2968                 if (data & (1ULL<<0))
2969                         svm_enable_lbrv(vcpu);
2970                 else
2971                         svm_disable_lbrv(vcpu);
2972                 break;
2973         case MSR_VM_HSAVE_PA:
2974                 svm->nested.hsave_msr = data;
2975                 break;
2976         case MSR_VM_CR:
2977                 return svm_set_vm_cr(vcpu, data);
2978         case MSR_VM_IGNNE:
2979                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2980                 break;
2981         case MSR_F10H_DECFG: {
2982                 struct kvm_msr_entry msr_entry;
2983
2984                 msr_entry.index = msr->index;
2985                 if (svm_get_msr_feature(&msr_entry))
2986                         return 1;
2987
2988                 /* Check the supported bits */
2989                 if (data & ~msr_entry.data)
2990                         return 1;
2991
2992                 /* Don't allow the guest to change a bit, #GP */
2993                 if (!msr->host_initiated && (data ^ msr_entry.data))
2994                         return 1;
2995
2996                 svm->msr_decfg = data;
2997                 break;
2998         }
2999         case MSR_IA32_APICBASE:
3000                 if (kvm_vcpu_apicv_active(vcpu))
3001                         avic_update_vapic_bar(to_svm(vcpu), data);
3002                 fallthrough;
3003         default:
3004                 return kvm_set_msr_common(vcpu, msr);
3005         }
3006         return 0;
3007 }
3008
3009 static int wrmsr_interception(struct vcpu_svm *svm)
3010 {
3011         return kvm_emulate_wrmsr(&svm->vcpu);
3012 }
3013
3014 static int msr_interception(struct vcpu_svm *svm)
3015 {
3016         if (svm->vmcb->control.exit_info_1)
3017                 return wrmsr_interception(svm);
3018         else
3019                 return rdmsr_interception(svm);
3020 }
3021
3022 static int interrupt_window_interception(struct vcpu_svm *svm)
3023 {
3024         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3025         svm_clear_vintr(svm);
3026
3027         /*
3028          * For AVIC, the only reason to end up here is ExtINTs.
3029          * In this case AVIC was temporarily disabled for
3030          * requesting the IRQ window and we have to re-enable it.
3031          */
3032         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
3033
3034         ++svm->vcpu.stat.irq_window_exits;
3035         return 1;
3036 }
3037
3038 static int pause_interception(struct vcpu_svm *svm)
3039 {
3040         struct kvm_vcpu *vcpu = &svm->vcpu;
3041         bool in_kernel;
3042
3043         /*
3044          * CPL is not made available for an SEV-ES guest, therefore
3045          * vcpu->arch.preempted_in_kernel can never be true.  Just
3046          * set in_kernel to false as well.
3047          */
3048         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
3049
3050         if (!kvm_pause_in_guest(vcpu->kvm))
3051                 grow_ple_window(vcpu);
3052
3053         kvm_vcpu_on_spin(vcpu, in_kernel);
3054         return 1;
3055 }
3056
3057 static int nop_interception(struct vcpu_svm *svm)
3058 {
3059         return kvm_skip_emulated_instruction(&(svm->vcpu));
3060 }
3061
3062 static int monitor_interception(struct vcpu_svm *svm)
3063 {
3064         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3065         return nop_interception(svm);
3066 }
3067
3068 static int mwait_interception(struct vcpu_svm *svm)
3069 {
3070         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3071         return nop_interception(svm);
3072 }
3073
3074 static int invpcid_interception(struct vcpu_svm *svm)
3075 {
3076         struct kvm_vcpu *vcpu = &svm->vcpu;
3077         unsigned long type;
3078         gva_t gva;
3079
3080         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3081                 kvm_queue_exception(vcpu, UD_VECTOR);
3082                 return 1;
3083         }
3084
3085         /*
3086          * For an INVPCID intercept:
3087          * EXITINFO1 provides the linear address of the memory operand.
3088          * EXITINFO2 provides the contents of the register operand.
3089          */
3090         type = svm->vmcb->control.exit_info_2;
3091         gva = svm->vmcb->control.exit_info_1;
3092
3093         if (type > 3) {
3094                 kvm_inject_gp(vcpu, 0);
3095                 return 1;
3096         }
3097
3098         return kvm_handle_invpcid(vcpu, type, gva);
3099 }
3100
3101 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3102         [SVM_EXIT_READ_CR0]                     = cr_interception,
3103         [SVM_EXIT_READ_CR3]                     = cr_interception,
3104         [SVM_EXIT_READ_CR4]                     = cr_interception,
3105         [SVM_EXIT_READ_CR8]                     = cr_interception,
3106         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3107         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3108         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3109         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3110         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3111         [SVM_EXIT_READ_DR0]                     = dr_interception,
3112         [SVM_EXIT_READ_DR1]                     = dr_interception,
3113         [SVM_EXIT_READ_DR2]                     = dr_interception,
3114         [SVM_EXIT_READ_DR3]                     = dr_interception,
3115         [SVM_EXIT_READ_DR4]                     = dr_interception,
3116         [SVM_EXIT_READ_DR5]                     = dr_interception,
3117         [SVM_EXIT_READ_DR6]                     = dr_interception,
3118         [SVM_EXIT_READ_DR7]                     = dr_interception,
3119         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3120         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3121         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3122         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3123         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3124         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3125         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3126         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3127         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3128         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3129         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3130         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3131         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3132         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3133         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3134         [SVM_EXIT_INTR]                         = intr_interception,
3135         [SVM_EXIT_NMI]                          = nmi_interception,
3136         [SVM_EXIT_SMI]                          = nop_on_interception,
3137         [SVM_EXIT_INIT]                         = nop_on_interception,
3138         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3139         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3140         [SVM_EXIT_CPUID]                        = cpuid_interception,
3141         [SVM_EXIT_IRET]                         = iret_interception,
3142         [SVM_EXIT_INVD]                         = invd_interception,
3143         [SVM_EXIT_PAUSE]                        = pause_interception,
3144         [SVM_EXIT_HLT]                          = halt_interception,
3145         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3146         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3147         [SVM_EXIT_IOIO]                         = io_interception,
3148         [SVM_EXIT_MSR]                          = msr_interception,
3149         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3150         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3151         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3152         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3153         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3154         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3155         [SVM_EXIT_STGI]                         = stgi_interception,
3156         [SVM_EXIT_CLGI]                         = clgi_interception,
3157         [SVM_EXIT_SKINIT]                       = skinit_interception,
3158         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3159         [SVM_EXIT_MONITOR]                      = monitor_interception,
3160         [SVM_EXIT_MWAIT]                        = mwait_interception,
3161         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3162         [SVM_EXIT_RDPRU]                        = rdpru_interception,
3163         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3164         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3165         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3166         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3167         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3168         [SVM_EXIT_NPF]                          = npf_interception,
3169         [SVM_EXIT_RSM]                          = rsm_interception,
3170         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3171         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3172         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3173 };
3174
3175 static void dump_vmcb(struct kvm_vcpu *vcpu)
3176 {
3177         struct vcpu_svm *svm = to_svm(vcpu);
3178         struct vmcb_control_area *control = &svm->vmcb->control;
3179         struct vmcb_save_area *save = &svm->vmcb->save;
3180
3181         if (!dump_invalid_vmcb) {
3182                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3183                 return;
3184         }
3185
3186         pr_err("VMCB Control Area:\n");
3187         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3188         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3189         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3190         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3191         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3192         pr_err("%-20s%08x %08x\n", "intercepts:",
3193               control->intercepts[INTERCEPT_WORD3],
3194                control->intercepts[INTERCEPT_WORD4]);
3195         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3196         pr_err("%-20s%d\n", "pause filter threshold:",
3197                control->pause_filter_thresh);
3198         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3199         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3200         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3201         pr_err("%-20s%d\n", "asid:", control->asid);
3202         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3203         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3204         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3205         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3206         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3207         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3208         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3209         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3210         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3211         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3212         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3213         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3214         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3215         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3216         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3217         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3218         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3219         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3220         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3221         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3222         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3223         pr_err("VMCB State Save Area:\n");
3224         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3225                "es:",
3226                save->es.selector, save->es.attrib,
3227                save->es.limit, save->es.base);
3228         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3229                "cs:",
3230                save->cs.selector, save->cs.attrib,
3231                save->cs.limit, save->cs.base);
3232         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3233                "ss:",
3234                save->ss.selector, save->ss.attrib,
3235                save->ss.limit, save->ss.base);
3236         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3237                "ds:",
3238                save->ds.selector, save->ds.attrib,
3239                save->ds.limit, save->ds.base);
3240         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3241                "fs:",
3242                save->fs.selector, save->fs.attrib,
3243                save->fs.limit, save->fs.base);
3244         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3245                "gs:",
3246                save->gs.selector, save->gs.attrib,
3247                save->gs.limit, save->gs.base);
3248         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3249                "gdtr:",
3250                save->gdtr.selector, save->gdtr.attrib,
3251                save->gdtr.limit, save->gdtr.base);
3252         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3253                "ldtr:",
3254                save->ldtr.selector, save->ldtr.attrib,
3255                save->ldtr.limit, save->ldtr.base);
3256         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3257                "idtr:",
3258                save->idtr.selector, save->idtr.attrib,
3259                save->idtr.limit, save->idtr.base);
3260         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3261                "tr:",
3262                save->tr.selector, save->tr.attrib,
3263                save->tr.limit, save->tr.base);
3264         pr_err("cpl:            %d                efer:         %016llx\n",
3265                 save->cpl, save->efer);
3266         pr_err("%-15s %016llx %-13s %016llx\n",
3267                "cr0:", save->cr0, "cr2:", save->cr2);
3268         pr_err("%-15s %016llx %-13s %016llx\n",
3269                "cr3:", save->cr3, "cr4:", save->cr4);
3270         pr_err("%-15s %016llx %-13s %016llx\n",
3271                "dr6:", save->dr6, "dr7:", save->dr7);
3272         pr_err("%-15s %016llx %-13s %016llx\n",
3273                "rip:", save->rip, "rflags:", save->rflags);
3274         pr_err("%-15s %016llx %-13s %016llx\n",
3275                "rsp:", save->rsp, "rax:", save->rax);
3276         pr_err("%-15s %016llx %-13s %016llx\n",
3277                "star:", save->star, "lstar:", save->lstar);
3278         pr_err("%-15s %016llx %-13s %016llx\n",
3279                "cstar:", save->cstar, "sfmask:", save->sfmask);
3280         pr_err("%-15s %016llx %-13s %016llx\n",
3281                "kernel_gs_base:", save->kernel_gs_base,
3282                "sysenter_cs:", save->sysenter_cs);
3283         pr_err("%-15s %016llx %-13s %016llx\n",
3284                "sysenter_esp:", save->sysenter_esp,
3285                "sysenter_eip:", save->sysenter_eip);
3286         pr_err("%-15s %016llx %-13s %016llx\n",
3287                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3288         pr_err("%-15s %016llx %-13s %016llx\n",
3289                "br_from:", save->br_from, "br_to:", save->br_to);
3290         pr_err("%-15s %016llx %-13s %016llx\n",
3291                "excp_from:", save->last_excp_from,
3292                "excp_to:", save->last_excp_to);
3293 }
3294
3295 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3296 {
3297         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3298             svm_exit_handlers[exit_code])
3299                 return 0;
3300
3301         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3302         dump_vmcb(vcpu);
3303         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3304         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3305         vcpu->run->internal.ndata = 2;
3306         vcpu->run->internal.data[0] = exit_code;
3307         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3308
3309         return -EINVAL;
3310 }
3311
3312 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3313 {
3314         if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3315                 return 0;
3316
3317 #ifdef CONFIG_RETPOLINE
3318         if (exit_code == SVM_EXIT_MSR)
3319                 return msr_interception(svm);
3320         else if (exit_code == SVM_EXIT_VINTR)
3321                 return interrupt_window_interception(svm);
3322         else if (exit_code == SVM_EXIT_INTR)
3323                 return intr_interception(svm);
3324         else if (exit_code == SVM_EXIT_HLT)
3325                 return halt_interception(svm);
3326         else if (exit_code == SVM_EXIT_NPF)
3327                 return npf_interception(svm);
3328 #endif
3329         return svm_exit_handlers[exit_code](svm);
3330 }
3331
3332 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3333                               u32 *intr_info, u32 *error_code)
3334 {
3335         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3336
3337         *info1 = control->exit_info_1;
3338         *info2 = control->exit_info_2;
3339         *intr_info = control->exit_int_info;
3340         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3341             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3342                 *error_code = control->exit_int_info_err;
3343         else
3344                 *error_code = 0;
3345 }
3346
3347 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3348 {
3349         struct vcpu_svm *svm = to_svm(vcpu);
3350         struct kvm_run *kvm_run = vcpu->run;
3351         u32 exit_code = svm->vmcb->control.exit_code;
3352
3353         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3354
3355         /* SEV-ES guests must use the CR write traps to track CR registers. */
3356         if (!sev_es_guest(vcpu->kvm)) {
3357                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3358                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3359                 if (npt_enabled)
3360                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3361         }
3362
3363         if (is_guest_mode(vcpu)) {
3364                 int vmexit;
3365
3366                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3367
3368                 vmexit = nested_svm_exit_special(svm);
3369
3370                 if (vmexit == NESTED_EXIT_CONTINUE)
3371                         vmexit = nested_svm_exit_handled(svm);
3372
3373                 if (vmexit == NESTED_EXIT_DONE)
3374                         return 1;
3375         }
3376
3377         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3378                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3379                 kvm_run->fail_entry.hardware_entry_failure_reason
3380                         = svm->vmcb->control.exit_code;
3381                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3382                 dump_vmcb(vcpu);
3383                 return 0;
3384         }
3385
3386         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3387             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3388             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3389             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3390                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3391                        "exit_code 0x%x\n",
3392                        __func__, svm->vmcb->control.exit_int_info,
3393                        exit_code);
3394
3395         if (exit_fastpath != EXIT_FASTPATH_NONE)
3396                 return 1;
3397
3398         return svm_invoke_exit_handler(svm, exit_code);
3399 }
3400
3401 static void reload_tss(struct kvm_vcpu *vcpu)
3402 {
3403         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3404
3405         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3406         load_TR_desc();
3407 }
3408
3409 static void pre_svm_run(struct vcpu_svm *svm)
3410 {
3411         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3412
3413         if (sev_guest(svm->vcpu.kvm))
3414                 return pre_sev_run(svm, svm->vcpu.cpu);
3415
3416         /* FIXME: handle wraparound of asid_generation */
3417         if (svm->asid_generation != sd->asid_generation)
3418                 new_asid(svm, sd);
3419 }
3420
3421 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3422 {
3423         struct vcpu_svm *svm = to_svm(vcpu);
3424
3425         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3426         vcpu->arch.hflags |= HF_NMI_MASK;
3427         if (!sev_es_guest(svm->vcpu.kvm))
3428                 svm_set_intercept(svm, INTERCEPT_IRET);
3429         ++vcpu->stat.nmi_injections;
3430 }
3431
3432 static void svm_set_irq(struct kvm_vcpu *vcpu)
3433 {
3434         struct vcpu_svm *svm = to_svm(vcpu);
3435
3436         BUG_ON(!(gif_set(svm)));
3437
3438         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3439         ++vcpu->stat.irq_injections;
3440
3441         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3442                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3443 }
3444
3445 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3446 {
3447         struct vcpu_svm *svm = to_svm(vcpu);
3448
3449         /*
3450          * SEV-ES guests must always keep the CR intercepts cleared. CR
3451          * tracking is done using the CR write traps.
3452          */
3453         if (sev_es_guest(vcpu->kvm))
3454                 return;
3455
3456         if (nested_svm_virtualize_tpr(vcpu))
3457                 return;
3458
3459         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3460
3461         if (irr == -1)
3462                 return;
3463
3464         if (tpr >= irr)
3465                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3466 }
3467
3468 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3469 {
3470         struct vcpu_svm *svm = to_svm(vcpu);
3471         struct vmcb *vmcb = svm->vmcb;
3472         bool ret;
3473
3474         if (!gif_set(svm))
3475                 return true;
3476
3477         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3478                 return false;
3479
3480         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3481               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3482
3483         return ret;
3484 }
3485
3486 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3487 {
3488         struct vcpu_svm *svm = to_svm(vcpu);
3489         if (svm->nested.nested_run_pending)
3490                 return -EBUSY;
3491
3492         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3493         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3494                 return -EBUSY;
3495
3496         return !svm_nmi_blocked(vcpu);
3497 }
3498
3499 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3500 {
3501         struct vcpu_svm *svm = to_svm(vcpu);
3502
3503         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3504 }
3505
3506 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3507 {
3508         struct vcpu_svm *svm = to_svm(vcpu);
3509
3510         if (masked) {
3511                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3512                 if (!sev_es_guest(svm->vcpu.kvm))
3513                         svm_set_intercept(svm, INTERCEPT_IRET);
3514         } else {
3515                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3516                 if (!sev_es_guest(svm->vcpu.kvm))
3517                         svm_clr_intercept(svm, INTERCEPT_IRET);
3518         }
3519 }
3520
3521 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3522 {
3523         struct vcpu_svm *svm = to_svm(vcpu);
3524         struct vmcb *vmcb = svm->vmcb;
3525
3526         if (!gif_set(svm))
3527                 return true;
3528
3529         if (sev_es_guest(svm->vcpu.kvm)) {
3530                 /*
3531                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3532                  * bit to determine the state of the IF flag.
3533                  */
3534                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3535                         return true;
3536         } else if (is_guest_mode(vcpu)) {
3537                 /* As long as interrupts are being delivered...  */
3538                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3539                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3540                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3541                         return true;
3542
3543                 /* ... vmexits aren't blocked by the interrupt shadow  */
3544                 if (nested_exit_on_intr(svm))
3545                         return false;
3546         } else {
3547                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3548                         return true;
3549         }
3550
3551         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3552 }
3553
3554 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3555 {
3556         struct vcpu_svm *svm = to_svm(vcpu);
3557         if (svm->nested.nested_run_pending)
3558                 return -EBUSY;
3559
3560         /*
3561          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3562          * e.g. if the IRQ arrived asynchronously after checking nested events.
3563          */
3564         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3565                 return -EBUSY;
3566
3567         return !svm_interrupt_blocked(vcpu);
3568 }
3569
3570 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3571 {
3572         struct vcpu_svm *svm = to_svm(vcpu);
3573
3574         /*
3575          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3576          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3577          * get that intercept, this function will be called again though and
3578          * we'll get the vintr intercept. However, if the vGIF feature is
3579          * enabled, the STGI interception will not occur. Enable the irq
3580          * window under the assumption that the hardware will set the GIF.
3581          */
3582         if (vgif_enabled(svm) || gif_set(svm)) {
3583                 /*
3584                  * IRQ window is not needed when AVIC is enabled,
3585                  * unless we have pending ExtINT since it cannot be injected
3586                  * via AVIC. In such case, we need to temporarily disable AVIC,
3587                  * and fallback to injecting IRQ via V_IRQ.
3588                  */
3589                 svm_toggle_avic_for_irq_window(vcpu, false);
3590                 svm_set_vintr(svm);
3591         }
3592 }
3593
3594 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3595 {
3596         struct vcpu_svm *svm = to_svm(vcpu);
3597
3598         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3599             == HF_NMI_MASK)
3600                 return; /* IRET will cause a vm exit */
3601
3602         if (!gif_set(svm)) {
3603                 if (vgif_enabled(svm))
3604                         svm_set_intercept(svm, INTERCEPT_STGI);
3605                 return; /* STGI will cause a vm exit */
3606         }
3607
3608         /*
3609          * Something prevents NMI from been injected. Single step over possible
3610          * problem (IRET or exception injection or interrupt shadow)
3611          */
3612         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3613         svm->nmi_singlestep = true;
3614         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3615 }
3616
3617 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3618 {
3619         return 0;
3620 }
3621
3622 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3623 {
3624         return 0;
3625 }
3626
3627 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3628 {
3629         struct vcpu_svm *svm = to_svm(vcpu);
3630
3631         /*
3632          * Flush only the current ASID even if the TLB flush was invoked via
3633          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3634          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3635          * unconditionally does a TLB flush on both nested VM-Enter and nested
3636          * VM-Exit (via kvm_mmu_reset_context()).
3637          */
3638         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3639                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3640         else
3641                 svm->asid_generation--;
3642 }
3643
3644 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3645 {
3646         struct vcpu_svm *svm = to_svm(vcpu);
3647
3648         invlpga(gva, svm->vmcb->control.asid);
3649 }
3650
3651 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3652 {
3653         struct vcpu_svm *svm = to_svm(vcpu);
3654
3655         if (nested_svm_virtualize_tpr(vcpu))
3656                 return;
3657
3658         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3659                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3660                 kvm_set_cr8(vcpu, cr8);
3661         }
3662 }
3663
3664 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3665 {
3666         struct vcpu_svm *svm = to_svm(vcpu);
3667         u64 cr8;
3668
3669         if (nested_svm_virtualize_tpr(vcpu) ||
3670             kvm_vcpu_apicv_active(vcpu))
3671                 return;
3672
3673         cr8 = kvm_get_cr8(vcpu);
3674         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3675         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3676 }
3677
3678 static void svm_complete_interrupts(struct vcpu_svm *svm)
3679 {
3680         u8 vector;
3681         int type;
3682         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3683         unsigned int3_injected = svm->int3_injected;
3684
3685         svm->int3_injected = 0;
3686
3687         /*
3688          * If we've made progress since setting HF_IRET_MASK, we've
3689          * executed an IRET and can allow NMI injection.
3690          */
3691         if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3692             (sev_es_guest(svm->vcpu.kvm) ||
3693              kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3694                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3695                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3696         }
3697
3698         svm->vcpu.arch.nmi_injected = false;
3699         kvm_clear_exception_queue(&svm->vcpu);
3700         kvm_clear_interrupt_queue(&svm->vcpu);
3701
3702         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3703                 return;
3704
3705         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3706
3707         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3708         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3709
3710         switch (type) {
3711         case SVM_EXITINTINFO_TYPE_NMI:
3712                 svm->vcpu.arch.nmi_injected = true;
3713                 break;
3714         case SVM_EXITINTINFO_TYPE_EXEPT:
3715                 /*
3716                  * Never re-inject a #VC exception.
3717                  */
3718                 if (vector == X86_TRAP_VC)
3719                         break;
3720
3721                 /*
3722                  * In case of software exceptions, do not reinject the vector,
3723                  * but re-execute the instruction instead. Rewind RIP first
3724                  * if we emulated INT3 before.
3725                  */
3726                 if (kvm_exception_is_soft(vector)) {
3727                         if (vector == BP_VECTOR && int3_injected &&
3728                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3729                                 kvm_rip_write(&svm->vcpu,
3730                                               kvm_rip_read(&svm->vcpu) -
3731                                               int3_injected);
3732                         break;
3733                 }
3734                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3735                         u32 err = svm->vmcb->control.exit_int_info_err;
3736                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3737
3738                 } else
3739                         kvm_requeue_exception(&svm->vcpu, vector);
3740                 break;
3741         case SVM_EXITINTINFO_TYPE_INTR:
3742                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3743                 break;
3744         default:
3745                 break;
3746         }
3747 }
3748
3749 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3750 {
3751         struct vcpu_svm *svm = to_svm(vcpu);
3752         struct vmcb_control_area *control = &svm->vmcb->control;
3753
3754         control->exit_int_info = control->event_inj;
3755         control->exit_int_info_err = control->event_inj_err;
3756         control->event_inj = 0;
3757         svm_complete_interrupts(svm);
3758 }
3759
3760 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3761 {
3762         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3763             to_svm(vcpu)->vmcb->control.exit_info_1)
3764                 return handle_fastpath_set_msr_irqoff(vcpu);
3765
3766         return EXIT_FASTPATH_NONE;
3767 }
3768
3769 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3770                                         struct vcpu_svm *svm)
3771 {
3772         /*
3773          * VMENTER enables interrupts (host state), but the kernel state is
3774          * interrupts disabled when this is invoked. Also tell RCU about
3775          * it. This is the same logic as for exit_to_user_mode().
3776          *
3777          * This ensures that e.g. latency analysis on the host observes
3778          * guest mode as interrupt enabled.
3779          *
3780          * guest_enter_irqoff() informs context tracking about the
3781          * transition to guest mode and if enabled adjusts RCU state
3782          * accordingly.
3783          */
3784         instrumentation_begin();
3785         trace_hardirqs_on_prepare();
3786         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3787         instrumentation_end();
3788
3789         guest_enter_irqoff();
3790         lockdep_hardirqs_on(CALLER_ADDR0);
3791
3792         if (sev_es_guest(svm->vcpu.kvm)) {
3793                 __svm_sev_es_vcpu_run(svm->vmcb_pa);
3794         } else {
3795                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3796
3797                 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3798
3799                 vmload(__sme_page_pa(sd->save_area));
3800         }
3801
3802         /*
3803          * VMEXIT disables interrupts (host state), but tracing and lockdep
3804          * have them in state 'on' as recorded before entering guest mode.
3805          * Same as enter_from_user_mode().
3806          *
3807          * guest_exit_irqoff() restores host context and reinstates RCU if
3808          * enabled and required.
3809          *
3810          * This needs to be done before the below as native_read_msr()
3811          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3812          * into world and some more.
3813          */
3814         lockdep_hardirqs_off(CALLER_ADDR0);
3815         guest_exit_irqoff();
3816
3817         instrumentation_begin();
3818         trace_hardirqs_off_finish();
3819         instrumentation_end();
3820 }
3821
3822 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3823 {
3824         struct vcpu_svm *svm = to_svm(vcpu);
3825
3826         trace_kvm_entry(vcpu);
3827
3828         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3829         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3830         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3831
3832         /*
3833          * Disable singlestep if we're injecting an interrupt/exception.
3834          * We don't want our modified rflags to be pushed on the stack where
3835          * we might not be able to easily reset them if we disabled NMI
3836          * singlestep later.
3837          */
3838         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3839                 /*
3840                  * Event injection happens before external interrupts cause a
3841                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3842                  * is enough to force an immediate vmexit.
3843                  */
3844                 disable_nmi_singlestep(svm);
3845                 smp_send_reschedule(vcpu->cpu);
3846         }
3847
3848         pre_svm_run(svm);
3849
3850         sync_lapic_to_cr8(vcpu);
3851
3852         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3853                 svm->vmcb->control.asid = svm->asid;
3854                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3855         }
3856         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3857
3858         /*
3859          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3860          * of a #DB.
3861          */
3862         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3863                 svm_set_dr6(svm, vcpu->arch.dr6);
3864         else
3865                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3866
3867         clgi();
3868         kvm_load_guest_xsave_state(vcpu);
3869
3870         kvm_wait_lapic_expire(vcpu);
3871
3872         /*
3873          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3874          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3875          * is no need to worry about the conditional branch over the wrmsr
3876          * being speculatively taken.
3877          */
3878         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3879
3880         svm_vcpu_enter_exit(vcpu, svm);
3881
3882         /*
3883          * We do not use IBRS in the kernel. If this vCPU has used the
3884          * SPEC_CTRL MSR it may have left it on; save the value and
3885          * turn it off. This is much more efficient than blindly adding
3886          * it to the atomic save/restore list. Especially as the former
3887          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3888          *
3889          * For non-nested case:
3890          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3891          * save it.
3892          *
3893          * For nested case:
3894          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3895          * save it.
3896          */
3897         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3898                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3899
3900         if (!sev_es_guest(svm->vcpu.kvm))
3901                 reload_tss(vcpu);
3902
3903         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3904
3905         if (!sev_es_guest(svm->vcpu.kvm)) {
3906                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3907                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3908                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3909                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3910         }
3911
3912         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3913                 kvm_before_interrupt(&svm->vcpu);
3914
3915         kvm_load_host_xsave_state(vcpu);
3916         stgi();
3917
3918         /* Any pending NMI will happen here */
3919
3920         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3921                 kvm_after_interrupt(&svm->vcpu);
3922
3923         sync_cr8_to_lapic(vcpu);
3924
3925         svm->next_rip = 0;
3926         if (is_guest_mode(&svm->vcpu)) {
3927                 sync_nested_vmcb_control(svm);
3928                 svm->nested.nested_run_pending = 0;
3929         }
3930
3931         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3932         vmcb_mark_all_clean(svm->vmcb);
3933
3934         /* if exit due to PF check for async PF */
3935         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3936                 svm->vcpu.arch.apf.host_apf_flags =
3937                         kvm_read_and_reset_apf_flags();
3938
3939         if (npt_enabled) {
3940                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3941                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3942         }
3943
3944         /*
3945          * We need to handle MC intercepts here before the vcpu has a chance to
3946          * change the physical cpu
3947          */
3948         if (unlikely(svm->vmcb->control.exit_code ==
3949                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3950                 svm_handle_mce(svm);
3951
3952         svm_complete_interrupts(svm);
3953
3954         if (is_guest_mode(vcpu))
3955                 return EXIT_FASTPATH_NONE;
3956
3957         return svm_exit_handlers_fastpath(vcpu);
3958 }
3959
3960 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3961                              int root_level)
3962 {
3963         struct vcpu_svm *svm = to_svm(vcpu);
3964         unsigned long cr3;
3965
3966         cr3 = __sme_set(root);
3967         if (npt_enabled) {
3968                 svm->vmcb->control.nested_cr3 = cr3;
3969                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3970
3971                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3972                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3973                         return;
3974                 cr3 = vcpu->arch.cr3;
3975         }
3976
3977         svm->vmcb->save.cr3 = cr3;
3978         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3979 }
3980
3981 static int is_disabled(void)
3982 {
3983         u64 vm_cr;
3984
3985         rdmsrl(MSR_VM_CR, vm_cr);
3986         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3987                 return 1;
3988
3989         return 0;
3990 }
3991
3992 static void
3993 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3994 {
3995         /*
3996          * Patch in the VMMCALL instruction:
3997          */
3998         hypercall[0] = 0x0f;
3999         hypercall[1] = 0x01;
4000         hypercall[2] = 0xd9;
4001 }
4002
4003 static int __init svm_check_processor_compat(void)
4004 {
4005         return 0;
4006 }
4007
4008 static bool svm_cpu_has_accelerated_tpr(void)
4009 {
4010         return false;
4011 }
4012
4013 /*
4014  * The kvm parameter can be NULL (module initialization, or invocation before
4015  * VM creation). Be sure to check the kvm parameter before using it.
4016  */
4017 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4018 {
4019         switch (index) {
4020         case MSR_IA32_MCG_EXT_CTL:
4021         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4022                 return false;
4023         case MSR_IA32_SMBASE:
4024                 /* SEV-ES guests do not support SMM, so report false */
4025                 if (kvm && sev_es_guest(kvm))
4026                         return false;
4027                 break;
4028         default:
4029                 break;
4030         }
4031
4032         return true;
4033 }
4034
4035 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4036 {
4037         return 0;
4038 }
4039
4040 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4041 {
4042         struct vcpu_svm *svm = to_svm(vcpu);
4043         struct kvm_cpuid_entry2 *best;
4044
4045         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4046                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4047                                     boot_cpu_has(X86_FEATURE_XSAVES);
4048
4049         /* Update nrips enabled cache */
4050         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4051                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
4052
4053         /* Check again if INVPCID interception if required */
4054         svm_check_invpcid(svm);
4055
4056         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4057         if (sev_guest(vcpu->kvm)) {
4058                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4059                 if (best)
4060                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4061         }
4062
4063         if (!kvm_vcpu_apicv_active(vcpu))
4064                 return;
4065
4066         /*
4067          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4068          * is exposed to the guest, disable AVIC.
4069          */
4070         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4071                 kvm_request_apicv_update(vcpu->kvm, false,
4072                                          APICV_INHIBIT_REASON_X2APIC);
4073
4074         /*
4075          * Currently, AVIC does not work with nested virtualization.
4076          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4077          */
4078         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4079                 kvm_request_apicv_update(vcpu->kvm, false,
4080                                          APICV_INHIBIT_REASON_NESTED);
4081 }
4082
4083 static bool svm_has_wbinvd_exit(void)
4084 {
4085         return true;
4086 }
4087
4088 #define PRE_EX(exit)  { .exit_code = (exit), \
4089                         .stage = X86_ICPT_PRE_EXCEPT, }
4090 #define POST_EX(exit) { .exit_code = (exit), \
4091                         .stage = X86_ICPT_POST_EXCEPT, }
4092 #define POST_MEM(exit) { .exit_code = (exit), \
4093                         .stage = X86_ICPT_POST_MEMACCESS, }
4094
4095 static const struct __x86_intercept {
4096         u32 exit_code;
4097         enum x86_intercept_stage stage;
4098 } x86_intercept_map[] = {
4099         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4100         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4101         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4102         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4103         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4104         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4105         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4106         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4107         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4108         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4109         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4110         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4111         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4112         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4113         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4114         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4115         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4116         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4117         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4118         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4119         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4120         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4121         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4122         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4123         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4124         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4125         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4126         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4127         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4128         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4129         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4130         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4131         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4132         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4133         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4134         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4135         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4136         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4137         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4138         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4139         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4140         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4141         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4142         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4143         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4144         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4145         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4146 };
4147
4148 #undef PRE_EX
4149 #undef POST_EX
4150 #undef POST_MEM
4151
4152 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4153                                struct x86_instruction_info *info,
4154                                enum x86_intercept_stage stage,
4155                                struct x86_exception *exception)
4156 {
4157         struct vcpu_svm *svm = to_svm(vcpu);
4158         int vmexit, ret = X86EMUL_CONTINUE;
4159         struct __x86_intercept icpt_info;
4160         struct vmcb *vmcb = svm->vmcb;
4161
4162         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4163                 goto out;
4164
4165         icpt_info = x86_intercept_map[info->intercept];
4166
4167         if (stage != icpt_info.stage)
4168                 goto out;
4169
4170         switch (icpt_info.exit_code) {
4171         case SVM_EXIT_READ_CR0:
4172                 if (info->intercept == x86_intercept_cr_read)
4173                         icpt_info.exit_code += info->modrm_reg;
4174                 break;
4175         case SVM_EXIT_WRITE_CR0: {
4176                 unsigned long cr0, val;
4177
4178                 if (info->intercept == x86_intercept_cr_write)
4179                         icpt_info.exit_code += info->modrm_reg;
4180
4181                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4182                     info->intercept == x86_intercept_clts)
4183                         break;
4184
4185                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4186                                         INTERCEPT_SELECTIVE_CR0)))
4187                         break;
4188
4189                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4190                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4191
4192                 if (info->intercept == x86_intercept_lmsw) {
4193                         cr0 &= 0xfUL;
4194                         val &= 0xfUL;
4195                         /* lmsw can't clear PE - catch this here */
4196                         if (cr0 & X86_CR0_PE)
4197                                 val |= X86_CR0_PE;
4198                 }
4199
4200                 if (cr0 ^ val)
4201                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4202
4203                 break;
4204         }
4205         case SVM_EXIT_READ_DR0:
4206         case SVM_EXIT_WRITE_DR0:
4207                 icpt_info.exit_code += info->modrm_reg;
4208                 break;
4209         case SVM_EXIT_MSR:
4210                 if (info->intercept == x86_intercept_wrmsr)
4211                         vmcb->control.exit_info_1 = 1;
4212                 else
4213                         vmcb->control.exit_info_1 = 0;
4214                 break;
4215         case SVM_EXIT_PAUSE:
4216                 /*
4217                  * We get this for NOP only, but pause
4218                  * is rep not, check this here
4219                  */
4220                 if (info->rep_prefix != REPE_PREFIX)
4221                         goto out;
4222                 break;
4223         case SVM_EXIT_IOIO: {
4224                 u64 exit_info;
4225                 u32 bytes;
4226
4227                 if (info->intercept == x86_intercept_in ||
4228                     info->intercept == x86_intercept_ins) {
4229                         exit_info = ((info->src_val & 0xffff) << 16) |
4230                                 SVM_IOIO_TYPE_MASK;
4231                         bytes = info->dst_bytes;
4232                 } else {
4233                         exit_info = (info->dst_val & 0xffff) << 16;
4234                         bytes = info->src_bytes;
4235                 }
4236
4237                 if (info->intercept == x86_intercept_outs ||
4238                     info->intercept == x86_intercept_ins)
4239                         exit_info |= SVM_IOIO_STR_MASK;
4240
4241                 if (info->rep_prefix)
4242                         exit_info |= SVM_IOIO_REP_MASK;
4243
4244                 bytes = min(bytes, 4u);
4245
4246                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4247
4248                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4249
4250                 vmcb->control.exit_info_1 = exit_info;
4251                 vmcb->control.exit_info_2 = info->next_rip;
4252
4253                 break;
4254         }
4255         default:
4256                 break;
4257         }
4258
4259         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4260         if (static_cpu_has(X86_FEATURE_NRIPS))
4261                 vmcb->control.next_rip  = info->next_rip;
4262         vmcb->control.exit_code = icpt_info.exit_code;
4263         vmexit = nested_svm_exit_handled(svm);
4264
4265         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4266                                            : X86EMUL_CONTINUE;
4267
4268 out:
4269         return ret;
4270 }
4271
4272 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4273 {
4274 }
4275
4276 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4277 {
4278         if (!kvm_pause_in_guest(vcpu->kvm))
4279                 shrink_ple_window(vcpu);
4280 }
4281
4282 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4283 {
4284         /* [63:9] are reserved. */
4285         vcpu->arch.mcg_cap &= 0x1ff;
4286 }
4287
4288 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4289 {
4290         struct vcpu_svm *svm = to_svm(vcpu);
4291
4292         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4293         if (!gif_set(svm))
4294                 return true;
4295
4296         return is_smm(vcpu);
4297 }
4298
4299 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4300 {
4301         struct vcpu_svm *svm = to_svm(vcpu);
4302         if (svm->nested.nested_run_pending)
4303                 return -EBUSY;
4304
4305         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4306         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4307                 return -EBUSY;
4308
4309         return !svm_smi_blocked(vcpu);
4310 }
4311
4312 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4313 {
4314         struct vcpu_svm *svm = to_svm(vcpu);
4315         int ret;
4316
4317         if (is_guest_mode(vcpu)) {
4318                 /* FED8h - SVM Guest */
4319                 put_smstate(u64, smstate, 0x7ed8, 1);
4320                 /* FEE0h - SVM Guest VMCB Physical Address */
4321                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4322
4323                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4324                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4325                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4326
4327                 ret = nested_svm_vmexit(svm);
4328                 if (ret)
4329                         return ret;
4330         }
4331         return 0;
4332 }
4333
4334 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4335 {
4336         struct vcpu_svm *svm = to_svm(vcpu);
4337         struct kvm_host_map map;
4338         int ret = 0;
4339
4340         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4341                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4342                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4343                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4344
4345                 if (guest) {
4346                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4347                                 return 1;
4348
4349                         if (!(saved_efer & EFER_SVME))
4350                                 return 1;
4351
4352                         if (kvm_vcpu_map(&svm->vcpu,
4353                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4354                                 return 1;
4355
4356                         if (svm_allocate_nested(svm))
4357                                 return 1;
4358
4359                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4360                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4361                 }
4362         }
4363
4364         return ret;
4365 }
4366
4367 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4368 {
4369         struct vcpu_svm *svm = to_svm(vcpu);
4370
4371         if (!gif_set(svm)) {
4372                 if (vgif_enabled(svm))
4373                         svm_set_intercept(svm, INTERCEPT_STGI);
4374                 /* STGI will cause a vm exit */
4375         } else {
4376                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4377         }
4378 }
4379
4380 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4381 {
4382         bool smep, smap, is_user;
4383         unsigned long cr4;
4384
4385         /*
4386          * When the guest is an SEV-ES guest, emulation is not possible.
4387          */
4388         if (sev_es_guest(vcpu->kvm))
4389                 return false;
4390
4391         /*
4392          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4393          *
4394          * Errata:
4395          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4396          * possible that CPU microcode implementing DecodeAssist will fail
4397          * to read bytes of instruction which caused #NPF. In this case,
4398          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4399          * return 0 instead of the correct guest instruction bytes.
4400          *
4401          * This happens because CPU microcode reading instruction bytes
4402          * uses a special opcode which attempts to read data using CPL=0
4403          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4404          * fault, it gives up and returns no instruction bytes.
4405          *
4406          * Detection:
4407          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4408          * returned 0 in GuestIntrBytes field of the VMCB.
4409          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4410          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4411          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4412          * a SMEP fault instead of #NPF).
4413          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4414          * As most guests enable SMAP if they have also enabled SMEP, use above
4415          * logic in order to attempt minimize false-positive of detecting errata
4416          * while still preserving all cases semantic correctness.
4417          *
4418          * Workaround:
4419          * To determine what instruction the guest was executing, the hypervisor
4420          * will have to decode the instruction at the instruction pointer.
4421          *
4422          * In non SEV guest, hypervisor will be able to read the guest
4423          * memory to decode the instruction pointer when insn_len is zero
4424          * so we return true to indicate that decoding is possible.
4425          *
4426          * But in the SEV guest, the guest memory is encrypted with the
4427          * guest specific key and hypervisor will not be able to decode the
4428          * instruction pointer so we will not able to workaround it. Lets
4429          * print the error and request to kill the guest.
4430          */
4431         if (likely(!insn || insn_len))
4432                 return true;
4433
4434         /*
4435          * If RIP is invalid, go ahead with emulation which will cause an
4436          * internal error exit.
4437          */
4438         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4439                 return true;
4440
4441         cr4 = kvm_read_cr4(vcpu);
4442         smep = cr4 & X86_CR4_SMEP;
4443         smap = cr4 & X86_CR4_SMAP;
4444         is_user = svm_get_cpl(vcpu) == 3;
4445         if (smap && (!smep || is_user)) {
4446                 if (!sev_guest(vcpu->kvm))
4447                         return true;
4448
4449                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4450                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4451         }
4452
4453         return false;
4454 }
4455
4456 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4457 {
4458         struct vcpu_svm *svm = to_svm(vcpu);
4459
4460         /*
4461          * TODO: Last condition latch INIT signals on vCPU when
4462          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4463          * To properly emulate the INIT intercept,
4464          * svm_check_nested_events() should call nested_svm_vmexit()
4465          * if an INIT signal is pending.
4466          */
4467         return !gif_set(svm) ||
4468                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4469 }
4470
4471 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4472 {
4473         if (!sev_es_guest(vcpu->kvm))
4474                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4475
4476         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4477 }
4478
4479 static void svm_vm_destroy(struct kvm *kvm)
4480 {
4481         avic_vm_destroy(kvm);
4482         sev_vm_destroy(kvm);
4483 }
4484
4485 static int svm_vm_init(struct kvm *kvm)
4486 {
4487         if (!pause_filter_count || !pause_filter_thresh)
4488                 kvm->arch.pause_in_guest = true;
4489
4490         if (avic) {
4491                 int ret = avic_vm_init(kvm);
4492                 if (ret)
4493                         return ret;
4494         }
4495
4496         kvm_apicv_init(kvm, avic);
4497         return 0;
4498 }
4499
4500 static struct kvm_x86_ops svm_x86_ops __initdata = {
4501         .hardware_unsetup = svm_hardware_teardown,
4502         .hardware_enable = svm_hardware_enable,
4503         .hardware_disable = svm_hardware_disable,
4504         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4505         .has_emulated_msr = svm_has_emulated_msr,
4506
4507         .vcpu_create = svm_create_vcpu,
4508         .vcpu_free = svm_free_vcpu,
4509         .vcpu_reset = svm_vcpu_reset,
4510
4511         .vm_size = sizeof(struct kvm_svm),
4512         .vm_init = svm_vm_init,
4513         .vm_destroy = svm_vm_destroy,
4514
4515         .prepare_guest_switch = svm_prepare_guest_switch,
4516         .vcpu_load = svm_vcpu_load,
4517         .vcpu_put = svm_vcpu_put,
4518         .vcpu_blocking = svm_vcpu_blocking,
4519         .vcpu_unblocking = svm_vcpu_unblocking,
4520
4521         .update_exception_bitmap = svm_update_exception_bitmap,
4522         .get_msr_feature = svm_get_msr_feature,
4523         .get_msr = svm_get_msr,
4524         .set_msr = svm_set_msr,
4525         .get_segment_base = svm_get_segment_base,
4526         .get_segment = svm_get_segment,
4527         .set_segment = svm_set_segment,
4528         .get_cpl = svm_get_cpl,
4529         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4530         .set_cr0 = svm_set_cr0,
4531         .is_valid_cr4 = svm_is_valid_cr4,
4532         .set_cr4 = svm_set_cr4,
4533         .set_efer = svm_set_efer,
4534         .get_idt = svm_get_idt,
4535         .set_idt = svm_set_idt,
4536         .get_gdt = svm_get_gdt,
4537         .set_gdt = svm_set_gdt,
4538         .set_dr7 = svm_set_dr7,
4539         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4540         .cache_reg = svm_cache_reg,
4541         .get_rflags = svm_get_rflags,
4542         .set_rflags = svm_set_rflags,
4543
4544         .tlb_flush_all = svm_flush_tlb,
4545         .tlb_flush_current = svm_flush_tlb,
4546         .tlb_flush_gva = svm_flush_tlb_gva,
4547         .tlb_flush_guest = svm_flush_tlb,
4548
4549         .run = svm_vcpu_run,
4550         .handle_exit = handle_exit,
4551         .skip_emulated_instruction = skip_emulated_instruction,
4552         .update_emulated_instruction = NULL,
4553         .set_interrupt_shadow = svm_set_interrupt_shadow,
4554         .get_interrupt_shadow = svm_get_interrupt_shadow,
4555         .patch_hypercall = svm_patch_hypercall,
4556         .set_irq = svm_set_irq,
4557         .set_nmi = svm_inject_nmi,
4558         .queue_exception = svm_queue_exception,
4559         .cancel_injection = svm_cancel_injection,
4560         .interrupt_allowed = svm_interrupt_allowed,
4561         .nmi_allowed = svm_nmi_allowed,
4562         .get_nmi_mask = svm_get_nmi_mask,
4563         .set_nmi_mask = svm_set_nmi_mask,
4564         .enable_nmi_window = svm_enable_nmi_window,
4565         .enable_irq_window = svm_enable_irq_window,
4566         .update_cr8_intercept = svm_update_cr8_intercept,
4567         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4568         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4569         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4570         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4571         .load_eoi_exitmap = svm_load_eoi_exitmap,
4572         .hwapic_irr_update = svm_hwapic_irr_update,
4573         .hwapic_isr_update = svm_hwapic_isr_update,
4574         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4575         .apicv_post_state_restore = avic_post_state_restore,
4576
4577         .set_tss_addr = svm_set_tss_addr,
4578         .set_identity_map_addr = svm_set_identity_map_addr,
4579         .get_mt_mask = svm_get_mt_mask,
4580
4581         .get_exit_info = svm_get_exit_info,
4582
4583         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4584
4585         .has_wbinvd_exit = svm_has_wbinvd_exit,
4586
4587         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4588
4589         .load_mmu_pgd = svm_load_mmu_pgd,
4590
4591         .check_intercept = svm_check_intercept,
4592         .handle_exit_irqoff = svm_handle_exit_irqoff,
4593
4594         .request_immediate_exit = __kvm_request_immediate_exit,
4595
4596         .sched_in = svm_sched_in,
4597
4598         .pmu_ops = &amd_pmu_ops,
4599         .nested_ops = &svm_nested_ops,
4600
4601         .deliver_posted_interrupt = svm_deliver_avic_intr,
4602         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4603         .update_pi_irte = svm_update_pi_irte,
4604         .setup_mce = svm_setup_mce,
4605
4606         .smi_allowed = svm_smi_allowed,
4607         .pre_enter_smm = svm_pre_enter_smm,
4608         .pre_leave_smm = svm_pre_leave_smm,
4609         .enable_smi_window = svm_enable_smi_window,
4610
4611         .mem_enc_op = svm_mem_enc_op,
4612         .mem_enc_reg_region = svm_register_enc_region,
4613         .mem_enc_unreg_region = svm_unregister_enc_region,
4614
4615         .can_emulate_instruction = svm_can_emulate_instruction,
4616
4617         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4618
4619         .msr_filter_changed = svm_msr_filter_changed,
4620         .complete_emulated_msr = svm_complete_emulated_msr,
4621
4622         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4623 };
4624
4625 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4626         .cpu_has_kvm_support = has_svm,
4627         .disabled_by_bios = is_disabled,
4628         .hardware_setup = svm_hardware_setup,
4629         .check_processor_compatibility = svm_check_processor_compat,
4630
4631         .runtime_ops = &svm_x86_ops,
4632 };
4633
4634 static int __init svm_init(void)
4635 {
4636         __unused_size_checks();
4637
4638         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4639                         __alignof__(struct vcpu_svm), THIS_MODULE);
4640 }
4641
4642 static void __exit svm_exit(void)
4643 {
4644         kvm_exit();
4645 }
4646
4647 module_init(svm_init)
4648 module_exit(svm_exit)