1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
40 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
51 static const struct x86_cpu_id svm_cpu_id[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly;
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
86 static uint64_t osvw_len = 4, osvw_status;
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
91 static const struct svm_direct_access_msrs {
92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
95 { .index = MSR_STAR, .always = true },
96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
106 { .index = MSR_IA32_PRED_CMD, .always = false },
107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 bool npt_enabled = true;
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152 module_param(pause_filter_thresh, ushort, 0444);
154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155 module_param(pause_filter_count, ushort, 0444);
157 /* Default doubles per-vcpu window every exit. */
158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159 module_param(pause_filter_count_grow, ushort, 0444);
161 /* Default resets per-vcpu window every exit to pause_filter_count. */
162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163 module_param(pause_filter_count_shrink, ushort, 0444);
165 /* Default is to compute the maximum so we can never overflow. */
166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167 module_param(pause_filter_count_max, ushort, 0444);
169 /* allow nested paging (virtualized MMU) for all guests */
170 static int npt = true;
171 module_param(npt, int, S_IRUGO);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
189 /* enable/disable SEV support */
190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
193 static bool __read_mostly dump_invalid_vmcb = 0;
194 module_param(dump_invalid_vmcb, bool, 0644);
196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
198 static void svm_complete_interrupts(struct vcpu_svm *svm);
200 static unsigned long iopm_base;
202 struct kvm_ldttss_desc {
205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
209 } __attribute__((packed));
211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
216 #define MSRS_RANGE_SIZE 2048
217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
219 u32 svm_msrpm_offset(u32 msr)
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
232 /* Now we have the u8 offset - but need the u32 offset */
236 /* MSR not in any range */
240 #define MAX_INST_SIZE 15
242 static inline void clgi(void)
244 asm volatile (__ex("clgi"));
247 static inline void stgi(void)
249 asm volatile (__ex("stgi"));
252 static inline void invlpga(unsigned long addr, u32 asid)
254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
257 static int get_max_npt_level(void)
260 return PT64_ROOT_4LEVEL;
262 return PT32E_ROOT_LEVEL;
266 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
268 struct vcpu_svm *svm = to_svm(vcpu);
269 u64 old_efer = vcpu->arch.efer;
270 vcpu->arch.efer = efer;
273 /* Shadow paging assumes NX to be available. */
276 if (!(efer & EFER_LMA))
280 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
281 if (!(efer & EFER_SVME)) {
282 svm_leave_nested(svm);
283 svm_set_gif(svm, true);
286 * Free the nested guest state, unless we are in SMM.
287 * In this case we will return to the nested guest
288 * as soon as we leave SMM.
290 if (!is_smm(&svm->vcpu))
291 svm_free_nested(svm);
294 int ret = svm_allocate_nested(svm);
297 vcpu->arch.efer = old_efer;
303 svm->vmcb->save.efer = efer | EFER_SVME;
304 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
308 static int is_external_interrupt(u32 info)
310 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
311 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
314 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
316 struct vcpu_svm *svm = to_svm(vcpu);
319 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
320 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
324 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
326 struct vcpu_svm *svm = to_svm(vcpu);
329 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
331 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
335 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
337 struct vcpu_svm *svm = to_svm(vcpu);
339 if (nrips && svm->vmcb->control.next_rip != 0) {
340 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
341 svm->next_rip = svm->vmcb->control.next_rip;
344 if (!svm->next_rip) {
345 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
348 kvm_rip_write(vcpu, svm->next_rip);
350 svm_set_interrupt_shadow(vcpu, 0);
355 static void svm_queue_exception(struct kvm_vcpu *vcpu)
357 struct vcpu_svm *svm = to_svm(vcpu);
358 unsigned nr = vcpu->arch.exception.nr;
359 bool has_error_code = vcpu->arch.exception.has_error_code;
360 u32 error_code = vcpu->arch.exception.error_code;
362 kvm_deliver_exception_payload(&svm->vcpu);
364 if (nr == BP_VECTOR && !nrips) {
365 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
368 * For guest debugging where we have to reinject #BP if some
369 * INT3 is guest-owned:
370 * Emulate nRIP by moving RIP forward. Will fail if injection
371 * raises a fault that is not intercepted. Still better than
372 * failing in all cases.
374 (void)skip_emulated_instruction(&svm->vcpu);
375 rip = kvm_rip_read(&svm->vcpu);
376 svm->int3_rip = rip + svm->vmcb->save.cs.base;
377 svm->int3_injected = rip - old_rip;
380 svm->vmcb->control.event_inj = nr
382 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
383 | SVM_EVTINJ_TYPE_EXEPT;
384 svm->vmcb->control.event_inj_err = error_code;
387 static void svm_init_erratum_383(void)
393 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
396 /* Use _safe variants to not break nested virtualization */
397 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
403 low = lower_32_bits(val);
404 high = upper_32_bits(val);
406 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
408 erratum_383_found = true;
411 static void svm_init_osvw(struct kvm_vcpu *vcpu)
414 * Guests should see errata 400 and 415 as fixed (assuming that
415 * HLT and IO instructions are intercepted).
417 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
418 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
421 * By increasing VCPU's osvw.length to 3 we are telling the guest that
422 * all osvw.status bits inside that length, including bit 0 (which is
423 * reserved for erratum 298), are valid. However, if host processor's
424 * osvw_len is 0 then osvw_status[0] carries no information. We need to
425 * be conservative here and therefore we tell the guest that erratum 298
426 * is present (because we really don't know).
428 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
429 vcpu->arch.osvw.status |= 1;
432 static int has_svm(void)
436 if (!cpu_has_svm(&msg)) {
437 printk(KERN_INFO "has_svm: %s\n", msg);
444 static void svm_hardware_disable(void)
446 /* Make sure we clean up behind us */
447 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
448 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
452 amd_pmu_disable_virt();
455 static int svm_hardware_enable(void)
458 struct svm_cpu_data *sd;
460 struct desc_struct *gdt;
461 int me = raw_smp_processor_id();
463 rdmsrl(MSR_EFER, efer);
464 if (efer & EFER_SVME)
468 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
471 sd = per_cpu(svm_data, me);
473 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
477 sd->asid_generation = 1;
478 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
479 sd->next_asid = sd->max_asid + 1;
480 sd->min_asid = max_sev_asid + 1;
482 gdt = get_current_gdt_rw();
483 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
485 wrmsrl(MSR_EFER, efer | EFER_SVME);
487 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
489 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
490 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
491 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
498 * Note that it is possible to have a system with mixed processor
499 * revisions and therefore different OSVW bits. If bits are not the same
500 * on different processors then choose the worst case (i.e. if erratum
501 * is present on one processor and not on another then assume that the
502 * erratum is present everywhere).
504 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
505 uint64_t len, status = 0;
508 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
510 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
514 osvw_status = osvw_len = 0;
518 osvw_status |= status;
519 osvw_status &= (1ULL << osvw_len) - 1;
522 osvw_status = osvw_len = 0;
524 svm_init_erratum_383();
526 amd_pmu_enable_virt();
531 static void svm_cpu_uninit(int cpu)
533 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
538 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
539 kfree(sd->sev_vmcbs);
540 __free_page(sd->save_area);
544 static int svm_cpu_init(int cpu)
546 struct svm_cpu_data *sd;
548 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
552 sd->save_area = alloc_page(GFP_KERNEL);
556 if (svm_sev_enabled()) {
557 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
564 per_cpu(svm_data, cpu) = sd;
569 __free_page(sd->save_area);
576 static int direct_access_msr_slot(u32 msr)
580 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
581 if (direct_access_msrs[i].index == msr)
587 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
590 struct vcpu_svm *svm = to_svm(vcpu);
591 int slot = direct_access_msr_slot(msr);
596 /* Set the shadow bitmaps to the desired intercept states */
598 set_bit(slot, svm->shadow_msr_intercept.read);
600 clear_bit(slot, svm->shadow_msr_intercept.read);
603 set_bit(slot, svm->shadow_msr_intercept.write);
605 clear_bit(slot, svm->shadow_msr_intercept.write);
608 static bool valid_msr_intercept(u32 index)
610 return direct_access_msr_slot(index) != -ENOENT;
613 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
620 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
623 offset = svm_msrpm_offset(msr);
624 bit_write = 2 * (msr & 0x0f) + 1;
627 BUG_ON(offset == MSR_INVALID);
629 return !!test_bit(bit_write, &tmp);
632 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
633 u32 msr, int read, int write)
635 u8 bit_read, bit_write;
640 * If this warning triggers extend the direct_access_msrs list at the
641 * beginning of the file
643 WARN_ON(!valid_msr_intercept(msr));
645 /* Enforce non allowed MSRs to trap */
646 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
649 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
652 offset = svm_msrpm_offset(msr);
653 bit_read = 2 * (msr & 0x0f);
654 bit_write = 2 * (msr & 0x0f) + 1;
657 BUG_ON(offset == MSR_INVALID);
659 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
660 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
665 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
668 set_shadow_msr_intercept(vcpu, msr, read, write);
669 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
672 u32 *svm_vcpu_alloc_msrpm(void)
674 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
680 msrpm = page_address(pages);
681 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
686 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
690 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
691 if (!direct_access_msrs[i].always)
693 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
698 void svm_vcpu_free_msrpm(u32 *msrpm)
700 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
703 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
705 struct vcpu_svm *svm = to_svm(vcpu);
709 * Set intercept permissions for all direct access MSRs again. They
710 * will automatically get filtered through the MSR filter, so we are
711 * back in sync after this.
713 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
714 u32 msr = direct_access_msrs[i].index;
715 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
716 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
718 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
722 static void add_msr_offset(u32 offset)
726 for (i = 0; i < MSRPM_OFFSETS; ++i) {
728 /* Offset already in list? */
729 if (msrpm_offsets[i] == offset)
732 /* Slot used by another offset? */
733 if (msrpm_offsets[i] != MSR_INVALID)
736 /* Add offset to list */
737 msrpm_offsets[i] = offset;
743 * If this BUG triggers the msrpm_offsets table has an overflow. Just
744 * increase MSRPM_OFFSETS in this case.
749 static void init_msrpm_offsets(void)
753 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
755 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
758 offset = svm_msrpm_offset(direct_access_msrs[i].index);
759 BUG_ON(offset == MSR_INVALID);
761 add_msr_offset(offset);
765 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
767 struct vcpu_svm *svm = to_svm(vcpu);
769 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
770 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
771 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
772 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
773 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
776 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
778 struct vcpu_svm *svm = to_svm(vcpu);
780 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
781 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
782 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
783 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
784 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
787 void disable_nmi_singlestep(struct vcpu_svm *svm)
789 svm->nmi_singlestep = false;
791 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
792 /* Clear our flags if they were not set by the guest */
793 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
794 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
795 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
796 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
800 static void grow_ple_window(struct kvm_vcpu *vcpu)
802 struct vcpu_svm *svm = to_svm(vcpu);
803 struct vmcb_control_area *control = &svm->vmcb->control;
804 int old = control->pause_filter_count;
806 control->pause_filter_count = __grow_ple_window(old,
808 pause_filter_count_grow,
809 pause_filter_count_max);
811 if (control->pause_filter_count != old) {
812 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
813 trace_kvm_ple_window_update(vcpu->vcpu_id,
814 control->pause_filter_count, old);
818 static void shrink_ple_window(struct kvm_vcpu *vcpu)
820 struct vcpu_svm *svm = to_svm(vcpu);
821 struct vmcb_control_area *control = &svm->vmcb->control;
822 int old = control->pause_filter_count;
824 control->pause_filter_count =
825 __shrink_ple_window(old,
827 pause_filter_count_shrink,
829 if (control->pause_filter_count != old) {
830 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
831 trace_kvm_ple_window_update(vcpu->vcpu_id,
832 control->pause_filter_count, old);
837 * The default MMIO mask is a single bit (excluding the present bit),
838 * which could conflict with the memory encryption bit. Check for
839 * memory encryption support and override the default MMIO mask if
840 * memory encryption is enabled.
842 static __init void svm_adjust_mmio_mask(void)
844 unsigned int enc_bit, mask_bit;
847 /* If there is no memory encryption support, use existing mask */
848 if (cpuid_eax(0x80000000) < 0x8000001f)
851 /* If memory encryption is not enabled, use existing mask */
852 rdmsrl(MSR_K8_SYSCFG, msr);
853 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
856 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
857 mask_bit = boot_cpu_data.x86_phys_bits;
859 /* Increment the mask bit if it is the same as the encryption bit */
860 if (enc_bit == mask_bit)
864 * If the mask bit location is below 52, then some bits above the
865 * physical addressing limit will always be reserved, so use the
866 * rsvd_bits() function to generate the mask. This mask, along with
867 * the present bit, will be used to generate a page fault with
870 * If the mask bit location is 52 (or above), then clear the mask.
872 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
874 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
877 static void svm_hardware_teardown(void)
881 if (svm_sev_enabled())
882 sev_hardware_teardown();
884 for_each_possible_cpu(cpu)
887 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
891 static __init void svm_set_cpu_caps(void)
897 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
899 kvm_cpu_cap_set(X86_FEATURE_SVM);
902 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
905 kvm_cpu_cap_set(X86_FEATURE_NPT);
908 /* CPUID 0x80000008 */
909 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
910 boot_cpu_has(X86_FEATURE_AMD_SSBD))
911 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
913 /* Enable INVPCID feature */
914 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
917 static __init int svm_hardware_setup(void)
920 struct page *iopm_pages;
924 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
929 iopm_va = page_address(iopm_pages);
930 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
931 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
933 init_msrpm_offsets();
935 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
937 if (boot_cpu_has(X86_FEATURE_NX))
938 kvm_enable_efer_bits(EFER_NX);
940 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
941 kvm_enable_efer_bits(EFER_FFXSR);
943 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
944 kvm_has_tsc_control = true;
945 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
946 kvm_tsc_scaling_ratio_frac_bits = 32;
949 /* Check for pause filtering support */
950 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
951 pause_filter_count = 0;
952 pause_filter_thresh = 0;
953 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
954 pause_filter_thresh = 0;
958 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
959 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
963 if (boot_cpu_has(X86_FEATURE_SEV) &&
964 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
965 r = sev_hardware_setup();
973 svm_adjust_mmio_mask();
975 for_each_possible_cpu(cpu) {
976 r = svm_cpu_init(cpu);
981 if (!boot_cpu_has(X86_FEATURE_NPT))
984 if (npt_enabled && !npt)
987 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
988 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
991 if (!boot_cpu_has(X86_FEATURE_NRIPS))
997 !boot_cpu_has(X86_FEATURE_AVIC) ||
998 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1001 pr_info("AVIC enabled\n");
1003 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1009 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1010 !IS_ENABLED(CONFIG_X86_64)) {
1013 pr_info("Virtual VMLOAD VMSAVE supported\n");
1018 if (!boot_cpu_has(X86_FEATURE_VGIF))
1021 pr_info("Virtual GIF supported\n");
1027 * It seems that on AMD processors PTE's accessed bit is
1028 * being set by the CPU hardware before the NPF vmexit.
1029 * This is not expected behaviour and our tests fail because
1031 * A workaround here is to disable support for
1032 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1033 * In this case userspace can know if there is support using
1034 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1036 * If future AMD CPU models change the behaviour described above,
1037 * this variable can be changed accordingly
1039 allow_smaller_maxphyaddr = !npt_enabled;
1044 svm_hardware_teardown();
1048 static void init_seg(struct vmcb_seg *seg)
1051 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1052 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1053 seg->limit = 0xffff;
1057 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1060 seg->attrib = SVM_SELECTOR_P_MASK | type;
1061 seg->limit = 0xffff;
1065 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1067 struct vcpu_svm *svm = to_svm(vcpu);
1068 u64 g_tsc_offset = 0;
1070 if (is_guest_mode(vcpu)) {
1071 /* Write L1's TSC offset. */
1072 g_tsc_offset = svm->vmcb->control.tsc_offset -
1073 svm->nested.hsave->control.tsc_offset;
1074 svm->nested.hsave->control.tsc_offset = offset;
1077 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1078 svm->vmcb->control.tsc_offset - g_tsc_offset,
1081 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1083 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1084 return svm->vmcb->control.tsc_offset;
1087 static void svm_check_invpcid(struct vcpu_svm *svm)
1090 * Intercept INVPCID instruction only if shadow page table is
1091 * enabled. Interception is not required with nested page table
1094 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1096 svm_set_intercept(svm, INTERCEPT_INVPCID);
1098 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1102 static void init_vmcb(struct vcpu_svm *svm)
1104 struct vmcb_control_area *control = &svm->vmcb->control;
1105 struct vmcb_save_area *save = &svm->vmcb->save;
1107 svm->vcpu.arch.hflags = 0;
1109 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1110 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1111 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1112 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1113 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1114 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1115 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1116 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1118 set_dr_intercepts(svm);
1120 set_exception_intercept(svm, PF_VECTOR);
1121 set_exception_intercept(svm, UD_VECTOR);
1122 set_exception_intercept(svm, MC_VECTOR);
1123 set_exception_intercept(svm, AC_VECTOR);
1124 set_exception_intercept(svm, DB_VECTOR);
1126 * Guest access to VMware backdoor ports could legitimately
1127 * trigger #GP because of TSS I/O permission bitmap.
1128 * We intercept those #GP and allow access to them anyway
1131 if (enable_vmware_backdoor)
1132 set_exception_intercept(svm, GP_VECTOR);
1134 svm_set_intercept(svm, INTERCEPT_INTR);
1135 svm_set_intercept(svm, INTERCEPT_NMI);
1136 svm_set_intercept(svm, INTERCEPT_SMI);
1137 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1138 svm_set_intercept(svm, INTERCEPT_RDPMC);
1139 svm_set_intercept(svm, INTERCEPT_CPUID);
1140 svm_set_intercept(svm, INTERCEPT_INVD);
1141 svm_set_intercept(svm, INTERCEPT_INVLPG);
1142 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1143 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1144 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1145 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1146 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1147 svm_set_intercept(svm, INTERCEPT_VMRUN);
1148 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1149 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1150 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1151 svm_set_intercept(svm, INTERCEPT_STGI);
1152 svm_set_intercept(svm, INTERCEPT_CLGI);
1153 svm_set_intercept(svm, INTERCEPT_SKINIT);
1154 svm_set_intercept(svm, INTERCEPT_WBINVD);
1155 svm_set_intercept(svm, INTERCEPT_XSETBV);
1156 svm_set_intercept(svm, INTERCEPT_RDPRU);
1157 svm_set_intercept(svm, INTERCEPT_RSM);
1159 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1160 svm_set_intercept(svm, INTERCEPT_MONITOR);
1161 svm_set_intercept(svm, INTERCEPT_MWAIT);
1164 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1165 svm_set_intercept(svm, INTERCEPT_HLT);
1167 control->iopm_base_pa = __sme_set(iopm_base);
1168 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1169 control->int_ctl = V_INTR_MASKING_MASK;
1171 init_seg(&save->es);
1172 init_seg(&save->ss);
1173 init_seg(&save->ds);
1174 init_seg(&save->fs);
1175 init_seg(&save->gs);
1177 save->cs.selector = 0xf000;
1178 save->cs.base = 0xffff0000;
1179 /* Executable/Readable Code Segment */
1180 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1181 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1182 save->cs.limit = 0xffff;
1184 save->gdtr.limit = 0xffff;
1185 save->idtr.limit = 0xffff;
1187 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1188 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1190 svm_set_efer(&svm->vcpu, 0);
1191 save->dr6 = 0xffff0ff0;
1192 kvm_set_rflags(&svm->vcpu, 2);
1193 save->rip = 0x0000fff0;
1194 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1197 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1198 * It also updates the guest-visible cr0 value.
1200 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1201 kvm_mmu_reset_context(&svm->vcpu);
1203 save->cr4 = X86_CR4_PAE;
1207 /* Setup VMCB for Nested Paging */
1208 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1209 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1210 clr_exception_intercept(svm, PF_VECTOR);
1211 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1212 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1213 save->g_pat = svm->vcpu.arch.pat;
1217 svm->asid_generation = 0;
1219 svm->nested.vmcb12_gpa = 0;
1220 svm->vcpu.arch.hflags = 0;
1222 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1223 control->pause_filter_count = pause_filter_count;
1224 if (pause_filter_thresh)
1225 control->pause_filter_thresh = pause_filter_thresh;
1226 svm_set_intercept(svm, INTERCEPT_PAUSE);
1228 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1231 svm_check_invpcid(svm);
1233 if (kvm_vcpu_apicv_active(&svm->vcpu))
1234 avic_init_vmcb(svm);
1237 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1238 * in VMCB and clear intercepts to avoid #VMEXIT.
1241 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1242 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1243 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1247 svm_clr_intercept(svm, INTERCEPT_STGI);
1248 svm_clr_intercept(svm, INTERCEPT_CLGI);
1249 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1252 if (sev_guest(svm->vcpu.kvm)) {
1253 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1254 clr_exception_intercept(svm, UD_VECTOR);
1257 vmcb_mark_all_dirty(svm->vmcb);
1263 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1265 struct vcpu_svm *svm = to_svm(vcpu);
1270 svm->virt_spec_ctrl = 0;
1273 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1274 MSR_IA32_APICBASE_ENABLE;
1275 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1276 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1280 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1281 kvm_rdx_write(vcpu, eax);
1283 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1284 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1287 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1289 struct vcpu_svm *svm;
1290 struct page *vmcb_page;
1293 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1297 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1301 err = avic_init_vcpu(svm);
1303 goto error_free_vmcb_page;
1305 /* We initialize this flag to true to make sure that the is_running
1306 * bit would be set the first time the vcpu is loaded.
1308 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1309 svm->avic_is_running = true;
1311 svm->msrpm = svm_vcpu_alloc_msrpm();
1313 goto error_free_vmcb_page;
1315 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1317 svm->vmcb = page_address(vmcb_page);
1318 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1319 svm->asid_generation = 0;
1322 svm_init_osvw(vcpu);
1323 vcpu->arch.microcode_version = 0x01000065;
1327 error_free_vmcb_page:
1328 __free_page(vmcb_page);
1333 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1337 for_each_online_cpu(i)
1338 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1341 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1343 struct vcpu_svm *svm = to_svm(vcpu);
1346 * The vmcb page can be recycled, causing a false negative in
1347 * svm_vcpu_load(). So, ensure that no logical CPU has this
1348 * vmcb page recorded as its current vmcb.
1350 svm_clear_current_vmcb(svm->vmcb);
1352 svm_free_nested(svm);
1354 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1355 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1358 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1360 struct vcpu_svm *svm = to_svm(vcpu);
1361 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1364 if (unlikely(cpu != vcpu->cpu)) {
1365 svm->asid_generation = 0;
1366 vmcb_mark_all_dirty(svm->vmcb);
1369 #ifdef CONFIG_X86_64
1370 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1372 savesegment(fs, svm->host.fs);
1373 savesegment(gs, svm->host.gs);
1374 svm->host.ldt = kvm_read_ldt();
1376 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1377 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1379 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1380 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1381 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1382 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1383 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1386 /* This assumes that the kernel never uses MSR_TSC_AUX */
1387 if (static_cpu_has(X86_FEATURE_RDTSCP))
1388 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1390 if (sd->current_vmcb != svm->vmcb) {
1391 sd->current_vmcb = svm->vmcb;
1392 indirect_branch_prediction_barrier();
1394 avic_vcpu_load(vcpu, cpu);
1397 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1399 struct vcpu_svm *svm = to_svm(vcpu);
1402 avic_vcpu_put(vcpu);
1404 ++vcpu->stat.host_state_reload;
1405 kvm_load_ldt(svm->host.ldt);
1406 #ifdef CONFIG_X86_64
1407 loadsegment(fs, svm->host.fs);
1408 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1409 load_gs_index(svm->host.gs);
1411 #ifdef CONFIG_X86_32_LAZY_GS
1412 loadsegment(gs, svm->host.gs);
1415 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1416 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1419 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1421 struct vcpu_svm *svm = to_svm(vcpu);
1422 unsigned long rflags = svm->vmcb->save.rflags;
1424 if (svm->nmi_singlestep) {
1425 /* Hide our flags if they were not set by the guest */
1426 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1427 rflags &= ~X86_EFLAGS_TF;
1428 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1429 rflags &= ~X86_EFLAGS_RF;
1434 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1436 if (to_svm(vcpu)->nmi_singlestep)
1437 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1440 * Any change of EFLAGS.VM is accompanied by a reload of SS
1441 * (caused by either a task switch or an inter-privilege IRET),
1442 * so we do not need to update the CPL here.
1444 to_svm(vcpu)->vmcb->save.rflags = rflags;
1447 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1450 case VCPU_EXREG_PDPTR:
1451 BUG_ON(!npt_enabled);
1452 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1459 static void svm_set_vintr(struct vcpu_svm *svm)
1461 struct vmcb_control_area *control;
1463 /* The following fields are ignored when AVIC is enabled */
1464 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1465 svm_set_intercept(svm, INTERCEPT_VINTR);
1468 * This is just a dummy VINTR to actually cause a vmexit to happen.
1469 * Actual injection of virtual interrupts happens through EVENTINJ.
1471 control = &svm->vmcb->control;
1472 control->int_vector = 0x0;
1473 control->int_ctl &= ~V_INTR_PRIO_MASK;
1474 control->int_ctl |= V_IRQ_MASK |
1475 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1476 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1479 static void svm_clear_vintr(struct vcpu_svm *svm)
1481 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1482 svm_clr_intercept(svm, INTERCEPT_VINTR);
1484 /* Drop int_ctl fields related to VINTR injection. */
1485 svm->vmcb->control.int_ctl &= mask;
1486 if (is_guest_mode(&svm->vcpu)) {
1487 svm->nested.hsave->control.int_ctl &= mask;
1489 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1490 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1491 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1494 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1497 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1499 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1502 case VCPU_SREG_CS: return &save->cs;
1503 case VCPU_SREG_DS: return &save->ds;
1504 case VCPU_SREG_ES: return &save->es;
1505 case VCPU_SREG_FS: return &save->fs;
1506 case VCPU_SREG_GS: return &save->gs;
1507 case VCPU_SREG_SS: return &save->ss;
1508 case VCPU_SREG_TR: return &save->tr;
1509 case VCPU_SREG_LDTR: return &save->ldtr;
1515 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1517 struct vmcb_seg *s = svm_seg(vcpu, seg);
1522 static void svm_get_segment(struct kvm_vcpu *vcpu,
1523 struct kvm_segment *var, int seg)
1525 struct vmcb_seg *s = svm_seg(vcpu, seg);
1527 var->base = s->base;
1528 var->limit = s->limit;
1529 var->selector = s->selector;
1530 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1531 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1532 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1533 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1534 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1535 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1536 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1539 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1540 * However, the SVM spec states that the G bit is not observed by the
1541 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1542 * So let's synthesize a legal G bit for all segments, this helps
1543 * running KVM nested. It also helps cross-vendor migration, because
1544 * Intel's vmentry has a check on the 'G' bit.
1546 var->g = s->limit > 0xfffff;
1549 * AMD's VMCB does not have an explicit unusable field, so emulate it
1550 * for cross vendor migration purposes by "not present"
1552 var->unusable = !var->present;
1557 * Work around a bug where the busy flag in the tr selector
1567 * The accessed bit must always be set in the segment
1568 * descriptor cache, although it can be cleared in the
1569 * descriptor, the cached bit always remains at 1. Since
1570 * Intel has a check on this, set it here to support
1571 * cross-vendor migration.
1578 * On AMD CPUs sometimes the DB bit in the segment
1579 * descriptor is left as 1, although the whole segment has
1580 * been made unusable. Clear it here to pass an Intel VMX
1581 * entry check when cross vendor migrating.
1585 /* This is symmetric with svm_set_segment() */
1586 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1591 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1593 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1598 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1600 struct vcpu_svm *svm = to_svm(vcpu);
1602 dt->size = svm->vmcb->save.idtr.limit;
1603 dt->address = svm->vmcb->save.idtr.base;
1606 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1608 struct vcpu_svm *svm = to_svm(vcpu);
1610 svm->vmcb->save.idtr.limit = dt->size;
1611 svm->vmcb->save.idtr.base = dt->address ;
1612 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1615 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1617 struct vcpu_svm *svm = to_svm(vcpu);
1619 dt->size = svm->vmcb->save.gdtr.limit;
1620 dt->address = svm->vmcb->save.gdtr.base;
1623 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1625 struct vcpu_svm *svm = to_svm(vcpu);
1627 svm->vmcb->save.gdtr.limit = dt->size;
1628 svm->vmcb->save.gdtr.base = dt->address ;
1629 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1632 static void update_cr0_intercept(struct vcpu_svm *svm)
1634 ulong gcr0 = svm->vcpu.arch.cr0;
1635 u64 *hcr0 = &svm->vmcb->save.cr0;
1637 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1638 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1640 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1642 if (gcr0 == *hcr0) {
1643 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1644 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1646 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1647 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1651 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1653 struct vcpu_svm *svm = to_svm(vcpu);
1655 #ifdef CONFIG_X86_64
1656 if (vcpu->arch.efer & EFER_LME) {
1657 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1658 vcpu->arch.efer |= EFER_LMA;
1659 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1662 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1663 vcpu->arch.efer &= ~EFER_LMA;
1664 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1668 vcpu->arch.cr0 = cr0;
1671 cr0 |= X86_CR0_PG | X86_CR0_WP;
1674 * re-enable caching here because the QEMU bios
1675 * does not do it - this results in some delay at
1678 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1679 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1680 svm->vmcb->save.cr0 = cr0;
1681 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1682 update_cr0_intercept(svm);
1685 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1687 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1688 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1690 if (cr4 & X86_CR4_VMXE)
1693 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1694 svm_flush_tlb(vcpu);
1696 vcpu->arch.cr4 = cr4;
1699 cr4 |= host_cr4_mce;
1700 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1701 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1705 static void svm_set_segment(struct kvm_vcpu *vcpu,
1706 struct kvm_segment *var, int seg)
1708 struct vcpu_svm *svm = to_svm(vcpu);
1709 struct vmcb_seg *s = svm_seg(vcpu, seg);
1711 s->base = var->base;
1712 s->limit = var->limit;
1713 s->selector = var->selector;
1714 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1715 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1716 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1717 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1718 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1719 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1720 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1721 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1724 * This is always accurate, except if SYSRET returned to a segment
1725 * with SS.DPL != 3. Intel does not have this quirk, and always
1726 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1727 * would entail passing the CPL to userspace and back.
1729 if (seg == VCPU_SREG_SS)
1730 /* This is symmetric with svm_get_segment() */
1731 svm->vmcb->save.cpl = (var->dpl & 3);
1733 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1736 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1738 struct vcpu_svm *svm = to_svm(vcpu);
1740 clr_exception_intercept(svm, BP_VECTOR);
1742 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1743 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1744 set_exception_intercept(svm, BP_VECTOR);
1748 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1750 if (sd->next_asid > sd->max_asid) {
1751 ++sd->asid_generation;
1752 sd->next_asid = sd->min_asid;
1753 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1756 svm->asid_generation = sd->asid_generation;
1757 svm->vmcb->control.asid = sd->next_asid++;
1759 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1762 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1764 struct vmcb *vmcb = svm->vmcb;
1766 if (unlikely(value != vmcb->save.dr6)) {
1767 vmcb->save.dr6 = value;
1768 vmcb_mark_dirty(vmcb, VMCB_DR);
1772 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1774 struct vcpu_svm *svm = to_svm(vcpu);
1776 get_debugreg(vcpu->arch.db[0], 0);
1777 get_debugreg(vcpu->arch.db[1], 1);
1778 get_debugreg(vcpu->arch.db[2], 2);
1779 get_debugreg(vcpu->arch.db[3], 3);
1781 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1782 * because db_interception might need it. We can do it before vmentry.
1784 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1785 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1786 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1787 set_dr_intercepts(svm);
1790 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1792 struct vcpu_svm *svm = to_svm(vcpu);
1794 svm->vmcb->save.dr7 = value;
1795 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1798 static int pf_interception(struct vcpu_svm *svm)
1800 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1801 u64 error_code = svm->vmcb->control.exit_info_1;
1803 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1804 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1805 svm->vmcb->control.insn_bytes : NULL,
1806 svm->vmcb->control.insn_len);
1809 static int npf_interception(struct vcpu_svm *svm)
1811 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1812 u64 error_code = svm->vmcb->control.exit_info_1;
1814 trace_kvm_page_fault(fault_address, error_code);
1815 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1816 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1817 svm->vmcb->control.insn_bytes : NULL,
1818 svm->vmcb->control.insn_len);
1821 static int db_interception(struct vcpu_svm *svm)
1823 struct kvm_run *kvm_run = svm->vcpu.run;
1824 struct kvm_vcpu *vcpu = &svm->vcpu;
1826 if (!(svm->vcpu.guest_debug &
1827 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1828 !svm->nmi_singlestep) {
1829 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1830 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1834 if (svm->nmi_singlestep) {
1835 disable_nmi_singlestep(svm);
1836 /* Make sure we check for pending NMIs upon entry */
1837 kvm_make_request(KVM_REQ_EVENT, vcpu);
1840 if (svm->vcpu.guest_debug &
1841 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1842 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1843 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1844 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1845 kvm_run->debug.arch.pc =
1846 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1847 kvm_run->debug.arch.exception = DB_VECTOR;
1854 static int bp_interception(struct vcpu_svm *svm)
1856 struct kvm_run *kvm_run = svm->vcpu.run;
1858 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1859 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1860 kvm_run->debug.arch.exception = BP_VECTOR;
1864 static int ud_interception(struct vcpu_svm *svm)
1866 return handle_ud(&svm->vcpu);
1869 static int ac_interception(struct vcpu_svm *svm)
1871 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1875 static int gp_interception(struct vcpu_svm *svm)
1877 struct kvm_vcpu *vcpu = &svm->vcpu;
1878 u32 error_code = svm->vmcb->control.exit_info_1;
1880 WARN_ON_ONCE(!enable_vmware_backdoor);
1883 * VMware backdoor emulation on #GP interception only handles IN{S},
1884 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1887 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1890 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1893 static bool is_erratum_383(void)
1898 if (!erratum_383_found)
1901 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1905 /* Bit 62 may or may not be set for this mce */
1906 value &= ~(1ULL << 62);
1908 if (value != 0xb600000000010015ULL)
1911 /* Clear MCi_STATUS registers */
1912 for (i = 0; i < 6; ++i)
1913 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1915 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1919 value &= ~(1ULL << 2);
1920 low = lower_32_bits(value);
1921 high = upper_32_bits(value);
1923 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1926 /* Flush tlb to evict multi-match entries */
1933 * Trigger machine check on the host. We assume all the MSRs are already set up
1934 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1935 * We pass a fake environment to the machine check handler because we want
1936 * the guest to be always treated like user space, no matter what context
1937 * it used internally.
1939 static void kvm_machine_check(void)
1941 #if defined(CONFIG_X86_MCE)
1942 struct pt_regs regs = {
1943 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1944 .flags = X86_EFLAGS_IF,
1947 do_machine_check(®s);
1951 static void svm_handle_mce(struct vcpu_svm *svm)
1953 if (is_erratum_383()) {
1955 * Erratum 383 triggered. Guest state is corrupt so kill the
1958 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1960 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1966 * On an #MC intercept the MCE handler is not called automatically in
1967 * the host. So do it by hand here.
1969 kvm_machine_check();
1972 static int mc_interception(struct vcpu_svm *svm)
1977 static int shutdown_interception(struct vcpu_svm *svm)
1979 struct kvm_run *kvm_run = svm->vcpu.run;
1982 * VMCB is undefined after a SHUTDOWN intercept
1983 * so reinitialize it.
1985 clear_page(svm->vmcb);
1988 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1992 static int io_interception(struct vcpu_svm *svm)
1994 struct kvm_vcpu *vcpu = &svm->vcpu;
1995 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1996 int size, in, string;
1999 ++svm->vcpu.stat.io_exits;
2000 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2001 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2003 return kvm_emulate_instruction(vcpu, 0);
2005 port = io_info >> 16;
2006 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2007 svm->next_rip = svm->vmcb->control.exit_info_2;
2009 return kvm_fast_pio(&svm->vcpu, size, port, in);
2012 static int nmi_interception(struct vcpu_svm *svm)
2017 static int intr_interception(struct vcpu_svm *svm)
2019 ++svm->vcpu.stat.irq_exits;
2023 static int nop_on_interception(struct vcpu_svm *svm)
2028 static int halt_interception(struct vcpu_svm *svm)
2030 return kvm_emulate_halt(&svm->vcpu);
2033 static int vmmcall_interception(struct vcpu_svm *svm)
2035 return kvm_emulate_hypercall(&svm->vcpu);
2038 static int vmload_interception(struct vcpu_svm *svm)
2040 struct vmcb *nested_vmcb;
2041 struct kvm_host_map map;
2044 if (nested_svm_check_permissions(svm))
2047 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2050 kvm_inject_gp(&svm->vcpu, 0);
2054 nested_vmcb = map.hva;
2056 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2058 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2059 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2064 static int vmsave_interception(struct vcpu_svm *svm)
2066 struct vmcb *nested_vmcb;
2067 struct kvm_host_map map;
2070 if (nested_svm_check_permissions(svm))
2073 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2076 kvm_inject_gp(&svm->vcpu, 0);
2080 nested_vmcb = map.hva;
2082 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2084 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2085 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2090 static int vmrun_interception(struct vcpu_svm *svm)
2092 if (nested_svm_check_permissions(svm))
2095 return nested_svm_vmrun(svm);
2098 void svm_set_gif(struct vcpu_svm *svm, bool value)
2102 * If VGIF is enabled, the STGI intercept is only added to
2103 * detect the opening of the SMI/NMI window; remove it now.
2104 * Likewise, clear the VINTR intercept, we will set it
2105 * again while processing KVM_REQ_EVENT if needed.
2107 if (vgif_enabled(svm))
2108 svm_clr_intercept(svm, INTERCEPT_STGI);
2109 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2110 svm_clear_vintr(svm);
2113 if (svm->vcpu.arch.smi_pending ||
2114 svm->vcpu.arch.nmi_pending ||
2115 kvm_cpu_has_injectable_intr(&svm->vcpu))
2116 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2121 * After a CLGI no interrupts should come. But if vGIF is
2122 * in use, we still rely on the VINTR intercept (rather than
2123 * STGI) to detect an open interrupt window.
2125 if (!vgif_enabled(svm))
2126 svm_clear_vintr(svm);
2130 static int stgi_interception(struct vcpu_svm *svm)
2134 if (nested_svm_check_permissions(svm))
2137 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2138 svm_set_gif(svm, true);
2142 static int clgi_interception(struct vcpu_svm *svm)
2146 if (nested_svm_check_permissions(svm))
2149 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2150 svm_set_gif(svm, false);
2154 static int invlpga_interception(struct vcpu_svm *svm)
2156 struct kvm_vcpu *vcpu = &svm->vcpu;
2158 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2159 kvm_rax_read(&svm->vcpu));
2161 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2162 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2164 return kvm_skip_emulated_instruction(&svm->vcpu);
2167 static int skinit_interception(struct vcpu_svm *svm)
2169 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2171 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2175 static int wbinvd_interception(struct vcpu_svm *svm)
2177 return kvm_emulate_wbinvd(&svm->vcpu);
2180 static int xsetbv_interception(struct vcpu_svm *svm)
2182 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2183 u32 index = kvm_rcx_read(&svm->vcpu);
2185 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2186 return kvm_skip_emulated_instruction(&svm->vcpu);
2192 static int rdpru_interception(struct vcpu_svm *svm)
2194 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2198 static int task_switch_interception(struct vcpu_svm *svm)
2202 int int_type = svm->vmcb->control.exit_int_info &
2203 SVM_EXITINTINFO_TYPE_MASK;
2204 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2206 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2208 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2209 bool has_error_code = false;
2212 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2214 if (svm->vmcb->control.exit_info_2 &
2215 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2216 reason = TASK_SWITCH_IRET;
2217 else if (svm->vmcb->control.exit_info_2 &
2218 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2219 reason = TASK_SWITCH_JMP;
2221 reason = TASK_SWITCH_GATE;
2223 reason = TASK_SWITCH_CALL;
2225 if (reason == TASK_SWITCH_GATE) {
2227 case SVM_EXITINTINFO_TYPE_NMI:
2228 svm->vcpu.arch.nmi_injected = false;
2230 case SVM_EXITINTINFO_TYPE_EXEPT:
2231 if (svm->vmcb->control.exit_info_2 &
2232 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2233 has_error_code = true;
2235 (u32)svm->vmcb->control.exit_info_2;
2237 kvm_clear_exception_queue(&svm->vcpu);
2239 case SVM_EXITINTINFO_TYPE_INTR:
2240 kvm_clear_interrupt_queue(&svm->vcpu);
2247 if (reason != TASK_SWITCH_GATE ||
2248 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2249 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2250 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2251 if (!skip_emulated_instruction(&svm->vcpu))
2255 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2258 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2259 has_error_code, error_code);
2262 static int cpuid_interception(struct vcpu_svm *svm)
2264 return kvm_emulate_cpuid(&svm->vcpu);
2267 static int iret_interception(struct vcpu_svm *svm)
2269 ++svm->vcpu.stat.nmi_window_exits;
2270 svm_clr_intercept(svm, INTERCEPT_IRET);
2271 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2272 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2273 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2277 static int invd_interception(struct vcpu_svm *svm)
2279 /* Treat an INVD instruction as a NOP and just skip it. */
2280 return kvm_skip_emulated_instruction(&svm->vcpu);
2283 static int invlpg_interception(struct vcpu_svm *svm)
2285 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2286 return kvm_emulate_instruction(&svm->vcpu, 0);
2288 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2289 return kvm_skip_emulated_instruction(&svm->vcpu);
2292 static int emulate_on_interception(struct vcpu_svm *svm)
2294 return kvm_emulate_instruction(&svm->vcpu, 0);
2297 static int rsm_interception(struct vcpu_svm *svm)
2299 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2302 static int rdpmc_interception(struct vcpu_svm *svm)
2307 return emulate_on_interception(svm);
2309 err = kvm_rdpmc(&svm->vcpu);
2310 return kvm_complete_insn_gp(&svm->vcpu, err);
2313 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2316 unsigned long cr0 = svm->vcpu.arch.cr0;
2319 if (!is_guest_mode(&svm->vcpu) ||
2320 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2323 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2324 val &= ~SVM_CR0_SELECTIVE_MASK;
2327 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2328 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2334 #define CR_VALID (1ULL << 63)
2336 static int cr_interception(struct vcpu_svm *svm)
2342 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2343 return emulate_on_interception(svm);
2345 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2346 return emulate_on_interception(svm);
2348 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2349 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2350 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2352 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2355 if (cr >= 16) { /* mov to cr */
2357 val = kvm_register_read(&svm->vcpu, reg);
2358 trace_kvm_cr_write(cr, val);
2361 if (!check_selective_cr0_intercepted(svm, val))
2362 err = kvm_set_cr0(&svm->vcpu, val);
2368 err = kvm_set_cr3(&svm->vcpu, val);
2371 err = kvm_set_cr4(&svm->vcpu, val);
2374 err = kvm_set_cr8(&svm->vcpu, val);
2377 WARN(1, "unhandled write to CR%d", cr);
2378 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2381 } else { /* mov from cr */
2384 val = kvm_read_cr0(&svm->vcpu);
2387 val = svm->vcpu.arch.cr2;
2390 val = kvm_read_cr3(&svm->vcpu);
2393 val = kvm_read_cr4(&svm->vcpu);
2396 val = kvm_get_cr8(&svm->vcpu);
2399 WARN(1, "unhandled read from CR%d", cr);
2400 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2403 kvm_register_write(&svm->vcpu, reg, val);
2404 trace_kvm_cr_read(cr, val);
2406 return kvm_complete_insn_gp(&svm->vcpu, err);
2409 static int dr_interception(struct vcpu_svm *svm)
2414 if (svm->vcpu.guest_debug == 0) {
2416 * No more DR vmexits; force a reload of the debug registers
2417 * and reenter on this instruction. The next vmexit will
2418 * retrieve the full state of the debug registers.
2420 clr_dr_intercepts(svm);
2421 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2425 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2426 return emulate_on_interception(svm);
2428 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2429 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2431 if (dr >= 16) { /* mov to DRn */
2432 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2434 val = kvm_register_read(&svm->vcpu, reg);
2435 kvm_set_dr(&svm->vcpu, dr - 16, val);
2437 if (!kvm_require_dr(&svm->vcpu, dr))
2439 kvm_get_dr(&svm->vcpu, dr, &val);
2440 kvm_register_write(&svm->vcpu, reg, val);
2443 return kvm_skip_emulated_instruction(&svm->vcpu);
2446 static int cr8_write_interception(struct vcpu_svm *svm)
2448 struct kvm_run *kvm_run = svm->vcpu.run;
2451 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2452 /* instruction emulation calls kvm_set_cr8() */
2453 r = cr_interception(svm);
2454 if (lapic_in_kernel(&svm->vcpu))
2456 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2458 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2462 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2466 switch (msr->index) {
2467 case MSR_F10H_DECFG:
2468 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2469 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2471 case MSR_IA32_PERF_CAPABILITIES:
2474 return KVM_MSR_RET_INVALID;
2480 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2482 struct vcpu_svm *svm = to_svm(vcpu);
2484 switch (msr_info->index) {
2486 msr_info->data = svm->vmcb->save.star;
2488 #ifdef CONFIG_X86_64
2490 msr_info->data = svm->vmcb->save.lstar;
2493 msr_info->data = svm->vmcb->save.cstar;
2495 case MSR_KERNEL_GS_BASE:
2496 msr_info->data = svm->vmcb->save.kernel_gs_base;
2498 case MSR_SYSCALL_MASK:
2499 msr_info->data = svm->vmcb->save.sfmask;
2502 case MSR_IA32_SYSENTER_CS:
2503 msr_info->data = svm->vmcb->save.sysenter_cs;
2505 case MSR_IA32_SYSENTER_EIP:
2506 msr_info->data = svm->sysenter_eip;
2508 case MSR_IA32_SYSENTER_ESP:
2509 msr_info->data = svm->sysenter_esp;
2512 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2514 msr_info->data = svm->tsc_aux;
2517 * Nobody will change the following 5 values in the VMCB so we can
2518 * safely return them on rdmsr. They will always be 0 until LBRV is
2521 case MSR_IA32_DEBUGCTLMSR:
2522 msr_info->data = svm->vmcb->save.dbgctl;
2524 case MSR_IA32_LASTBRANCHFROMIP:
2525 msr_info->data = svm->vmcb->save.br_from;
2527 case MSR_IA32_LASTBRANCHTOIP:
2528 msr_info->data = svm->vmcb->save.br_to;
2530 case MSR_IA32_LASTINTFROMIP:
2531 msr_info->data = svm->vmcb->save.last_excp_from;
2533 case MSR_IA32_LASTINTTOIP:
2534 msr_info->data = svm->vmcb->save.last_excp_to;
2536 case MSR_VM_HSAVE_PA:
2537 msr_info->data = svm->nested.hsave_msr;
2540 msr_info->data = svm->nested.vm_cr_msr;
2542 case MSR_IA32_SPEC_CTRL:
2543 if (!msr_info->host_initiated &&
2544 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2545 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2546 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2547 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2550 msr_info->data = svm->spec_ctrl;
2552 case MSR_AMD64_VIRT_SPEC_CTRL:
2553 if (!msr_info->host_initiated &&
2554 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2557 msr_info->data = svm->virt_spec_ctrl;
2559 case MSR_F15H_IC_CFG: {
2563 family = guest_cpuid_family(vcpu);
2564 model = guest_cpuid_model(vcpu);
2566 if (family < 0 || model < 0)
2567 return kvm_get_msr_common(vcpu, msr_info);
2571 if (family == 0x15 &&
2572 (model >= 0x2 && model < 0x20))
2573 msr_info->data = 0x1E;
2576 case MSR_F10H_DECFG:
2577 msr_info->data = svm->msr_decfg;
2580 return kvm_get_msr_common(vcpu, msr_info);
2585 static int rdmsr_interception(struct vcpu_svm *svm)
2587 return kvm_emulate_rdmsr(&svm->vcpu);
2590 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2592 struct vcpu_svm *svm = to_svm(vcpu);
2593 int svm_dis, chg_mask;
2595 if (data & ~SVM_VM_CR_VALID_MASK)
2598 chg_mask = SVM_VM_CR_VALID_MASK;
2600 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2601 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2603 svm->nested.vm_cr_msr &= ~chg_mask;
2604 svm->nested.vm_cr_msr |= (data & chg_mask);
2606 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2608 /* check for svm_disable while efer.svme is set */
2609 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2615 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2617 struct vcpu_svm *svm = to_svm(vcpu);
2619 u32 ecx = msr->index;
2620 u64 data = msr->data;
2622 case MSR_IA32_CR_PAT:
2623 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2625 vcpu->arch.pat = data;
2626 svm->vmcb->save.g_pat = data;
2627 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2629 case MSR_IA32_SPEC_CTRL:
2630 if (!msr->host_initiated &&
2631 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2632 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2633 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2634 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2637 if (kvm_spec_ctrl_test_value(data))
2640 svm->spec_ctrl = data;
2646 * When it's written (to non-zero) for the first time, pass
2650 * The handling of the MSR bitmap for L2 guests is done in
2651 * nested_svm_vmrun_msrpm.
2652 * We update the L1 MSR bit as well since it will end up
2653 * touching the MSR anyway now.
2655 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2657 case MSR_IA32_PRED_CMD:
2658 if (!msr->host_initiated &&
2659 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2662 if (data & ~PRED_CMD_IBPB)
2664 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2669 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2670 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2672 case MSR_AMD64_VIRT_SPEC_CTRL:
2673 if (!msr->host_initiated &&
2674 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2677 if (data & ~SPEC_CTRL_SSBD)
2680 svm->virt_spec_ctrl = data;
2683 svm->vmcb->save.star = data;
2685 #ifdef CONFIG_X86_64
2687 svm->vmcb->save.lstar = data;
2690 svm->vmcb->save.cstar = data;
2692 case MSR_KERNEL_GS_BASE:
2693 svm->vmcb->save.kernel_gs_base = data;
2695 case MSR_SYSCALL_MASK:
2696 svm->vmcb->save.sfmask = data;
2699 case MSR_IA32_SYSENTER_CS:
2700 svm->vmcb->save.sysenter_cs = data;
2702 case MSR_IA32_SYSENTER_EIP:
2703 svm->sysenter_eip = data;
2704 svm->vmcb->save.sysenter_eip = data;
2706 case MSR_IA32_SYSENTER_ESP:
2707 svm->sysenter_esp = data;
2708 svm->vmcb->save.sysenter_esp = data;
2711 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2715 * This is rare, so we update the MSR here instead of using
2716 * direct_access_msrs. Doing that would require a rdmsr in
2719 svm->tsc_aux = data;
2720 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2722 case MSR_IA32_DEBUGCTLMSR:
2723 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2724 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2728 if (data & DEBUGCTL_RESERVED_BITS)
2731 svm->vmcb->save.dbgctl = data;
2732 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2733 if (data & (1ULL<<0))
2734 svm_enable_lbrv(vcpu);
2736 svm_disable_lbrv(vcpu);
2738 case MSR_VM_HSAVE_PA:
2739 svm->nested.hsave_msr = data;
2742 return svm_set_vm_cr(vcpu, data);
2744 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2746 case MSR_F10H_DECFG: {
2747 struct kvm_msr_entry msr_entry;
2749 msr_entry.index = msr->index;
2750 if (svm_get_msr_feature(&msr_entry))
2753 /* Check the supported bits */
2754 if (data & ~msr_entry.data)
2757 /* Don't allow the guest to change a bit, #GP */
2758 if (!msr->host_initiated && (data ^ msr_entry.data))
2761 svm->msr_decfg = data;
2764 case MSR_IA32_APICBASE:
2765 if (kvm_vcpu_apicv_active(vcpu))
2766 avic_update_vapic_bar(to_svm(vcpu), data);
2769 return kvm_set_msr_common(vcpu, msr);
2774 static int wrmsr_interception(struct vcpu_svm *svm)
2776 return kvm_emulate_wrmsr(&svm->vcpu);
2779 static int msr_interception(struct vcpu_svm *svm)
2781 if (svm->vmcb->control.exit_info_1)
2782 return wrmsr_interception(svm);
2784 return rdmsr_interception(svm);
2787 static int interrupt_window_interception(struct vcpu_svm *svm)
2789 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2790 svm_clear_vintr(svm);
2793 * For AVIC, the only reason to end up here is ExtINTs.
2794 * In this case AVIC was temporarily disabled for
2795 * requesting the IRQ window and we have to re-enable it.
2797 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2799 ++svm->vcpu.stat.irq_window_exits;
2803 static int pause_interception(struct vcpu_svm *svm)
2805 struct kvm_vcpu *vcpu = &svm->vcpu;
2806 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2808 if (!kvm_pause_in_guest(vcpu->kvm))
2809 grow_ple_window(vcpu);
2811 kvm_vcpu_on_spin(vcpu, in_kernel);
2815 static int nop_interception(struct vcpu_svm *svm)
2817 return kvm_skip_emulated_instruction(&(svm->vcpu));
2820 static int monitor_interception(struct vcpu_svm *svm)
2822 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2823 return nop_interception(svm);
2826 static int mwait_interception(struct vcpu_svm *svm)
2828 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2829 return nop_interception(svm);
2832 static int invpcid_interception(struct vcpu_svm *svm)
2834 struct kvm_vcpu *vcpu = &svm->vcpu;
2838 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2839 kvm_queue_exception(vcpu, UD_VECTOR);
2844 * For an INVPCID intercept:
2845 * EXITINFO1 provides the linear address of the memory operand.
2846 * EXITINFO2 provides the contents of the register operand.
2848 type = svm->vmcb->control.exit_info_2;
2849 gva = svm->vmcb->control.exit_info_1;
2852 kvm_inject_gp(vcpu, 0);
2856 return kvm_handle_invpcid(vcpu, type, gva);
2859 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2860 [SVM_EXIT_READ_CR0] = cr_interception,
2861 [SVM_EXIT_READ_CR3] = cr_interception,
2862 [SVM_EXIT_READ_CR4] = cr_interception,
2863 [SVM_EXIT_READ_CR8] = cr_interception,
2864 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
2865 [SVM_EXIT_WRITE_CR0] = cr_interception,
2866 [SVM_EXIT_WRITE_CR3] = cr_interception,
2867 [SVM_EXIT_WRITE_CR4] = cr_interception,
2868 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2869 [SVM_EXIT_READ_DR0] = dr_interception,
2870 [SVM_EXIT_READ_DR1] = dr_interception,
2871 [SVM_EXIT_READ_DR2] = dr_interception,
2872 [SVM_EXIT_READ_DR3] = dr_interception,
2873 [SVM_EXIT_READ_DR4] = dr_interception,
2874 [SVM_EXIT_READ_DR5] = dr_interception,
2875 [SVM_EXIT_READ_DR6] = dr_interception,
2876 [SVM_EXIT_READ_DR7] = dr_interception,
2877 [SVM_EXIT_WRITE_DR0] = dr_interception,
2878 [SVM_EXIT_WRITE_DR1] = dr_interception,
2879 [SVM_EXIT_WRITE_DR2] = dr_interception,
2880 [SVM_EXIT_WRITE_DR3] = dr_interception,
2881 [SVM_EXIT_WRITE_DR4] = dr_interception,
2882 [SVM_EXIT_WRITE_DR5] = dr_interception,
2883 [SVM_EXIT_WRITE_DR6] = dr_interception,
2884 [SVM_EXIT_WRITE_DR7] = dr_interception,
2885 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2886 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2887 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2888 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2889 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2890 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
2891 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
2892 [SVM_EXIT_INTR] = intr_interception,
2893 [SVM_EXIT_NMI] = nmi_interception,
2894 [SVM_EXIT_SMI] = nop_on_interception,
2895 [SVM_EXIT_INIT] = nop_on_interception,
2896 [SVM_EXIT_VINTR] = interrupt_window_interception,
2897 [SVM_EXIT_RDPMC] = rdpmc_interception,
2898 [SVM_EXIT_CPUID] = cpuid_interception,
2899 [SVM_EXIT_IRET] = iret_interception,
2900 [SVM_EXIT_INVD] = invd_interception,
2901 [SVM_EXIT_PAUSE] = pause_interception,
2902 [SVM_EXIT_HLT] = halt_interception,
2903 [SVM_EXIT_INVLPG] = invlpg_interception,
2904 [SVM_EXIT_INVLPGA] = invlpga_interception,
2905 [SVM_EXIT_IOIO] = io_interception,
2906 [SVM_EXIT_MSR] = msr_interception,
2907 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2908 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2909 [SVM_EXIT_VMRUN] = vmrun_interception,
2910 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2911 [SVM_EXIT_VMLOAD] = vmload_interception,
2912 [SVM_EXIT_VMSAVE] = vmsave_interception,
2913 [SVM_EXIT_STGI] = stgi_interception,
2914 [SVM_EXIT_CLGI] = clgi_interception,
2915 [SVM_EXIT_SKINIT] = skinit_interception,
2916 [SVM_EXIT_WBINVD] = wbinvd_interception,
2917 [SVM_EXIT_MONITOR] = monitor_interception,
2918 [SVM_EXIT_MWAIT] = mwait_interception,
2919 [SVM_EXIT_XSETBV] = xsetbv_interception,
2920 [SVM_EXIT_RDPRU] = rdpru_interception,
2921 [SVM_EXIT_INVPCID] = invpcid_interception,
2922 [SVM_EXIT_NPF] = npf_interception,
2923 [SVM_EXIT_RSM] = rsm_interception,
2924 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2925 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
2928 static void dump_vmcb(struct kvm_vcpu *vcpu)
2930 struct vcpu_svm *svm = to_svm(vcpu);
2931 struct vmcb_control_area *control = &svm->vmcb->control;
2932 struct vmcb_save_area *save = &svm->vmcb->save;
2934 if (!dump_invalid_vmcb) {
2935 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2939 pr_err("VMCB Control Area:\n");
2940 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2941 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
2942 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2943 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
2944 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
2945 pr_err("%-20s%08x %08x\n", "intercepts:",
2946 control->intercepts[INTERCEPT_WORD3],
2947 control->intercepts[INTERCEPT_WORD4]);
2948 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2949 pr_err("%-20s%d\n", "pause filter threshold:",
2950 control->pause_filter_thresh);
2951 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2952 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2953 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2954 pr_err("%-20s%d\n", "asid:", control->asid);
2955 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2956 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2957 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2958 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2959 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2960 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2961 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2962 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2963 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2964 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2965 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2966 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2967 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2968 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2969 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2970 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2971 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2972 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2973 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2974 pr_err("VMCB State Save Area:\n");
2975 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2977 save->es.selector, save->es.attrib,
2978 save->es.limit, save->es.base);
2979 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2981 save->cs.selector, save->cs.attrib,
2982 save->cs.limit, save->cs.base);
2983 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2985 save->ss.selector, save->ss.attrib,
2986 save->ss.limit, save->ss.base);
2987 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2989 save->ds.selector, save->ds.attrib,
2990 save->ds.limit, save->ds.base);
2991 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2993 save->fs.selector, save->fs.attrib,
2994 save->fs.limit, save->fs.base);
2995 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2997 save->gs.selector, save->gs.attrib,
2998 save->gs.limit, save->gs.base);
2999 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3001 save->gdtr.selector, save->gdtr.attrib,
3002 save->gdtr.limit, save->gdtr.base);
3003 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3005 save->ldtr.selector, save->ldtr.attrib,
3006 save->ldtr.limit, save->ldtr.base);
3007 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3009 save->idtr.selector, save->idtr.attrib,
3010 save->idtr.limit, save->idtr.base);
3011 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3013 save->tr.selector, save->tr.attrib,
3014 save->tr.limit, save->tr.base);
3015 pr_err("cpl: %d efer: %016llx\n",
3016 save->cpl, save->efer);
3017 pr_err("%-15s %016llx %-13s %016llx\n",
3018 "cr0:", save->cr0, "cr2:", save->cr2);
3019 pr_err("%-15s %016llx %-13s %016llx\n",
3020 "cr3:", save->cr3, "cr4:", save->cr4);
3021 pr_err("%-15s %016llx %-13s %016llx\n",
3022 "dr6:", save->dr6, "dr7:", save->dr7);
3023 pr_err("%-15s %016llx %-13s %016llx\n",
3024 "rip:", save->rip, "rflags:", save->rflags);
3025 pr_err("%-15s %016llx %-13s %016llx\n",
3026 "rsp:", save->rsp, "rax:", save->rax);
3027 pr_err("%-15s %016llx %-13s %016llx\n",
3028 "star:", save->star, "lstar:", save->lstar);
3029 pr_err("%-15s %016llx %-13s %016llx\n",
3030 "cstar:", save->cstar, "sfmask:", save->sfmask);
3031 pr_err("%-15s %016llx %-13s %016llx\n",
3032 "kernel_gs_base:", save->kernel_gs_base,
3033 "sysenter_cs:", save->sysenter_cs);
3034 pr_err("%-15s %016llx %-13s %016llx\n",
3035 "sysenter_esp:", save->sysenter_esp,
3036 "sysenter_eip:", save->sysenter_eip);
3037 pr_err("%-15s %016llx %-13s %016llx\n",
3038 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3039 pr_err("%-15s %016llx %-13s %016llx\n",
3040 "br_from:", save->br_from, "br_to:", save->br_to);
3041 pr_err("%-15s %016llx %-13s %016llx\n",
3042 "excp_from:", save->last_excp_from,
3043 "excp_to:", save->last_excp_to);
3046 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3047 u32 *intr_info, u32 *error_code)
3049 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3051 *info1 = control->exit_info_1;
3052 *info2 = control->exit_info_2;
3053 *intr_info = control->exit_int_info;
3054 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3055 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3056 *error_code = control->exit_int_info_err;
3061 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3063 struct vcpu_svm *svm = to_svm(vcpu);
3064 struct kvm_run *kvm_run = vcpu->run;
3065 u32 exit_code = svm->vmcb->control.exit_code;
3067 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3069 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3070 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3072 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3074 if (is_guest_mode(vcpu)) {
3077 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3079 vmexit = nested_svm_exit_special(svm);
3081 if (vmexit == NESTED_EXIT_CONTINUE)
3082 vmexit = nested_svm_exit_handled(svm);
3084 if (vmexit == NESTED_EXIT_DONE)
3088 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3089 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3090 kvm_run->fail_entry.hardware_entry_failure_reason
3091 = svm->vmcb->control.exit_code;
3092 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3097 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3098 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3099 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3100 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3101 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3103 __func__, svm->vmcb->control.exit_int_info,
3106 if (exit_fastpath != EXIT_FASTPATH_NONE)
3109 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3110 || !svm_exit_handlers[exit_code]) {
3111 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3113 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3114 vcpu->run->internal.suberror =
3115 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3116 vcpu->run->internal.ndata = 2;
3117 vcpu->run->internal.data[0] = exit_code;
3118 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3122 #ifdef CONFIG_RETPOLINE
3123 if (exit_code == SVM_EXIT_MSR)
3124 return msr_interception(svm);
3125 else if (exit_code == SVM_EXIT_VINTR)
3126 return interrupt_window_interception(svm);
3127 else if (exit_code == SVM_EXIT_INTR)
3128 return intr_interception(svm);
3129 else if (exit_code == SVM_EXIT_HLT)
3130 return halt_interception(svm);
3131 else if (exit_code == SVM_EXIT_NPF)
3132 return npf_interception(svm);
3134 return svm_exit_handlers[exit_code](svm);
3137 static void reload_tss(struct kvm_vcpu *vcpu)
3139 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3141 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3145 static void pre_svm_run(struct vcpu_svm *svm)
3147 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3149 if (sev_guest(svm->vcpu.kvm))
3150 return pre_sev_run(svm, svm->vcpu.cpu);
3152 /* FIXME: handle wraparound of asid_generation */
3153 if (svm->asid_generation != sd->asid_generation)
3157 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3159 struct vcpu_svm *svm = to_svm(vcpu);
3161 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3162 vcpu->arch.hflags |= HF_NMI_MASK;
3163 svm_set_intercept(svm, INTERCEPT_IRET);
3164 ++vcpu->stat.nmi_injections;
3167 static void svm_set_irq(struct kvm_vcpu *vcpu)
3169 struct vcpu_svm *svm = to_svm(vcpu);
3171 BUG_ON(!(gif_set(svm)));
3173 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3174 ++vcpu->stat.irq_injections;
3176 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3177 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3180 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3182 struct vcpu_svm *svm = to_svm(vcpu);
3184 if (nested_svm_virtualize_tpr(vcpu))
3187 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3193 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3196 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3198 struct vcpu_svm *svm = to_svm(vcpu);
3199 struct vmcb *vmcb = svm->vmcb;
3205 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3208 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3209 (svm->vcpu.arch.hflags & HF_NMI_MASK);
3214 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3216 struct vcpu_svm *svm = to_svm(vcpu);
3217 if (svm->nested.nested_run_pending)
3220 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3221 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3224 return !svm_nmi_blocked(vcpu);
3227 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3229 struct vcpu_svm *svm = to_svm(vcpu);
3231 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3234 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3236 struct vcpu_svm *svm = to_svm(vcpu);
3239 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3240 svm_set_intercept(svm, INTERCEPT_IRET);
3242 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3243 svm_clr_intercept(svm, INTERCEPT_IRET);
3247 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3249 struct vcpu_svm *svm = to_svm(vcpu);
3250 struct vmcb *vmcb = svm->vmcb;
3255 if (is_guest_mode(vcpu)) {
3256 /* As long as interrupts are being delivered... */
3257 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3258 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3259 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3262 /* ... vmexits aren't blocked by the interrupt shadow */
3263 if (nested_exit_on_intr(svm))
3266 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3270 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3273 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3275 struct vcpu_svm *svm = to_svm(vcpu);
3276 if (svm->nested.nested_run_pending)
3280 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3281 * e.g. if the IRQ arrived asynchronously after checking nested events.
3283 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3286 return !svm_interrupt_blocked(vcpu);
3289 static void enable_irq_window(struct kvm_vcpu *vcpu)
3291 struct vcpu_svm *svm = to_svm(vcpu);
3294 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3295 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3296 * get that intercept, this function will be called again though and
3297 * we'll get the vintr intercept. However, if the vGIF feature is
3298 * enabled, the STGI interception will not occur. Enable the irq
3299 * window under the assumption that the hardware will set the GIF.
3301 if (vgif_enabled(svm) || gif_set(svm)) {
3303 * IRQ window is not needed when AVIC is enabled,
3304 * unless we have pending ExtINT since it cannot be injected
3305 * via AVIC. In such case, we need to temporarily disable AVIC,
3306 * and fallback to injecting IRQ via V_IRQ.
3308 svm_toggle_avic_for_irq_window(vcpu, false);
3313 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3315 struct vcpu_svm *svm = to_svm(vcpu);
3317 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3319 return; /* IRET will cause a vm exit */
3321 if (!gif_set(svm)) {
3322 if (vgif_enabled(svm))
3323 svm_set_intercept(svm, INTERCEPT_STGI);
3324 return; /* STGI will cause a vm exit */
3328 * Something prevents NMI from been injected. Single step over possible
3329 * problem (IRET or exception injection or interrupt shadow)
3331 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3332 svm->nmi_singlestep = true;
3333 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3336 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3341 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3346 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3348 struct vcpu_svm *svm = to_svm(vcpu);
3351 * Flush only the current ASID even if the TLB flush was invoked via
3352 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3353 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3354 * unconditionally does a TLB flush on both nested VM-Enter and nested
3355 * VM-Exit (via kvm_mmu_reset_context()).
3357 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3358 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3360 svm->asid_generation--;
3363 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3365 struct vcpu_svm *svm = to_svm(vcpu);
3367 invlpga(gva, svm->vmcb->control.asid);
3370 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3374 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3376 struct vcpu_svm *svm = to_svm(vcpu);
3378 if (nested_svm_virtualize_tpr(vcpu))
3381 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3382 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3383 kvm_set_cr8(vcpu, cr8);
3387 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3389 struct vcpu_svm *svm = to_svm(vcpu);
3392 if (nested_svm_virtualize_tpr(vcpu) ||
3393 kvm_vcpu_apicv_active(vcpu))
3396 cr8 = kvm_get_cr8(vcpu);
3397 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3398 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3401 static void svm_complete_interrupts(struct vcpu_svm *svm)
3405 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3406 unsigned int3_injected = svm->int3_injected;
3408 svm->int3_injected = 0;
3411 * If we've made progress since setting HF_IRET_MASK, we've
3412 * executed an IRET and can allow NMI injection.
3414 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3415 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3416 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3417 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3420 svm->vcpu.arch.nmi_injected = false;
3421 kvm_clear_exception_queue(&svm->vcpu);
3422 kvm_clear_interrupt_queue(&svm->vcpu);
3424 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3427 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3429 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3430 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3433 case SVM_EXITINTINFO_TYPE_NMI:
3434 svm->vcpu.arch.nmi_injected = true;
3436 case SVM_EXITINTINFO_TYPE_EXEPT:
3438 * In case of software exceptions, do not reinject the vector,
3439 * but re-execute the instruction instead. Rewind RIP first
3440 * if we emulated INT3 before.
3442 if (kvm_exception_is_soft(vector)) {
3443 if (vector == BP_VECTOR && int3_injected &&
3444 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3445 kvm_rip_write(&svm->vcpu,
3446 kvm_rip_read(&svm->vcpu) -
3450 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3451 u32 err = svm->vmcb->control.exit_int_info_err;
3452 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3455 kvm_requeue_exception(&svm->vcpu, vector);
3457 case SVM_EXITINTINFO_TYPE_INTR:
3458 kvm_queue_interrupt(&svm->vcpu, vector, false);
3465 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3467 struct vcpu_svm *svm = to_svm(vcpu);
3468 struct vmcb_control_area *control = &svm->vmcb->control;
3470 control->exit_int_info = control->event_inj;
3471 control->exit_int_info_err = control->event_inj_err;
3472 control->event_inj = 0;
3473 svm_complete_interrupts(svm);
3476 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3478 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3479 to_svm(vcpu)->vmcb->control.exit_info_1)
3480 return handle_fastpath_set_msr_irqoff(vcpu);
3482 return EXIT_FASTPATH_NONE;
3485 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3487 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3488 struct vcpu_svm *svm)
3491 * VMENTER enables interrupts (host state), but the kernel state is
3492 * interrupts disabled when this is invoked. Also tell RCU about
3493 * it. This is the same logic as for exit_to_user_mode().
3495 * This ensures that e.g. latency analysis on the host observes
3496 * guest mode as interrupt enabled.
3498 * guest_enter_irqoff() informs context tracking about the
3499 * transition to guest mode and if enabled adjusts RCU state
3502 instrumentation_begin();
3503 trace_hardirqs_on_prepare();
3504 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3505 instrumentation_end();
3507 guest_enter_irqoff();
3508 lockdep_hardirqs_on(CALLER_ADDR0);
3510 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3512 #ifdef CONFIG_X86_64
3513 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3515 loadsegment(fs, svm->host.fs);
3516 #ifndef CONFIG_X86_32_LAZY_GS
3517 loadsegment(gs, svm->host.gs);
3522 * VMEXIT disables interrupts (host state), but tracing and lockdep
3523 * have them in state 'on' as recorded before entering guest mode.
3524 * Same as enter_from_user_mode().
3526 * guest_exit_irqoff() restores host context and reinstates RCU if
3527 * enabled and required.
3529 * This needs to be done before the below as native_read_msr()
3530 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3531 * into world and some more.
3533 lockdep_hardirqs_off(CALLER_ADDR0);
3534 guest_exit_irqoff();
3536 instrumentation_begin();
3537 trace_hardirqs_off_finish();
3538 instrumentation_end();
3541 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3543 struct vcpu_svm *svm = to_svm(vcpu);
3545 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3546 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3547 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3550 * Disable singlestep if we're injecting an interrupt/exception.
3551 * We don't want our modified rflags to be pushed on the stack where
3552 * we might not be able to easily reset them if we disabled NMI
3555 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3557 * Event injection happens before external interrupts cause a
3558 * vmexit and interrupts are disabled here, so smp_send_reschedule
3559 * is enough to force an immediate vmexit.
3561 disable_nmi_singlestep(svm);
3562 smp_send_reschedule(vcpu->cpu);
3567 sync_lapic_to_cr8(vcpu);
3569 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3572 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3575 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3576 svm_set_dr6(svm, vcpu->arch.dr6);
3578 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3581 kvm_load_guest_xsave_state(vcpu);
3583 kvm_wait_lapic_expire(vcpu);
3586 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3587 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3588 * is no need to worry about the conditional branch over the wrmsr
3589 * being speculatively taken.
3591 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3593 svm_vcpu_enter_exit(vcpu, svm);
3596 * We do not use IBRS in the kernel. If this vCPU has used the
3597 * SPEC_CTRL MSR it may have left it on; save the value and
3598 * turn it off. This is much more efficient than blindly adding
3599 * it to the atomic save/restore list. Especially as the former
3600 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3602 * For non-nested case:
3603 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3607 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3610 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3611 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3615 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3617 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3618 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3619 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3620 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3622 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3623 kvm_before_interrupt(&svm->vcpu);
3625 kvm_load_host_xsave_state(vcpu);
3628 /* Any pending NMI will happen here */
3630 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3631 kvm_after_interrupt(&svm->vcpu);
3633 sync_cr8_to_lapic(vcpu);
3636 if (is_guest_mode(&svm->vcpu)) {
3637 sync_nested_vmcb_control(svm);
3638 svm->nested.nested_run_pending = 0;
3641 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3642 vmcb_mark_all_clean(svm->vmcb);
3644 /* if exit due to PF check for async PF */
3645 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3646 svm->vcpu.arch.apf.host_apf_flags =
3647 kvm_read_and_reset_apf_flags();
3650 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3651 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3655 * We need to handle MC intercepts here before the vcpu has a chance to
3656 * change the physical cpu
3658 if (unlikely(svm->vmcb->control.exit_code ==
3659 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3660 svm_handle_mce(svm);
3662 svm_complete_interrupts(svm);
3664 if (is_guest_mode(vcpu))
3665 return EXIT_FASTPATH_NONE;
3667 return svm_exit_handlers_fastpath(vcpu);
3670 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3673 struct vcpu_svm *svm = to_svm(vcpu);
3676 cr3 = __sme_set(root);
3678 svm->vmcb->control.nested_cr3 = cr3;
3679 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3681 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3682 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3684 cr3 = vcpu->arch.cr3;
3687 svm->vmcb->save.cr3 = cr3;
3688 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3691 static int is_disabled(void)
3695 rdmsrl(MSR_VM_CR, vm_cr);
3696 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3703 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3706 * Patch in the VMMCALL instruction:
3708 hypercall[0] = 0x0f;
3709 hypercall[1] = 0x01;
3710 hypercall[2] = 0xd9;
3713 static int __init svm_check_processor_compat(void)
3718 static bool svm_cpu_has_accelerated_tpr(void)
3723 static bool svm_has_emulated_msr(u32 index)
3726 case MSR_IA32_MCG_EXT_CTL:
3727 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3736 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3741 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3743 struct vcpu_svm *svm = to_svm(vcpu);
3745 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3746 boot_cpu_has(X86_FEATURE_XSAVE) &&
3747 boot_cpu_has(X86_FEATURE_XSAVES);
3749 /* Update nrips enabled cache */
3750 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3751 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3753 /* Check again if INVPCID interception if required */
3754 svm_check_invpcid(svm);
3756 if (!kvm_vcpu_apicv_active(vcpu))
3760 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3761 * is exposed to the guest, disable AVIC.
3763 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3764 kvm_request_apicv_update(vcpu->kvm, false,
3765 APICV_INHIBIT_REASON_X2APIC);
3768 * Currently, AVIC does not work with nested virtualization.
3769 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3771 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3772 kvm_request_apicv_update(vcpu->kvm, false,
3773 APICV_INHIBIT_REASON_NESTED);
3776 static bool svm_has_wbinvd_exit(void)
3781 #define PRE_EX(exit) { .exit_code = (exit), \
3782 .stage = X86_ICPT_PRE_EXCEPT, }
3783 #define POST_EX(exit) { .exit_code = (exit), \
3784 .stage = X86_ICPT_POST_EXCEPT, }
3785 #define POST_MEM(exit) { .exit_code = (exit), \
3786 .stage = X86_ICPT_POST_MEMACCESS, }
3788 static const struct __x86_intercept {
3790 enum x86_intercept_stage stage;
3791 } x86_intercept_map[] = {
3792 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3793 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3794 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3795 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3796 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3797 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3798 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3799 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3800 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3801 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3802 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3803 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3804 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3805 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3806 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
3807 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3808 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3809 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3810 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3811 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3812 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3813 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3814 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
3815 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3816 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3817 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
3818 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3819 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3820 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3821 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3822 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3823 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3824 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3825 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3826 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
3827 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3828 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3829 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3830 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3831 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3832 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3833 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
3834 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3835 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3836 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3837 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
3838 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
3845 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3846 struct x86_instruction_info *info,
3847 enum x86_intercept_stage stage,
3848 struct x86_exception *exception)
3850 struct vcpu_svm *svm = to_svm(vcpu);
3851 int vmexit, ret = X86EMUL_CONTINUE;
3852 struct __x86_intercept icpt_info;
3853 struct vmcb *vmcb = svm->vmcb;
3855 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3858 icpt_info = x86_intercept_map[info->intercept];
3860 if (stage != icpt_info.stage)
3863 switch (icpt_info.exit_code) {
3864 case SVM_EXIT_READ_CR0:
3865 if (info->intercept == x86_intercept_cr_read)
3866 icpt_info.exit_code += info->modrm_reg;
3868 case SVM_EXIT_WRITE_CR0: {
3869 unsigned long cr0, val;
3871 if (info->intercept == x86_intercept_cr_write)
3872 icpt_info.exit_code += info->modrm_reg;
3874 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3875 info->intercept == x86_intercept_clts)
3878 if (!(vmcb_is_intercept(&svm->nested.ctl,
3879 INTERCEPT_SELECTIVE_CR0)))
3882 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3883 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3885 if (info->intercept == x86_intercept_lmsw) {
3888 /* lmsw can't clear PE - catch this here */
3889 if (cr0 & X86_CR0_PE)
3894 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3898 case SVM_EXIT_READ_DR0:
3899 case SVM_EXIT_WRITE_DR0:
3900 icpt_info.exit_code += info->modrm_reg;
3903 if (info->intercept == x86_intercept_wrmsr)
3904 vmcb->control.exit_info_1 = 1;
3906 vmcb->control.exit_info_1 = 0;
3908 case SVM_EXIT_PAUSE:
3910 * We get this for NOP only, but pause
3911 * is rep not, check this here
3913 if (info->rep_prefix != REPE_PREFIX)
3916 case SVM_EXIT_IOIO: {
3920 if (info->intercept == x86_intercept_in ||
3921 info->intercept == x86_intercept_ins) {
3922 exit_info = ((info->src_val & 0xffff) << 16) |
3924 bytes = info->dst_bytes;
3926 exit_info = (info->dst_val & 0xffff) << 16;
3927 bytes = info->src_bytes;
3930 if (info->intercept == x86_intercept_outs ||
3931 info->intercept == x86_intercept_ins)
3932 exit_info |= SVM_IOIO_STR_MASK;
3934 if (info->rep_prefix)
3935 exit_info |= SVM_IOIO_REP_MASK;
3937 bytes = min(bytes, 4u);
3939 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3941 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3943 vmcb->control.exit_info_1 = exit_info;
3944 vmcb->control.exit_info_2 = info->next_rip;
3952 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3953 if (static_cpu_has(X86_FEATURE_NRIPS))
3954 vmcb->control.next_rip = info->next_rip;
3955 vmcb->control.exit_code = icpt_info.exit_code;
3956 vmexit = nested_svm_exit_handled(svm);
3958 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3965 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3969 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3971 if (!kvm_pause_in_guest(vcpu->kvm))
3972 shrink_ple_window(vcpu);
3975 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3977 /* [63:9] are reserved. */
3978 vcpu->arch.mcg_cap &= 0x1ff;
3981 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3983 struct vcpu_svm *svm = to_svm(vcpu);
3985 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3989 return is_smm(vcpu);
3992 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3994 struct vcpu_svm *svm = to_svm(vcpu);
3995 if (svm->nested.nested_run_pending)
3998 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3999 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4002 return !svm_smi_blocked(vcpu);
4005 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4007 struct vcpu_svm *svm = to_svm(vcpu);
4010 if (is_guest_mode(vcpu)) {
4011 /* FED8h - SVM Guest */
4012 put_smstate(u64, smstate, 0x7ed8, 1);
4013 /* FEE0h - SVM Guest VMCB Physical Address */
4014 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4016 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4017 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4018 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4020 ret = nested_svm_vmexit(svm);
4027 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4029 struct vcpu_svm *svm = to_svm(vcpu);
4030 struct kvm_host_map map;
4033 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4034 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4035 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4036 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4039 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4042 if (!(saved_efer & EFER_SVME))
4045 if (kvm_vcpu_map(&svm->vcpu,
4046 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4049 if (svm_allocate_nested(svm))
4052 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4053 kvm_vcpu_unmap(&svm->vcpu, &map, true);
4060 static void enable_smi_window(struct kvm_vcpu *vcpu)
4062 struct vcpu_svm *svm = to_svm(vcpu);
4064 if (!gif_set(svm)) {
4065 if (vgif_enabled(svm))
4066 svm_set_intercept(svm, INTERCEPT_STGI);
4067 /* STGI will cause a vm exit */
4069 /* We must be in SMM; RSM will cause a vmexit anyway. */
4073 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4075 bool smep, smap, is_user;
4079 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4082 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4083 * possible that CPU microcode implementing DecodeAssist will fail
4084 * to read bytes of instruction which caused #NPF. In this case,
4085 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4086 * return 0 instead of the correct guest instruction bytes.
4088 * This happens because CPU microcode reading instruction bytes
4089 * uses a special opcode which attempts to read data using CPL=0
4090 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4091 * fault, it gives up and returns no instruction bytes.
4094 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4095 * returned 0 in GuestIntrBytes field of the VMCB.
4096 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4097 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4098 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4099 * a SMEP fault instead of #NPF).
4100 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4101 * As most guests enable SMAP if they have also enabled SMEP, use above
4102 * logic in order to attempt minimize false-positive of detecting errata
4103 * while still preserving all cases semantic correctness.
4106 * To determine what instruction the guest was executing, the hypervisor
4107 * will have to decode the instruction at the instruction pointer.
4109 * In non SEV guest, hypervisor will be able to read the guest
4110 * memory to decode the instruction pointer when insn_len is zero
4111 * so we return true to indicate that decoding is possible.
4113 * But in the SEV guest, the guest memory is encrypted with the
4114 * guest specific key and hypervisor will not be able to decode the
4115 * instruction pointer so we will not able to workaround it. Lets
4116 * print the error and request to kill the guest.
4118 if (likely(!insn || insn_len))
4122 * If RIP is invalid, go ahead with emulation which will cause an
4123 * internal error exit.
4125 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4128 cr4 = kvm_read_cr4(vcpu);
4129 smep = cr4 & X86_CR4_SMEP;
4130 smap = cr4 & X86_CR4_SMAP;
4131 is_user = svm_get_cpl(vcpu) == 3;
4132 if (smap && (!smep || is_user)) {
4133 if (!sev_guest(vcpu->kvm))
4136 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4137 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4143 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4145 struct vcpu_svm *svm = to_svm(vcpu);
4148 * TODO: Last condition latch INIT signals on vCPU when
4149 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4150 * To properly emulate the INIT intercept,
4151 * svm_check_nested_events() should call nested_svm_vmexit()
4152 * if an INIT signal is pending.
4154 return !gif_set(svm) ||
4155 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4158 static void svm_vm_destroy(struct kvm *kvm)
4160 avic_vm_destroy(kvm);
4161 sev_vm_destroy(kvm);
4164 static int svm_vm_init(struct kvm *kvm)
4166 if (!pause_filter_count || !pause_filter_thresh)
4167 kvm->arch.pause_in_guest = true;
4170 int ret = avic_vm_init(kvm);
4175 kvm_apicv_init(kvm, avic);
4179 static struct kvm_x86_ops svm_x86_ops __initdata = {
4180 .hardware_unsetup = svm_hardware_teardown,
4181 .hardware_enable = svm_hardware_enable,
4182 .hardware_disable = svm_hardware_disable,
4183 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4184 .has_emulated_msr = svm_has_emulated_msr,
4186 .vcpu_create = svm_create_vcpu,
4187 .vcpu_free = svm_free_vcpu,
4188 .vcpu_reset = svm_vcpu_reset,
4190 .vm_size = sizeof(struct kvm_svm),
4191 .vm_init = svm_vm_init,
4192 .vm_destroy = svm_vm_destroy,
4194 .prepare_guest_switch = svm_prepare_guest_switch,
4195 .vcpu_load = svm_vcpu_load,
4196 .vcpu_put = svm_vcpu_put,
4197 .vcpu_blocking = svm_vcpu_blocking,
4198 .vcpu_unblocking = svm_vcpu_unblocking,
4200 .update_exception_bitmap = update_exception_bitmap,
4201 .get_msr_feature = svm_get_msr_feature,
4202 .get_msr = svm_get_msr,
4203 .set_msr = svm_set_msr,
4204 .get_segment_base = svm_get_segment_base,
4205 .get_segment = svm_get_segment,
4206 .set_segment = svm_set_segment,
4207 .get_cpl = svm_get_cpl,
4208 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4209 .set_cr0 = svm_set_cr0,
4210 .set_cr4 = svm_set_cr4,
4211 .set_efer = svm_set_efer,
4212 .get_idt = svm_get_idt,
4213 .set_idt = svm_set_idt,
4214 .get_gdt = svm_get_gdt,
4215 .set_gdt = svm_set_gdt,
4216 .set_dr7 = svm_set_dr7,
4217 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4218 .cache_reg = svm_cache_reg,
4219 .get_rflags = svm_get_rflags,
4220 .set_rflags = svm_set_rflags,
4222 .tlb_flush_all = svm_flush_tlb,
4223 .tlb_flush_current = svm_flush_tlb,
4224 .tlb_flush_gva = svm_flush_tlb_gva,
4225 .tlb_flush_guest = svm_flush_tlb,
4227 .run = svm_vcpu_run,
4228 .handle_exit = handle_exit,
4229 .skip_emulated_instruction = skip_emulated_instruction,
4230 .update_emulated_instruction = NULL,
4231 .set_interrupt_shadow = svm_set_interrupt_shadow,
4232 .get_interrupt_shadow = svm_get_interrupt_shadow,
4233 .patch_hypercall = svm_patch_hypercall,
4234 .set_irq = svm_set_irq,
4235 .set_nmi = svm_inject_nmi,
4236 .queue_exception = svm_queue_exception,
4237 .cancel_injection = svm_cancel_injection,
4238 .interrupt_allowed = svm_interrupt_allowed,
4239 .nmi_allowed = svm_nmi_allowed,
4240 .get_nmi_mask = svm_get_nmi_mask,
4241 .set_nmi_mask = svm_set_nmi_mask,
4242 .enable_nmi_window = enable_nmi_window,
4243 .enable_irq_window = enable_irq_window,
4244 .update_cr8_intercept = update_cr8_intercept,
4245 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4246 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4247 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4248 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4249 .load_eoi_exitmap = svm_load_eoi_exitmap,
4250 .hwapic_irr_update = svm_hwapic_irr_update,
4251 .hwapic_isr_update = svm_hwapic_isr_update,
4252 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4253 .apicv_post_state_restore = avic_post_state_restore,
4255 .set_tss_addr = svm_set_tss_addr,
4256 .set_identity_map_addr = svm_set_identity_map_addr,
4257 .get_mt_mask = svm_get_mt_mask,
4259 .get_exit_info = svm_get_exit_info,
4261 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4263 .has_wbinvd_exit = svm_has_wbinvd_exit,
4265 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4267 .load_mmu_pgd = svm_load_mmu_pgd,
4269 .check_intercept = svm_check_intercept,
4270 .handle_exit_irqoff = svm_handle_exit_irqoff,
4272 .request_immediate_exit = __kvm_request_immediate_exit,
4274 .sched_in = svm_sched_in,
4276 .pmu_ops = &amd_pmu_ops,
4277 .nested_ops = &svm_nested_ops,
4279 .deliver_posted_interrupt = svm_deliver_avic_intr,
4280 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4281 .update_pi_irte = svm_update_pi_irte,
4282 .setup_mce = svm_setup_mce,
4284 .smi_allowed = svm_smi_allowed,
4285 .pre_enter_smm = svm_pre_enter_smm,
4286 .pre_leave_smm = svm_pre_leave_smm,
4287 .enable_smi_window = enable_smi_window,
4289 .mem_enc_op = svm_mem_enc_op,
4290 .mem_enc_reg_region = svm_register_enc_region,
4291 .mem_enc_unreg_region = svm_unregister_enc_region,
4293 .can_emulate_instruction = svm_can_emulate_instruction,
4295 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4297 .msr_filter_changed = svm_msr_filter_changed,
4300 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4301 .cpu_has_kvm_support = has_svm,
4302 .disabled_by_bios = is_disabled,
4303 .hardware_setup = svm_hardware_setup,
4304 .check_processor_compatibility = svm_check_processor_compat,
4306 .runtime_ops = &svm_x86_ops,
4309 static int __init svm_init(void)
4311 __unused_size_checks();
4313 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4314 __alignof__(struct vcpu_svm), THIS_MODULE);
4317 static void __exit svm_exit(void)
4322 module_init(svm_init)
4323 module_exit(svm_exit)