1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
28 #include <linux/cc_platform.h>
31 #include <asm/perf_event.h>
32 #include <asm/tlbflush.h>
34 #include <asm/debugreg.h>
35 #include <asm/kvm_para.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
39 #include <asm/traps.h>
40 #include <asm/fpu/api.h>
42 #include <asm/virtext.h>
48 #include "kvm_onhyperv.h"
49 #include "svm_onhyperv.h"
51 MODULE_AUTHOR("Qumranet");
52 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id svm_cpu_id[] = {
56 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
59 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62 #define SEG_TYPE_LDT 2
63 #define SEG_TYPE_BUSY_TSS16 3
65 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
67 static bool erratum_383_found __read_mostly;
69 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
72 * Set osvw_len to higher value when updated Revision Guides
73 * are published and we know what the new status bits are
75 static uint64_t osvw_len = 4, osvw_status;
77 static DEFINE_PER_CPU(u64, current_tsc_ratio);
79 static const struct svm_direct_access_msrs {
80 u32 index; /* Index of the MSR */
81 bool always; /* True if intercept is initially cleared */
82 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
83 { .index = MSR_STAR, .always = true },
84 { .index = MSR_IA32_SYSENTER_CS, .always = true },
85 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
86 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
88 { .index = MSR_GS_BASE, .always = true },
89 { .index = MSR_FS_BASE, .always = true },
90 { .index = MSR_KERNEL_GS_BASE, .always = true },
91 { .index = MSR_LSTAR, .always = true },
92 { .index = MSR_CSTAR, .always = true },
93 { .index = MSR_SYSCALL_MASK, .always = true },
95 { .index = MSR_IA32_SPEC_CTRL, .always = false },
96 { .index = MSR_IA32_PRED_CMD, .always = false },
97 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
98 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
99 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
100 { .index = MSR_IA32_LASTINTTOIP, .always = false },
101 { .index = MSR_EFER, .always = false },
102 { .index = MSR_IA32_CR_PAT, .always = false },
103 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
104 { .index = MSR_INVALID, .always = false },
108 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
109 * pause_filter_count: On processors that support Pause filtering(indicated
110 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
111 * count value. On VMRUN this value is loaded into an internal counter.
112 * Each time a pause instruction is executed, this counter is decremented
113 * until it reaches zero at which time a #VMEXIT is generated if pause
114 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
115 * Intercept Filtering for more details.
116 * This also indicate if ple logic enabled.
118 * pause_filter_thresh: In addition, some processor families support advanced
119 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
120 * the amount of time a guest is allowed to execute in a pause loop.
121 * In this mode, a 16-bit pause filter threshold field is added in the
122 * VMCB. The threshold value is a cycle count that is used to reset the
123 * pause counter. As with simple pause filtering, VMRUN loads the pause
124 * count value from VMCB into an internal counter. Then, on each pause
125 * instruction the hardware checks the elapsed number of cycles since
126 * the most recent pause instruction against the pause filter threshold.
127 * If the elapsed cycle count is greater than the pause filter threshold,
128 * then the internal pause count is reloaded from the VMCB and execution
129 * continues. If the elapsed cycle count is less than the pause filter
130 * threshold, then the internal pause count is decremented. If the count
131 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
132 * triggered. If advanced pause filtering is supported and pause filter
133 * threshold field is set to zero, the filter will operate in the simpler,
137 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
138 module_param(pause_filter_thresh, ushort, 0444);
140 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
141 module_param(pause_filter_count, ushort, 0444);
143 /* Default doubles per-vcpu window every exit. */
144 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
145 module_param(pause_filter_count_grow, ushort, 0444);
147 /* Default resets per-vcpu window every exit to pause_filter_count. */
148 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
149 module_param(pause_filter_count_shrink, ushort, 0444);
151 /* Default is to compute the maximum so we can never overflow. */
152 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
153 module_param(pause_filter_count_max, ushort, 0444);
156 * Use nested page tables by default. Note, NPT may get forced off by
157 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
159 bool npt_enabled = true;
160 module_param_named(npt, npt_enabled, bool, 0444);
162 /* allow nested virtualization in KVM/SVM */
163 static int nested = true;
164 module_param(nested, int, S_IRUGO);
166 /* enable/disable Next RIP Save */
167 static int nrips = true;
168 module_param(nrips, int, 0444);
170 /* enable/disable Virtual VMLOAD VMSAVE */
171 static int vls = true;
172 module_param(vls, int, 0444);
174 /* enable/disable Virtual GIF */
175 static int vgif = true;
176 module_param(vgif, int, 0444);
178 /* enable/disable LBR virtualization */
179 static int lbrv = true;
180 module_param(lbrv, int, 0444);
182 static int tsc_scaling = true;
183 module_param(tsc_scaling, int, 0444);
186 * enable / disable AVIC. Because the defaults differ for APICv
187 * support between VMX and SVM we cannot use module_param_named.
190 module_param(avic, bool, 0444);
192 bool __read_mostly dump_invalid_vmcb;
193 module_param(dump_invalid_vmcb, bool, 0644);
196 bool intercept_smi = true;
197 module_param(intercept_smi, bool, 0444);
200 static bool svm_gp_erratum_intercept = true;
202 static u8 rsm_ins_bytes[] = "\x0f\xaa";
204 static unsigned long iopm_base;
206 struct kvm_ldttss_desc {
209 unsigned base1:8, type:5, dpl:2, p:1;
210 unsigned limit1:4, zero0:3, g:1, base2:8;
213 } __attribute__((packed));
215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
218 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
219 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
221 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
222 * defer the restoration of TSC_AUX until the CPU returns to userspace.
224 static int tsc_aux_uret_slot __read_mostly = -1;
226 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
228 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
229 #define MSRS_RANGE_SIZE 2048
230 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
232 u32 svm_msrpm_offset(u32 msr)
237 for (i = 0; i < NUM_MSR_MAPS; i++) {
238 if (msr < msrpm_ranges[i] ||
239 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
242 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
243 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
245 /* Now we have the u8 offset - but need the u32 offset */
249 /* MSR not in any range */
253 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
255 static int get_npt_level(void)
258 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
260 return PT32E_ROOT_LEVEL;
264 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
266 struct vcpu_svm *svm = to_svm(vcpu);
267 u64 old_efer = vcpu->arch.efer;
268 vcpu->arch.efer = efer;
271 /* Shadow paging assumes NX to be available. */
274 if (!(efer & EFER_LMA))
278 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(vcpu);
281 svm_set_gif(svm, true);
282 /* #GP intercept is still needed for vmware backdoor */
283 if (!enable_vmware_backdoor)
284 clr_exception_intercept(svm, GP_VECTOR);
287 * Free the nested guest state, unless we are in SMM.
288 * In this case we will return to the nested guest
289 * as soon as we leave SMM.
292 svm_free_nested(svm);
295 int ret = svm_allocate_nested(svm);
298 vcpu->arch.efer = old_efer;
303 * Never intercept #GP for SEV guests, KVM can't
304 * decrypt guest memory to workaround the erratum.
306 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
307 set_exception_intercept(svm, GP_VECTOR);
311 svm->vmcb->save.efer = efer | EFER_SVME;
312 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
316 static int is_external_interrupt(u32 info)
318 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
319 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
322 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
324 struct vcpu_svm *svm = to_svm(vcpu);
327 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
328 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
332 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
334 struct vcpu_svm *svm = to_svm(vcpu);
337 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
339 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
343 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
345 struct vcpu_svm *svm = to_svm(vcpu);
348 * SEV-ES does not expose the next RIP. The RIP update is controlled by
349 * the type of exit and the #VC handler in the guest.
351 if (sev_es_guest(vcpu->kvm))
354 if (nrips && svm->vmcb->control.next_rip != 0) {
355 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
356 svm->next_rip = svm->vmcb->control.next_rip;
359 if (!svm->next_rip) {
360 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
363 kvm_rip_write(vcpu, svm->next_rip);
367 svm_set_interrupt_shadow(vcpu, 0);
372 static void svm_queue_exception(struct kvm_vcpu *vcpu)
374 struct vcpu_svm *svm = to_svm(vcpu);
375 unsigned nr = vcpu->arch.exception.nr;
376 bool has_error_code = vcpu->arch.exception.has_error_code;
377 u32 error_code = vcpu->arch.exception.error_code;
379 kvm_deliver_exception_payload(vcpu);
381 if (nr == BP_VECTOR && !nrips) {
382 unsigned long rip, old_rip = kvm_rip_read(vcpu);
385 * For guest debugging where we have to reinject #BP if some
386 * INT3 is guest-owned:
387 * Emulate nRIP by moving RIP forward. Will fail if injection
388 * raises a fault that is not intercepted. Still better than
389 * failing in all cases.
391 (void)svm_skip_emulated_instruction(vcpu);
392 rip = kvm_rip_read(vcpu);
393 svm->int3_rip = rip + svm->vmcb->save.cs.base;
394 svm->int3_injected = rip - old_rip;
397 svm->vmcb->control.event_inj = nr
399 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
400 | SVM_EVTINJ_TYPE_EXEPT;
401 svm->vmcb->control.event_inj_err = error_code;
404 static void svm_init_erratum_383(void)
410 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
413 /* Use _safe variants to not break nested virtualization */
414 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
420 low = lower_32_bits(val);
421 high = upper_32_bits(val);
423 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
425 erratum_383_found = true;
428 static void svm_init_osvw(struct kvm_vcpu *vcpu)
431 * Guests should see errata 400 and 415 as fixed (assuming that
432 * HLT and IO instructions are intercepted).
434 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
435 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
438 * By increasing VCPU's osvw.length to 3 we are telling the guest that
439 * all osvw.status bits inside that length, including bit 0 (which is
440 * reserved for erratum 298), are valid. However, if host processor's
441 * osvw_len is 0 then osvw_status[0] carries no information. We need to
442 * be conservative here and therefore we tell the guest that erratum 298
443 * is present (because we really don't know).
445 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
446 vcpu->arch.osvw.status |= 1;
449 static int has_svm(void)
453 if (!cpu_has_svm(&msg)) {
454 printk(KERN_INFO "has_svm: %s\n", msg);
458 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
459 pr_info("KVM is unsupported when running as an SEV guest\n");
466 static void svm_hardware_disable(void)
468 /* Make sure we clean up behind us */
470 wrmsrl(MSR_AMD64_TSC_RATIO, SVM_TSC_RATIO_DEFAULT);
474 amd_pmu_disable_virt();
477 static int svm_hardware_enable(void)
480 struct svm_cpu_data *sd;
482 struct desc_struct *gdt;
483 int me = raw_smp_processor_id();
485 rdmsrl(MSR_EFER, efer);
486 if (efer & EFER_SVME)
490 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
493 sd = per_cpu(svm_data, me);
495 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
499 sd->asid_generation = 1;
500 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
501 sd->next_asid = sd->max_asid + 1;
502 sd->min_asid = max_sev_asid + 1;
504 gdt = get_current_gdt_rw();
505 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
507 wrmsrl(MSR_EFER, efer | EFER_SVME);
509 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
511 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
513 * Set the default value, even if we don't use TSC scaling
514 * to avoid having stale value in the msr
516 wrmsrl(MSR_AMD64_TSC_RATIO, SVM_TSC_RATIO_DEFAULT);
517 __this_cpu_write(current_tsc_ratio, SVM_TSC_RATIO_DEFAULT);
524 * Note that it is possible to have a system with mixed processor
525 * revisions and therefore different OSVW bits. If bits are not the same
526 * on different processors then choose the worst case (i.e. if erratum
527 * is present on one processor and not on another then assume that the
528 * erratum is present everywhere).
530 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
531 uint64_t len, status = 0;
534 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
536 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
540 osvw_status = osvw_len = 0;
544 osvw_status |= status;
545 osvw_status &= (1ULL << osvw_len) - 1;
548 osvw_status = osvw_len = 0;
550 svm_init_erratum_383();
552 amd_pmu_enable_virt();
557 static void svm_cpu_uninit(int cpu)
559 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
564 per_cpu(svm_data, cpu) = NULL;
565 kfree(sd->sev_vmcbs);
566 __free_page(sd->save_area);
570 static int svm_cpu_init(int cpu)
572 struct svm_cpu_data *sd;
575 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
579 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
583 ret = sev_cpu_init(sd);
587 per_cpu(svm_data, cpu) = sd;
592 __free_page(sd->save_area);
599 static int direct_access_msr_slot(u32 msr)
603 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
604 if (direct_access_msrs[i].index == msr)
610 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
613 struct vcpu_svm *svm = to_svm(vcpu);
614 int slot = direct_access_msr_slot(msr);
619 /* Set the shadow bitmaps to the desired intercept states */
621 set_bit(slot, svm->shadow_msr_intercept.read);
623 clear_bit(slot, svm->shadow_msr_intercept.read);
626 set_bit(slot, svm->shadow_msr_intercept.write);
628 clear_bit(slot, svm->shadow_msr_intercept.write);
631 static bool valid_msr_intercept(u32 index)
633 return direct_access_msr_slot(index) != -ENOENT;
636 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
643 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
646 offset = svm_msrpm_offset(msr);
647 bit_write = 2 * (msr & 0x0f) + 1;
650 BUG_ON(offset == MSR_INVALID);
652 return !!test_bit(bit_write, &tmp);
655 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
656 u32 msr, int read, int write)
658 struct vcpu_svm *svm = to_svm(vcpu);
659 u8 bit_read, bit_write;
664 * If this warning triggers extend the direct_access_msrs list at the
665 * beginning of the file
667 WARN_ON(!valid_msr_intercept(msr));
669 /* Enforce non allowed MSRs to trap */
670 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
673 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
676 offset = svm_msrpm_offset(msr);
677 bit_read = 2 * (msr & 0x0f);
678 bit_write = 2 * (msr & 0x0f) + 1;
681 BUG_ON(offset == MSR_INVALID);
683 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
684 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
688 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
689 svm->nested.force_msr_bitmap_recalc = true;
692 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
695 set_shadow_msr_intercept(vcpu, msr, read, write);
696 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
699 u32 *svm_vcpu_alloc_msrpm(void)
701 unsigned int order = get_order(MSRPM_SIZE);
702 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
708 msrpm = page_address(pages);
709 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
714 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
718 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
719 if (!direct_access_msrs[i].always)
721 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
726 void svm_vcpu_free_msrpm(u32 *msrpm)
728 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
731 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
733 struct vcpu_svm *svm = to_svm(vcpu);
737 * Set intercept permissions for all direct access MSRs again. They
738 * will automatically get filtered through the MSR filter, so we are
739 * back in sync after this.
741 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
742 u32 msr = direct_access_msrs[i].index;
743 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
744 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
746 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
750 static void add_msr_offset(u32 offset)
754 for (i = 0; i < MSRPM_OFFSETS; ++i) {
756 /* Offset already in list? */
757 if (msrpm_offsets[i] == offset)
760 /* Slot used by another offset? */
761 if (msrpm_offsets[i] != MSR_INVALID)
764 /* Add offset to list */
765 msrpm_offsets[i] = offset;
771 * If this BUG triggers the msrpm_offsets table has an overflow. Just
772 * increase MSRPM_OFFSETS in this case.
777 static void init_msrpm_offsets(void)
781 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
783 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
786 offset = svm_msrpm_offset(direct_access_msrs[i].index);
787 BUG_ON(offset == MSR_INVALID);
789 add_msr_offset(offset);
793 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
795 struct vcpu_svm *svm = to_svm(vcpu);
797 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
798 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
799 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
800 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
801 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
804 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
806 struct vcpu_svm *svm = to_svm(vcpu);
808 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
809 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
810 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
811 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
812 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
815 void disable_nmi_singlestep(struct vcpu_svm *svm)
817 svm->nmi_singlestep = false;
819 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
820 /* Clear our flags if they were not set by the guest */
821 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
822 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
823 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
824 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
828 static void grow_ple_window(struct kvm_vcpu *vcpu)
830 struct vcpu_svm *svm = to_svm(vcpu);
831 struct vmcb_control_area *control = &svm->vmcb->control;
832 int old = control->pause_filter_count;
834 control->pause_filter_count = __grow_ple_window(old,
836 pause_filter_count_grow,
837 pause_filter_count_max);
839 if (control->pause_filter_count != old) {
840 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
841 trace_kvm_ple_window_update(vcpu->vcpu_id,
842 control->pause_filter_count, old);
846 static void shrink_ple_window(struct kvm_vcpu *vcpu)
848 struct vcpu_svm *svm = to_svm(vcpu);
849 struct vmcb_control_area *control = &svm->vmcb->control;
850 int old = control->pause_filter_count;
852 control->pause_filter_count =
853 __shrink_ple_window(old,
855 pause_filter_count_shrink,
857 if (control->pause_filter_count != old) {
858 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
859 trace_kvm_ple_window_update(vcpu->vcpu_id,
860 control->pause_filter_count, old);
864 static void svm_hardware_unsetup(void)
868 sev_hardware_unsetup();
870 for_each_possible_cpu(cpu)
873 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
874 get_order(IOPM_SIZE));
878 static void init_seg(struct vmcb_seg *seg)
881 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
882 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
887 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
890 seg->attrib = SVM_SELECTOR_P_MASK | type;
895 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
897 struct vcpu_svm *svm = to_svm(vcpu);
899 return svm->nested.ctl.tsc_offset;
902 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
904 struct vcpu_svm *svm = to_svm(vcpu);
906 return svm->tsc_ratio_msr;
909 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
911 struct vcpu_svm *svm = to_svm(vcpu);
913 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
914 svm->vmcb->control.tsc_offset = offset;
915 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
918 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
920 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
923 /* Evaluate instruction intercepts that depend on guest CPUID features. */
924 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
925 struct vcpu_svm *svm)
928 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
929 * roots, or if INVPCID is disabled in the guest to inject #UD.
931 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
933 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
934 svm_set_intercept(svm, INTERCEPT_INVPCID);
936 svm_clr_intercept(svm, INTERCEPT_INVPCID);
939 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
940 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
941 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
943 svm_set_intercept(svm, INTERCEPT_RDTSCP);
947 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
949 struct vcpu_svm *svm = to_svm(vcpu);
951 if (guest_cpuid_is_intel(vcpu)) {
953 * We must intercept SYSENTER_EIP and SYSENTER_ESP
954 * accesses because the processor only stores 32 bits.
955 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
957 svm_set_intercept(svm, INTERCEPT_VMLOAD);
958 svm_set_intercept(svm, INTERCEPT_VMSAVE);
959 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
961 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
962 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
965 * If hardware supports Virtual VMLOAD VMSAVE then enable it
966 * in VMCB and clear intercepts to avoid #VMEXIT.
969 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
970 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
971 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
973 /* No need to intercept these MSRs */
974 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
975 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
979 static void init_vmcb(struct kvm_vcpu *vcpu)
981 struct vcpu_svm *svm = to_svm(vcpu);
982 struct vmcb_control_area *control = &svm->vmcb->control;
983 struct vmcb_save_area *save = &svm->vmcb->save;
985 svm_set_intercept(svm, INTERCEPT_CR0_READ);
986 svm_set_intercept(svm, INTERCEPT_CR3_READ);
987 svm_set_intercept(svm, INTERCEPT_CR4_READ);
988 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
989 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
990 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
991 if (!kvm_vcpu_apicv_active(vcpu))
992 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
994 set_dr_intercepts(svm);
996 set_exception_intercept(svm, PF_VECTOR);
997 set_exception_intercept(svm, UD_VECTOR);
998 set_exception_intercept(svm, MC_VECTOR);
999 set_exception_intercept(svm, AC_VECTOR);
1000 set_exception_intercept(svm, DB_VECTOR);
1002 * Guest access to VMware backdoor ports could legitimately
1003 * trigger #GP because of TSS I/O permission bitmap.
1004 * We intercept those #GP and allow access to them anyway
1005 * as VMware does. Don't intercept #GP for SEV guests as KVM can't
1006 * decrypt guest memory to decode the faulting instruction.
1008 if (enable_vmware_backdoor && !sev_guest(vcpu->kvm))
1009 set_exception_intercept(svm, GP_VECTOR);
1011 svm_set_intercept(svm, INTERCEPT_INTR);
1012 svm_set_intercept(svm, INTERCEPT_NMI);
1015 svm_set_intercept(svm, INTERCEPT_SMI);
1017 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1018 svm_set_intercept(svm, INTERCEPT_RDPMC);
1019 svm_set_intercept(svm, INTERCEPT_CPUID);
1020 svm_set_intercept(svm, INTERCEPT_INVD);
1021 svm_set_intercept(svm, INTERCEPT_INVLPG);
1022 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1023 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1024 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1025 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1026 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1027 svm_set_intercept(svm, INTERCEPT_VMRUN);
1028 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1029 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1030 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1031 svm_set_intercept(svm, INTERCEPT_STGI);
1032 svm_set_intercept(svm, INTERCEPT_CLGI);
1033 svm_set_intercept(svm, INTERCEPT_SKINIT);
1034 svm_set_intercept(svm, INTERCEPT_WBINVD);
1035 svm_set_intercept(svm, INTERCEPT_XSETBV);
1036 svm_set_intercept(svm, INTERCEPT_RDPRU);
1037 svm_set_intercept(svm, INTERCEPT_RSM);
1039 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1040 svm_set_intercept(svm, INTERCEPT_MONITOR);
1041 svm_set_intercept(svm, INTERCEPT_MWAIT);
1044 if (!kvm_hlt_in_guest(vcpu->kvm))
1045 svm_set_intercept(svm, INTERCEPT_HLT);
1047 control->iopm_base_pa = __sme_set(iopm_base);
1048 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1049 control->int_ctl = V_INTR_MASKING_MASK;
1051 init_seg(&save->es);
1052 init_seg(&save->ss);
1053 init_seg(&save->ds);
1054 init_seg(&save->fs);
1055 init_seg(&save->gs);
1057 save->cs.selector = 0xf000;
1058 save->cs.base = 0xffff0000;
1059 /* Executable/Readable Code Segment */
1060 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1061 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1062 save->cs.limit = 0xffff;
1064 save->gdtr.base = 0;
1065 save->gdtr.limit = 0xffff;
1066 save->idtr.base = 0;
1067 save->idtr.limit = 0xffff;
1069 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1070 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1073 /* Setup VMCB for Nested Paging */
1074 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1075 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1076 clr_exception_intercept(svm, PF_VECTOR);
1077 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1078 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1079 save->g_pat = vcpu->arch.pat;
1082 svm->current_vmcb->asid_generation = 0;
1085 svm->nested.vmcb12_gpa = INVALID_GPA;
1086 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1088 if (!kvm_pause_in_guest(vcpu->kvm)) {
1089 control->pause_filter_count = pause_filter_count;
1090 if (pause_filter_thresh)
1091 control->pause_filter_thresh = pause_filter_thresh;
1092 svm_set_intercept(svm, INTERCEPT_PAUSE);
1094 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1097 svm_recalc_instruction_intercepts(vcpu, svm);
1100 * If the host supports V_SPEC_CTRL then disable the interception
1101 * of MSR_IA32_SPEC_CTRL.
1103 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1104 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1106 if (kvm_vcpu_apicv_active(vcpu))
1107 avic_init_vmcb(svm);
1110 svm_clr_intercept(svm, INTERCEPT_STGI);
1111 svm_clr_intercept(svm, INTERCEPT_CLGI);
1112 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1115 if (sev_guest(vcpu->kvm)) {
1116 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1117 clr_exception_intercept(svm, UD_VECTOR);
1119 if (sev_es_guest(vcpu->kvm)) {
1120 /* Perform SEV-ES specific VMCB updates */
1121 sev_es_init_vmcb(svm);
1125 svm_hv_init_vmcb(svm->vmcb);
1126 init_vmcb_after_set_cpuid(vcpu);
1128 vmcb_mark_all_dirty(svm->vmcb);
1133 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1135 struct vcpu_svm *svm = to_svm(vcpu);
1137 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1139 svm_init_osvw(vcpu);
1140 vcpu->arch.microcode_version = 0x01000065;
1141 svm->tsc_ratio_msr = kvm_default_tsc_scaling_ratio;
1143 if (sev_es_guest(vcpu->kvm))
1144 sev_es_vcpu_reset(svm);
1147 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1149 struct vcpu_svm *svm = to_svm(vcpu);
1152 svm->virt_spec_ctrl = 0;
1157 __svm_vcpu_reset(vcpu);
1160 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1162 svm->current_vmcb = target_vmcb;
1163 svm->vmcb = target_vmcb->ptr;
1166 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1168 struct vcpu_svm *svm;
1169 struct page *vmcb01_page;
1170 struct page *vmsa_page = NULL;
1173 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1177 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1181 if (sev_es_guest(vcpu->kvm)) {
1183 * SEV-ES guests require a separate VMSA page used to contain
1184 * the encrypted register state of the guest.
1186 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1188 goto error_free_vmcb_page;
1191 * SEV-ES guests maintain an encrypted version of their FPU
1192 * state which is restored and saved on VMRUN and VMEXIT.
1193 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1194 * do xsave/xrstor on it.
1196 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1199 err = avic_init_vcpu(svm);
1201 goto error_free_vmsa_page;
1203 svm->msrpm = svm_vcpu_alloc_msrpm();
1206 goto error_free_vmsa_page;
1209 svm->vmcb01.ptr = page_address(vmcb01_page);
1210 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1211 svm_switch_vmcb(svm, &svm->vmcb01);
1214 svm->sev_es.vmsa = page_address(vmsa_page);
1216 svm->guest_state_loaded = false;
1220 error_free_vmsa_page:
1222 __free_page(vmsa_page);
1223 error_free_vmcb_page:
1224 __free_page(vmcb01_page);
1229 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1233 for_each_online_cpu(i)
1234 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1237 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1239 struct vcpu_svm *svm = to_svm(vcpu);
1242 * The vmcb page can be recycled, causing a false negative in
1243 * svm_vcpu_load(). So, ensure that no logical CPU has this
1244 * vmcb page recorded as its current vmcb.
1246 svm_clear_current_vmcb(svm->vmcb);
1248 svm_free_nested(svm);
1250 sev_free_vcpu(vcpu);
1252 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1253 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1256 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1258 struct vcpu_svm *svm = to_svm(vcpu);
1259 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1261 if (sev_es_guest(vcpu->kvm))
1262 sev_es_unmap_ghcb(svm);
1264 if (svm->guest_state_loaded)
1268 * Save additional host state that will be restored on VMEXIT (sev-es)
1269 * or subsequent vmload of host save area.
1271 vmsave(__sme_page_pa(sd->save_area));
1272 if (sev_es_guest(vcpu->kvm)) {
1273 struct vmcb_save_area *hostsa;
1274 hostsa = (struct vmcb_save_area *)(page_address(sd->save_area) + 0x400);
1276 sev_es_prepare_switch_to_guest(hostsa);
1280 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1281 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1282 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1283 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1287 if (likely(tsc_aux_uret_slot >= 0))
1288 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1290 svm->guest_state_loaded = true;
1293 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1295 to_svm(vcpu)->guest_state_loaded = false;
1298 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1300 struct vcpu_svm *svm = to_svm(vcpu);
1301 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1303 if (sd->current_vmcb != svm->vmcb) {
1304 sd->current_vmcb = svm->vmcb;
1305 indirect_branch_prediction_barrier();
1307 if (kvm_vcpu_apicv_active(vcpu))
1308 __avic_vcpu_load(vcpu, cpu);
1311 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1313 if (kvm_vcpu_apicv_active(vcpu))
1314 __avic_vcpu_put(vcpu);
1316 svm_prepare_host_switch(vcpu);
1318 ++vcpu->stat.host_state_reload;
1321 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1323 struct vcpu_svm *svm = to_svm(vcpu);
1324 unsigned long rflags = svm->vmcb->save.rflags;
1326 if (svm->nmi_singlestep) {
1327 /* Hide our flags if they were not set by the guest */
1328 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1329 rflags &= ~X86_EFLAGS_TF;
1330 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1331 rflags &= ~X86_EFLAGS_RF;
1336 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1338 if (to_svm(vcpu)->nmi_singlestep)
1339 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1342 * Any change of EFLAGS.VM is accompanied by a reload of SS
1343 * (caused by either a task switch or an inter-privilege IRET),
1344 * so we do not need to update the CPL here.
1346 to_svm(vcpu)->vmcb->save.rflags = rflags;
1349 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1351 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1353 return sev_es_guest(vcpu->kvm)
1354 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1355 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1358 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1360 kvm_register_mark_available(vcpu, reg);
1363 case VCPU_EXREG_PDPTR:
1365 * When !npt_enabled, mmu->pdptrs[] is already available since
1366 * it is always updated per SDM when moving to CRs.
1369 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1372 KVM_BUG_ON(1, vcpu->kvm);
1376 static void svm_set_vintr(struct vcpu_svm *svm)
1378 struct vmcb_control_area *control;
1381 * The following fields are ignored when AVIC is enabled
1383 WARN_ON(kvm_apicv_activated(svm->vcpu.kvm));
1385 svm_set_intercept(svm, INTERCEPT_VINTR);
1388 * This is just a dummy VINTR to actually cause a vmexit to happen.
1389 * Actual injection of virtual interrupts happens through EVENTINJ.
1391 control = &svm->vmcb->control;
1392 control->int_vector = 0x0;
1393 control->int_ctl &= ~V_INTR_PRIO_MASK;
1394 control->int_ctl |= V_IRQ_MASK |
1395 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1396 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1399 static void svm_clear_vintr(struct vcpu_svm *svm)
1401 svm_clr_intercept(svm, INTERCEPT_VINTR);
1403 /* Drop int_ctl fields related to VINTR injection. */
1404 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1405 if (is_guest_mode(&svm->vcpu)) {
1406 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1408 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1409 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1411 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1412 V_IRQ_INJECTION_BITS_MASK;
1414 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1417 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1420 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1422 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1423 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1426 case VCPU_SREG_CS: return &save->cs;
1427 case VCPU_SREG_DS: return &save->ds;
1428 case VCPU_SREG_ES: return &save->es;
1429 case VCPU_SREG_FS: return &save01->fs;
1430 case VCPU_SREG_GS: return &save01->gs;
1431 case VCPU_SREG_SS: return &save->ss;
1432 case VCPU_SREG_TR: return &save01->tr;
1433 case VCPU_SREG_LDTR: return &save01->ldtr;
1439 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1441 struct vmcb_seg *s = svm_seg(vcpu, seg);
1446 static void svm_get_segment(struct kvm_vcpu *vcpu,
1447 struct kvm_segment *var, int seg)
1449 struct vmcb_seg *s = svm_seg(vcpu, seg);
1451 var->base = s->base;
1452 var->limit = s->limit;
1453 var->selector = s->selector;
1454 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1455 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1456 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1457 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1458 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1459 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1460 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1463 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1464 * However, the SVM spec states that the G bit is not observed by the
1465 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1466 * So let's synthesize a legal G bit for all segments, this helps
1467 * running KVM nested. It also helps cross-vendor migration, because
1468 * Intel's vmentry has a check on the 'G' bit.
1470 var->g = s->limit > 0xfffff;
1473 * AMD's VMCB does not have an explicit unusable field, so emulate it
1474 * for cross vendor migration purposes by "not present"
1476 var->unusable = !var->present;
1481 * Work around a bug where the busy flag in the tr selector
1491 * The accessed bit must always be set in the segment
1492 * descriptor cache, although it can be cleared in the
1493 * descriptor, the cached bit always remains at 1. Since
1494 * Intel has a check on this, set it here to support
1495 * cross-vendor migration.
1502 * On AMD CPUs sometimes the DB bit in the segment
1503 * descriptor is left as 1, although the whole segment has
1504 * been made unusable. Clear it here to pass an Intel VMX
1505 * entry check when cross vendor migrating.
1509 /* This is symmetric with svm_set_segment() */
1510 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1515 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1517 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1522 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1524 struct kvm_segment cs;
1526 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1531 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1533 struct vcpu_svm *svm = to_svm(vcpu);
1535 dt->size = svm->vmcb->save.idtr.limit;
1536 dt->address = svm->vmcb->save.idtr.base;
1539 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1541 struct vcpu_svm *svm = to_svm(vcpu);
1543 svm->vmcb->save.idtr.limit = dt->size;
1544 svm->vmcb->save.idtr.base = dt->address ;
1545 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1548 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1550 struct vcpu_svm *svm = to_svm(vcpu);
1552 dt->size = svm->vmcb->save.gdtr.limit;
1553 dt->address = svm->vmcb->save.gdtr.base;
1556 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1558 struct vcpu_svm *svm = to_svm(vcpu);
1560 svm->vmcb->save.gdtr.limit = dt->size;
1561 svm->vmcb->save.gdtr.base = dt->address ;
1562 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1565 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1567 struct vcpu_svm *svm = to_svm(vcpu);
1570 * For guests that don't set guest_state_protected, the cr3 update is
1571 * handled via kvm_mmu_load() while entering the guest. For guests
1572 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1573 * VMCB save area now, since the save area will become the initial
1574 * contents of the VMSA, and future VMCB save area updates won't be
1577 if (sev_es_guest(vcpu->kvm)) {
1578 svm->vmcb->save.cr3 = cr3;
1579 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1583 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1585 struct vcpu_svm *svm = to_svm(vcpu);
1587 bool old_paging = is_paging(vcpu);
1589 #ifdef CONFIG_X86_64
1590 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1591 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1592 vcpu->arch.efer |= EFER_LMA;
1593 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1596 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1597 vcpu->arch.efer &= ~EFER_LMA;
1598 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1602 vcpu->arch.cr0 = cr0;
1605 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1606 if (old_paging != is_paging(vcpu))
1607 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1611 * re-enable caching here because the QEMU bios
1612 * does not do it - this results in some delay at
1615 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1616 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1618 svm->vmcb->save.cr0 = hcr0;
1619 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1622 * SEV-ES guests must always keep the CR intercepts cleared. CR
1623 * tracking is done using the CR write traps.
1625 if (sev_es_guest(vcpu->kvm))
1629 /* Selective CR0 write remains on. */
1630 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1631 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1633 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1634 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1638 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1643 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1645 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1646 unsigned long old_cr4 = vcpu->arch.cr4;
1648 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1649 svm_flush_tlb_current(vcpu);
1651 vcpu->arch.cr4 = cr4;
1655 if (!is_paging(vcpu))
1656 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1658 cr4 |= host_cr4_mce;
1659 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1660 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1662 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1663 kvm_update_cpuid_runtime(vcpu);
1666 static void svm_set_segment(struct kvm_vcpu *vcpu,
1667 struct kvm_segment *var, int seg)
1669 struct vcpu_svm *svm = to_svm(vcpu);
1670 struct vmcb_seg *s = svm_seg(vcpu, seg);
1672 s->base = var->base;
1673 s->limit = var->limit;
1674 s->selector = var->selector;
1675 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1676 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1677 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1678 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1679 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1680 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1681 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1682 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1685 * This is always accurate, except if SYSRET returned to a segment
1686 * with SS.DPL != 3. Intel does not have this quirk, and always
1687 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1688 * would entail passing the CPL to userspace and back.
1690 if (seg == VCPU_SREG_SS)
1691 /* This is symmetric with svm_get_segment() */
1692 svm->vmcb->save.cpl = (var->dpl & 3);
1694 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1697 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1699 struct vcpu_svm *svm = to_svm(vcpu);
1701 clr_exception_intercept(svm, BP_VECTOR);
1703 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1704 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1705 set_exception_intercept(svm, BP_VECTOR);
1709 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1711 if (sd->next_asid > sd->max_asid) {
1712 ++sd->asid_generation;
1713 sd->next_asid = sd->min_asid;
1714 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1715 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1718 svm->current_vmcb->asid_generation = sd->asid_generation;
1719 svm->asid = sd->next_asid++;
1722 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1724 struct vmcb *vmcb = svm->vmcb;
1726 if (svm->vcpu.arch.guest_state_protected)
1729 if (unlikely(value != vmcb->save.dr6)) {
1730 vmcb->save.dr6 = value;
1731 vmcb_mark_dirty(vmcb, VMCB_DR);
1735 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1737 struct vcpu_svm *svm = to_svm(vcpu);
1739 if (vcpu->arch.guest_state_protected)
1742 get_debugreg(vcpu->arch.db[0], 0);
1743 get_debugreg(vcpu->arch.db[1], 1);
1744 get_debugreg(vcpu->arch.db[2], 2);
1745 get_debugreg(vcpu->arch.db[3], 3);
1747 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1748 * because db_interception might need it. We can do it before vmentry.
1750 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1751 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1752 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1753 set_dr_intercepts(svm);
1756 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1758 struct vcpu_svm *svm = to_svm(vcpu);
1760 if (vcpu->arch.guest_state_protected)
1763 svm->vmcb->save.dr7 = value;
1764 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1767 static int pf_interception(struct kvm_vcpu *vcpu)
1769 struct vcpu_svm *svm = to_svm(vcpu);
1771 u64 fault_address = svm->vmcb->control.exit_info_2;
1772 u64 error_code = svm->vmcb->control.exit_info_1;
1774 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1775 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1776 svm->vmcb->control.insn_bytes : NULL,
1777 svm->vmcb->control.insn_len);
1780 static int npf_interception(struct kvm_vcpu *vcpu)
1782 struct vcpu_svm *svm = to_svm(vcpu);
1784 u64 fault_address = svm->vmcb->control.exit_info_2;
1785 u64 error_code = svm->vmcb->control.exit_info_1;
1787 trace_kvm_page_fault(fault_address, error_code);
1788 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1789 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1790 svm->vmcb->control.insn_bytes : NULL,
1791 svm->vmcb->control.insn_len);
1794 static int db_interception(struct kvm_vcpu *vcpu)
1796 struct kvm_run *kvm_run = vcpu->run;
1797 struct vcpu_svm *svm = to_svm(vcpu);
1799 if (!(vcpu->guest_debug &
1800 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1801 !svm->nmi_singlestep) {
1802 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1803 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1807 if (svm->nmi_singlestep) {
1808 disable_nmi_singlestep(svm);
1809 /* Make sure we check for pending NMIs upon entry */
1810 kvm_make_request(KVM_REQ_EVENT, vcpu);
1813 if (vcpu->guest_debug &
1814 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1815 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1816 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1817 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1818 kvm_run->debug.arch.pc =
1819 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1820 kvm_run->debug.arch.exception = DB_VECTOR;
1827 static int bp_interception(struct kvm_vcpu *vcpu)
1829 struct vcpu_svm *svm = to_svm(vcpu);
1830 struct kvm_run *kvm_run = vcpu->run;
1832 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1833 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1834 kvm_run->debug.arch.exception = BP_VECTOR;
1838 static int ud_interception(struct kvm_vcpu *vcpu)
1840 return handle_ud(vcpu);
1843 static int ac_interception(struct kvm_vcpu *vcpu)
1845 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1849 static bool is_erratum_383(void)
1854 if (!erratum_383_found)
1857 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1861 /* Bit 62 may or may not be set for this mce */
1862 value &= ~(1ULL << 62);
1864 if (value != 0xb600000000010015ULL)
1867 /* Clear MCi_STATUS registers */
1868 for (i = 0; i < 6; ++i)
1869 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1871 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1875 value &= ~(1ULL << 2);
1876 low = lower_32_bits(value);
1877 high = upper_32_bits(value);
1879 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1882 /* Flush tlb to evict multi-match entries */
1888 static void svm_handle_mce(struct kvm_vcpu *vcpu)
1890 if (is_erratum_383()) {
1892 * Erratum 383 triggered. Guest state is corrupt so kill the
1895 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1897 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1903 * On an #MC intercept the MCE handler is not called automatically in
1904 * the host. So do it by hand here.
1906 kvm_machine_check();
1909 static int mc_interception(struct kvm_vcpu *vcpu)
1914 static int shutdown_interception(struct kvm_vcpu *vcpu)
1916 struct kvm_run *kvm_run = vcpu->run;
1917 struct vcpu_svm *svm = to_svm(vcpu);
1920 * The VM save area has already been encrypted so it
1921 * cannot be reinitialized - just terminate.
1923 if (sev_es_guest(vcpu->kvm))
1927 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
1928 * the VMCB in a known good state. Unfortuately, KVM doesn't have
1929 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
1930 * userspace. At a platform view, INIT is acceptable behavior as
1931 * there exist bare metal platforms that automatically INIT the CPU
1932 * in response to shutdown.
1934 clear_page(svm->vmcb);
1935 kvm_vcpu_reset(vcpu, true);
1937 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1941 static int io_interception(struct kvm_vcpu *vcpu)
1943 struct vcpu_svm *svm = to_svm(vcpu);
1944 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1945 int size, in, string;
1948 ++vcpu->stat.io_exits;
1949 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1950 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1951 port = io_info >> 16;
1952 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1955 if (sev_es_guest(vcpu->kvm))
1956 return sev_es_string_io(svm, size, port, in);
1958 return kvm_emulate_instruction(vcpu, 0);
1961 svm->next_rip = svm->vmcb->control.exit_info_2;
1963 return kvm_fast_pio(vcpu, size, port, in);
1966 static int nmi_interception(struct kvm_vcpu *vcpu)
1971 static int smi_interception(struct kvm_vcpu *vcpu)
1976 static int intr_interception(struct kvm_vcpu *vcpu)
1978 ++vcpu->stat.irq_exits;
1982 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
1984 struct vcpu_svm *svm = to_svm(vcpu);
1985 struct vmcb *vmcb12;
1986 struct kvm_host_map map;
1989 if (nested_svm_check_permissions(vcpu))
1992 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1995 kvm_inject_gp(vcpu, 0);
2001 ret = kvm_skip_emulated_instruction(vcpu);
2004 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2005 svm->sysenter_eip_hi = 0;
2006 svm->sysenter_esp_hi = 0;
2008 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2011 kvm_vcpu_unmap(vcpu, &map, true);
2016 static int vmload_interception(struct kvm_vcpu *vcpu)
2018 return vmload_vmsave_interception(vcpu, true);
2021 static int vmsave_interception(struct kvm_vcpu *vcpu)
2023 return vmload_vmsave_interception(vcpu, false);
2026 static int vmrun_interception(struct kvm_vcpu *vcpu)
2028 if (nested_svm_check_permissions(vcpu))
2031 return nested_svm_vmrun(vcpu);
2041 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2042 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2044 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2046 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2047 return NONE_SVM_INSTR;
2049 switch (ctxt->modrm) {
2050 case 0xd8: /* VMRUN */
2051 return SVM_INSTR_VMRUN;
2052 case 0xda: /* VMLOAD */
2053 return SVM_INSTR_VMLOAD;
2054 case 0xdb: /* VMSAVE */
2055 return SVM_INSTR_VMSAVE;
2060 return NONE_SVM_INSTR;
2063 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2065 const int guest_mode_exit_codes[] = {
2066 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2067 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2068 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2070 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2071 [SVM_INSTR_VMRUN] = vmrun_interception,
2072 [SVM_INSTR_VMLOAD] = vmload_interception,
2073 [SVM_INSTR_VMSAVE] = vmsave_interception,
2075 struct vcpu_svm *svm = to_svm(vcpu);
2078 if (is_guest_mode(vcpu)) {
2079 /* Returns '1' or -errno on failure, '0' on success. */
2080 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2085 return svm_instr_handlers[opcode](vcpu);
2089 * #GP handling code. Note that #GP can be triggered under the following two
2091 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2092 * some AMD CPUs when EAX of these instructions are in the reserved memory
2093 * regions (e.g. SMM memory on host).
2094 * 2) VMware backdoor
2096 static int gp_interception(struct kvm_vcpu *vcpu)
2098 struct vcpu_svm *svm = to_svm(vcpu);
2099 u32 error_code = svm->vmcb->control.exit_info_1;
2102 /* Both #GP cases have zero error_code */
2106 /* Decode the instruction for usage later */
2107 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2110 opcode = svm_instr_opcode(vcpu);
2112 if (opcode == NONE_SVM_INSTR) {
2113 if (!enable_vmware_backdoor)
2117 * VMware backdoor emulation on #GP interception only handles
2118 * IN{S}, OUT{S}, and RDPMC.
2120 if (!is_guest_mode(vcpu))
2121 return kvm_emulate_instruction(vcpu,
2122 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2124 /* All SVM instructions expect page aligned RAX */
2125 if (svm->vmcb->save.rax & ~PAGE_MASK)
2128 return emulate_svm_instr(vcpu, opcode);
2132 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2136 void svm_set_gif(struct vcpu_svm *svm, bool value)
2140 * If VGIF is enabled, the STGI intercept is only added to
2141 * detect the opening of the SMI/NMI window; remove it now.
2142 * Likewise, clear the VINTR intercept, we will set it
2143 * again while processing KVM_REQ_EVENT if needed.
2145 if (vgif_enabled(svm))
2146 svm_clr_intercept(svm, INTERCEPT_STGI);
2147 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2148 svm_clear_vintr(svm);
2151 if (svm->vcpu.arch.smi_pending ||
2152 svm->vcpu.arch.nmi_pending ||
2153 kvm_cpu_has_injectable_intr(&svm->vcpu))
2154 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2159 * After a CLGI no interrupts should come. But if vGIF is
2160 * in use, we still rely on the VINTR intercept (rather than
2161 * STGI) to detect an open interrupt window.
2163 if (!vgif_enabled(svm))
2164 svm_clear_vintr(svm);
2168 static int stgi_interception(struct kvm_vcpu *vcpu)
2172 if (nested_svm_check_permissions(vcpu))
2175 ret = kvm_skip_emulated_instruction(vcpu);
2176 svm_set_gif(to_svm(vcpu), true);
2180 static int clgi_interception(struct kvm_vcpu *vcpu)
2184 if (nested_svm_check_permissions(vcpu))
2187 ret = kvm_skip_emulated_instruction(vcpu);
2188 svm_set_gif(to_svm(vcpu), false);
2192 static int invlpga_interception(struct kvm_vcpu *vcpu)
2194 gva_t gva = kvm_rax_read(vcpu);
2195 u32 asid = kvm_rcx_read(vcpu);
2197 /* FIXME: Handle an address size prefix. */
2198 if (!is_long_mode(vcpu))
2201 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2203 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2204 kvm_mmu_invlpg(vcpu, gva);
2206 return kvm_skip_emulated_instruction(vcpu);
2209 static int skinit_interception(struct kvm_vcpu *vcpu)
2211 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2213 kvm_queue_exception(vcpu, UD_VECTOR);
2217 static int task_switch_interception(struct kvm_vcpu *vcpu)
2219 struct vcpu_svm *svm = to_svm(vcpu);
2222 int int_type = svm->vmcb->control.exit_int_info &
2223 SVM_EXITINTINFO_TYPE_MASK;
2224 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2226 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2228 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2229 bool has_error_code = false;
2232 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2234 if (svm->vmcb->control.exit_info_2 &
2235 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2236 reason = TASK_SWITCH_IRET;
2237 else if (svm->vmcb->control.exit_info_2 &
2238 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2239 reason = TASK_SWITCH_JMP;
2241 reason = TASK_SWITCH_GATE;
2243 reason = TASK_SWITCH_CALL;
2245 if (reason == TASK_SWITCH_GATE) {
2247 case SVM_EXITINTINFO_TYPE_NMI:
2248 vcpu->arch.nmi_injected = false;
2250 case SVM_EXITINTINFO_TYPE_EXEPT:
2251 if (svm->vmcb->control.exit_info_2 &
2252 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2253 has_error_code = true;
2255 (u32)svm->vmcb->control.exit_info_2;
2257 kvm_clear_exception_queue(vcpu);
2259 case SVM_EXITINTINFO_TYPE_INTR:
2260 kvm_clear_interrupt_queue(vcpu);
2267 if (reason != TASK_SWITCH_GATE ||
2268 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2269 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2270 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2271 if (!svm_skip_emulated_instruction(vcpu))
2275 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2278 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2279 has_error_code, error_code);
2282 static int iret_interception(struct kvm_vcpu *vcpu)
2284 struct vcpu_svm *svm = to_svm(vcpu);
2286 ++vcpu->stat.nmi_window_exits;
2287 vcpu->arch.hflags |= HF_IRET_MASK;
2288 if (!sev_es_guest(vcpu->kvm)) {
2289 svm_clr_intercept(svm, INTERCEPT_IRET);
2290 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2292 kvm_make_request(KVM_REQ_EVENT, vcpu);
2296 static int invlpg_interception(struct kvm_vcpu *vcpu)
2298 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2299 return kvm_emulate_instruction(vcpu, 0);
2301 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2302 return kvm_skip_emulated_instruction(vcpu);
2305 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2307 return kvm_emulate_instruction(vcpu, 0);
2310 static int rsm_interception(struct kvm_vcpu *vcpu)
2312 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2315 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2318 struct vcpu_svm *svm = to_svm(vcpu);
2319 unsigned long cr0 = vcpu->arch.cr0;
2322 if (!is_guest_mode(vcpu) ||
2323 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2326 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2327 val &= ~SVM_CR0_SELECTIVE_MASK;
2330 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2331 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2337 #define CR_VALID (1ULL << 63)
2339 static int cr_interception(struct kvm_vcpu *vcpu)
2341 struct vcpu_svm *svm = to_svm(vcpu);
2346 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2347 return emulate_on_interception(vcpu);
2349 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2350 return emulate_on_interception(vcpu);
2352 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2353 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2354 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2356 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2359 if (cr >= 16) { /* mov to cr */
2361 val = kvm_register_read(vcpu, reg);
2362 trace_kvm_cr_write(cr, val);
2365 if (!check_selective_cr0_intercepted(vcpu, val))
2366 err = kvm_set_cr0(vcpu, val);
2372 err = kvm_set_cr3(vcpu, val);
2375 err = kvm_set_cr4(vcpu, val);
2378 err = kvm_set_cr8(vcpu, val);
2381 WARN(1, "unhandled write to CR%d", cr);
2382 kvm_queue_exception(vcpu, UD_VECTOR);
2385 } else { /* mov from cr */
2388 val = kvm_read_cr0(vcpu);
2391 val = vcpu->arch.cr2;
2394 val = kvm_read_cr3(vcpu);
2397 val = kvm_read_cr4(vcpu);
2400 val = kvm_get_cr8(vcpu);
2403 WARN(1, "unhandled read from CR%d", cr);
2404 kvm_queue_exception(vcpu, UD_VECTOR);
2407 kvm_register_write(vcpu, reg, val);
2408 trace_kvm_cr_read(cr, val);
2410 return kvm_complete_insn_gp(vcpu, err);
2413 static int cr_trap(struct kvm_vcpu *vcpu)
2415 struct vcpu_svm *svm = to_svm(vcpu);
2416 unsigned long old_value, new_value;
2420 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2422 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2425 old_value = kvm_read_cr0(vcpu);
2426 svm_set_cr0(vcpu, new_value);
2428 kvm_post_set_cr0(vcpu, old_value, new_value);
2431 old_value = kvm_read_cr4(vcpu);
2432 svm_set_cr4(vcpu, new_value);
2434 kvm_post_set_cr4(vcpu, old_value, new_value);
2437 ret = kvm_set_cr8(vcpu, new_value);
2440 WARN(1, "unhandled CR%d write trap", cr);
2441 kvm_queue_exception(vcpu, UD_VECTOR);
2445 return kvm_complete_insn_gp(vcpu, ret);
2448 static int dr_interception(struct kvm_vcpu *vcpu)
2450 struct vcpu_svm *svm = to_svm(vcpu);
2455 if (vcpu->guest_debug == 0) {
2457 * No more DR vmexits; force a reload of the debug registers
2458 * and reenter on this instruction. The next vmexit will
2459 * retrieve the full state of the debug registers.
2461 clr_dr_intercepts(svm);
2462 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2466 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2467 return emulate_on_interception(vcpu);
2469 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2470 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2471 if (dr >= 16) { /* mov to DRn */
2473 val = kvm_register_read(vcpu, reg);
2474 err = kvm_set_dr(vcpu, dr, val);
2476 kvm_get_dr(vcpu, dr, &val);
2477 kvm_register_write(vcpu, reg, val);
2480 return kvm_complete_insn_gp(vcpu, err);
2483 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2487 u8 cr8_prev = kvm_get_cr8(vcpu);
2488 /* instruction emulation calls kvm_set_cr8() */
2489 r = cr_interception(vcpu);
2490 if (lapic_in_kernel(vcpu))
2492 if (cr8_prev <= kvm_get_cr8(vcpu))
2494 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2498 static int efer_trap(struct kvm_vcpu *vcpu)
2500 struct msr_data msr_info;
2504 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2505 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2506 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2507 * the guest doesn't have X86_FEATURE_SVM.
2509 msr_info.host_initiated = false;
2510 msr_info.index = MSR_EFER;
2511 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2512 ret = kvm_set_msr_common(vcpu, &msr_info);
2514 return kvm_complete_insn_gp(vcpu, ret);
2517 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2521 switch (msr->index) {
2522 case MSR_F10H_DECFG:
2523 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2524 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2526 case MSR_IA32_PERF_CAPABILITIES:
2529 return KVM_MSR_RET_INVALID;
2535 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2537 struct vcpu_svm *svm = to_svm(vcpu);
2539 switch (msr_info->index) {
2540 case MSR_AMD64_TSC_RATIO:
2541 if (!msr_info->host_initiated && !svm->tsc_scaling_enabled)
2543 msr_info->data = svm->tsc_ratio_msr;
2546 msr_info->data = svm->vmcb01.ptr->save.star;
2548 #ifdef CONFIG_X86_64
2550 msr_info->data = svm->vmcb01.ptr->save.lstar;
2553 msr_info->data = svm->vmcb01.ptr->save.cstar;
2555 case MSR_KERNEL_GS_BASE:
2556 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2558 case MSR_SYSCALL_MASK:
2559 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2562 case MSR_IA32_SYSENTER_CS:
2563 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2565 case MSR_IA32_SYSENTER_EIP:
2566 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2567 if (guest_cpuid_is_intel(vcpu))
2568 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2570 case MSR_IA32_SYSENTER_ESP:
2571 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2572 if (guest_cpuid_is_intel(vcpu))
2573 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2576 msr_info->data = svm->tsc_aux;
2579 * Nobody will change the following 5 values in the VMCB so we can
2580 * safely return them on rdmsr. They will always be 0 until LBRV is
2583 case MSR_IA32_DEBUGCTLMSR:
2584 msr_info->data = svm->vmcb->save.dbgctl;
2586 case MSR_IA32_LASTBRANCHFROMIP:
2587 msr_info->data = svm->vmcb->save.br_from;
2589 case MSR_IA32_LASTBRANCHTOIP:
2590 msr_info->data = svm->vmcb->save.br_to;
2592 case MSR_IA32_LASTINTFROMIP:
2593 msr_info->data = svm->vmcb->save.last_excp_from;
2595 case MSR_IA32_LASTINTTOIP:
2596 msr_info->data = svm->vmcb->save.last_excp_to;
2598 case MSR_VM_HSAVE_PA:
2599 msr_info->data = svm->nested.hsave_msr;
2602 msr_info->data = svm->nested.vm_cr_msr;
2604 case MSR_IA32_SPEC_CTRL:
2605 if (!msr_info->host_initiated &&
2606 !guest_has_spec_ctrl_msr(vcpu))
2609 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2610 msr_info->data = svm->vmcb->save.spec_ctrl;
2612 msr_info->data = svm->spec_ctrl;
2614 case MSR_AMD64_VIRT_SPEC_CTRL:
2615 if (!msr_info->host_initiated &&
2616 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2619 msr_info->data = svm->virt_spec_ctrl;
2621 case MSR_F15H_IC_CFG: {
2625 family = guest_cpuid_family(vcpu);
2626 model = guest_cpuid_model(vcpu);
2628 if (family < 0 || model < 0)
2629 return kvm_get_msr_common(vcpu, msr_info);
2633 if (family == 0x15 &&
2634 (model >= 0x2 && model < 0x20))
2635 msr_info->data = 0x1E;
2638 case MSR_F10H_DECFG:
2639 msr_info->data = svm->msr_decfg;
2642 return kvm_get_msr_common(vcpu, msr_info);
2647 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2649 struct vcpu_svm *svm = to_svm(vcpu);
2650 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2651 return kvm_complete_insn_gp(vcpu, err);
2653 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2654 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2656 SVM_EVTINJ_TYPE_EXEPT |
2661 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2663 struct vcpu_svm *svm = to_svm(vcpu);
2664 int svm_dis, chg_mask;
2666 if (data & ~SVM_VM_CR_VALID_MASK)
2669 chg_mask = SVM_VM_CR_VALID_MASK;
2671 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2672 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2674 svm->nested.vm_cr_msr &= ~chg_mask;
2675 svm->nested.vm_cr_msr |= (data & chg_mask);
2677 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2679 /* check for svm_disable while efer.svme is set */
2680 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2686 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2688 struct vcpu_svm *svm = to_svm(vcpu);
2691 u32 ecx = msr->index;
2692 u64 data = msr->data;
2694 case MSR_AMD64_TSC_RATIO:
2696 if (!svm->tsc_scaling_enabled) {
2698 if (!msr->host_initiated)
2701 * In case TSC scaling is not enabled, always
2702 * leave this MSR at the default value.
2704 * Due to bug in qemu 6.2.0, it would try to set
2705 * this msr to 0 if tsc scaling is not enabled.
2706 * Ignore this value as well.
2708 if (data != 0 && data != svm->tsc_ratio_msr)
2713 if (data & SVM_TSC_RATIO_RSVD)
2716 svm->tsc_ratio_msr = data;
2718 if (svm->tsc_scaling_enabled && is_guest_mode(vcpu))
2719 nested_svm_update_tsc_ratio_msr(vcpu);
2722 case MSR_IA32_CR_PAT:
2723 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2725 vcpu->arch.pat = data;
2726 svm->vmcb01.ptr->save.g_pat = data;
2727 if (is_guest_mode(vcpu))
2728 nested_vmcb02_compute_g_pat(svm);
2729 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2731 case MSR_IA32_SPEC_CTRL:
2732 if (!msr->host_initiated &&
2733 !guest_has_spec_ctrl_msr(vcpu))
2736 if (kvm_spec_ctrl_test_value(data))
2739 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2740 svm->vmcb->save.spec_ctrl = data;
2742 svm->spec_ctrl = data;
2748 * When it's written (to non-zero) for the first time, pass
2752 * The handling of the MSR bitmap for L2 guests is done in
2753 * nested_svm_vmrun_msrpm.
2754 * We update the L1 MSR bit as well since it will end up
2755 * touching the MSR anyway now.
2757 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2759 case MSR_IA32_PRED_CMD:
2760 if (!msr->host_initiated &&
2761 !guest_has_pred_cmd_msr(vcpu))
2764 if (data & ~PRED_CMD_IBPB)
2766 if (!boot_cpu_has(X86_FEATURE_IBPB))
2771 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2772 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2774 case MSR_AMD64_VIRT_SPEC_CTRL:
2775 if (!msr->host_initiated &&
2776 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2779 if (data & ~SPEC_CTRL_SSBD)
2782 svm->virt_spec_ctrl = data;
2785 svm->vmcb01.ptr->save.star = data;
2787 #ifdef CONFIG_X86_64
2789 svm->vmcb01.ptr->save.lstar = data;
2792 svm->vmcb01.ptr->save.cstar = data;
2794 case MSR_KERNEL_GS_BASE:
2795 svm->vmcb01.ptr->save.kernel_gs_base = data;
2797 case MSR_SYSCALL_MASK:
2798 svm->vmcb01.ptr->save.sfmask = data;
2801 case MSR_IA32_SYSENTER_CS:
2802 svm->vmcb01.ptr->save.sysenter_cs = data;
2804 case MSR_IA32_SYSENTER_EIP:
2805 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2807 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2808 * when we spoof an Intel vendor ID (for cross vendor migration).
2809 * In this case we use this intercept to track the high
2810 * 32 bit part of these msrs to support Intel's
2811 * implementation of SYSENTER/SYSEXIT.
2813 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2815 case MSR_IA32_SYSENTER_ESP:
2816 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2817 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2821 * TSC_AUX is usually changed only during boot and never read
2822 * directly. Intercept TSC_AUX instead of exposing it to the
2823 * guest via direct_access_msrs, and switch it via user return.
2826 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2831 svm->tsc_aux = data;
2833 case MSR_IA32_DEBUGCTLMSR:
2835 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2839 if (data & DEBUGCTL_RESERVED_BITS)
2842 svm->vmcb->save.dbgctl = data;
2843 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2844 if (data & (1ULL<<0))
2845 svm_enable_lbrv(vcpu);
2847 svm_disable_lbrv(vcpu);
2849 case MSR_VM_HSAVE_PA:
2851 * Old kernels did not validate the value written to
2852 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
2853 * value to allow live migrating buggy or malicious guests
2854 * originating from those kernels.
2856 if (!msr->host_initiated && !page_address_valid(vcpu, data))
2859 svm->nested.hsave_msr = data & PAGE_MASK;
2862 return svm_set_vm_cr(vcpu, data);
2864 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2866 case MSR_F10H_DECFG: {
2867 struct kvm_msr_entry msr_entry;
2869 msr_entry.index = msr->index;
2870 if (svm_get_msr_feature(&msr_entry))
2873 /* Check the supported bits */
2874 if (data & ~msr_entry.data)
2877 /* Don't allow the guest to change a bit, #GP */
2878 if (!msr->host_initiated && (data ^ msr_entry.data))
2881 svm->msr_decfg = data;
2885 return kvm_set_msr_common(vcpu, msr);
2890 static int msr_interception(struct kvm_vcpu *vcpu)
2892 if (to_svm(vcpu)->vmcb->control.exit_info_1)
2893 return kvm_emulate_wrmsr(vcpu);
2895 return kvm_emulate_rdmsr(vcpu);
2898 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2900 kvm_make_request(KVM_REQ_EVENT, vcpu);
2901 svm_clear_vintr(to_svm(vcpu));
2904 * For AVIC, the only reason to end up here is ExtINTs.
2905 * In this case AVIC was temporarily disabled for
2906 * requesting the IRQ window and we have to re-enable it.
2908 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
2910 ++vcpu->stat.irq_window_exits;
2914 static int pause_interception(struct kvm_vcpu *vcpu)
2919 * CPL is not made available for an SEV-ES guest, therefore
2920 * vcpu->arch.preempted_in_kernel can never be true. Just
2921 * set in_kernel to false as well.
2923 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
2925 if (!kvm_pause_in_guest(vcpu->kvm))
2926 grow_ple_window(vcpu);
2928 kvm_vcpu_on_spin(vcpu, in_kernel);
2929 return kvm_skip_emulated_instruction(vcpu);
2932 static int invpcid_interception(struct kvm_vcpu *vcpu)
2934 struct vcpu_svm *svm = to_svm(vcpu);
2938 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2939 kvm_queue_exception(vcpu, UD_VECTOR);
2944 * For an INVPCID intercept:
2945 * EXITINFO1 provides the linear address of the memory operand.
2946 * EXITINFO2 provides the contents of the register operand.
2948 type = svm->vmcb->control.exit_info_2;
2949 gva = svm->vmcb->control.exit_info_1;
2951 return kvm_handle_invpcid(vcpu, type, gva);
2954 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
2955 [SVM_EXIT_READ_CR0] = cr_interception,
2956 [SVM_EXIT_READ_CR3] = cr_interception,
2957 [SVM_EXIT_READ_CR4] = cr_interception,
2958 [SVM_EXIT_READ_CR8] = cr_interception,
2959 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
2960 [SVM_EXIT_WRITE_CR0] = cr_interception,
2961 [SVM_EXIT_WRITE_CR3] = cr_interception,
2962 [SVM_EXIT_WRITE_CR4] = cr_interception,
2963 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2964 [SVM_EXIT_READ_DR0] = dr_interception,
2965 [SVM_EXIT_READ_DR1] = dr_interception,
2966 [SVM_EXIT_READ_DR2] = dr_interception,
2967 [SVM_EXIT_READ_DR3] = dr_interception,
2968 [SVM_EXIT_READ_DR4] = dr_interception,
2969 [SVM_EXIT_READ_DR5] = dr_interception,
2970 [SVM_EXIT_READ_DR6] = dr_interception,
2971 [SVM_EXIT_READ_DR7] = dr_interception,
2972 [SVM_EXIT_WRITE_DR0] = dr_interception,
2973 [SVM_EXIT_WRITE_DR1] = dr_interception,
2974 [SVM_EXIT_WRITE_DR2] = dr_interception,
2975 [SVM_EXIT_WRITE_DR3] = dr_interception,
2976 [SVM_EXIT_WRITE_DR4] = dr_interception,
2977 [SVM_EXIT_WRITE_DR5] = dr_interception,
2978 [SVM_EXIT_WRITE_DR6] = dr_interception,
2979 [SVM_EXIT_WRITE_DR7] = dr_interception,
2980 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2981 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2982 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2983 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2984 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2985 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
2986 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
2987 [SVM_EXIT_INTR] = intr_interception,
2988 [SVM_EXIT_NMI] = nmi_interception,
2989 [SVM_EXIT_SMI] = smi_interception,
2990 [SVM_EXIT_VINTR] = interrupt_window_interception,
2991 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
2992 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
2993 [SVM_EXIT_IRET] = iret_interception,
2994 [SVM_EXIT_INVD] = kvm_emulate_invd,
2995 [SVM_EXIT_PAUSE] = pause_interception,
2996 [SVM_EXIT_HLT] = kvm_emulate_halt,
2997 [SVM_EXIT_INVLPG] = invlpg_interception,
2998 [SVM_EXIT_INVLPGA] = invlpga_interception,
2999 [SVM_EXIT_IOIO] = io_interception,
3000 [SVM_EXIT_MSR] = msr_interception,
3001 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3002 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3003 [SVM_EXIT_VMRUN] = vmrun_interception,
3004 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3005 [SVM_EXIT_VMLOAD] = vmload_interception,
3006 [SVM_EXIT_VMSAVE] = vmsave_interception,
3007 [SVM_EXIT_STGI] = stgi_interception,
3008 [SVM_EXIT_CLGI] = clgi_interception,
3009 [SVM_EXIT_SKINIT] = skinit_interception,
3010 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3011 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3012 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3013 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3014 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3015 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3016 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3017 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3018 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3019 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3020 [SVM_EXIT_INVPCID] = invpcid_interception,
3021 [SVM_EXIT_NPF] = npf_interception,
3022 [SVM_EXIT_RSM] = rsm_interception,
3023 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3024 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3025 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3028 static void dump_vmcb(struct kvm_vcpu *vcpu)
3030 struct vcpu_svm *svm = to_svm(vcpu);
3031 struct vmcb_control_area *control = &svm->vmcb->control;
3032 struct vmcb_save_area *save = &svm->vmcb->save;
3033 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3035 if (!dump_invalid_vmcb) {
3036 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3040 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3041 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3042 pr_err("VMCB Control Area:\n");
3043 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3044 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3045 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3046 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3047 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3048 pr_err("%-20s%08x %08x\n", "intercepts:",
3049 control->intercepts[INTERCEPT_WORD3],
3050 control->intercepts[INTERCEPT_WORD4]);
3051 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3052 pr_err("%-20s%d\n", "pause filter threshold:",
3053 control->pause_filter_thresh);
3054 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3055 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3056 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3057 pr_err("%-20s%d\n", "asid:", control->asid);
3058 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3059 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3060 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3061 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3062 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3063 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3064 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3065 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3066 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3067 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3068 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3069 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3070 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3071 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3072 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3073 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3074 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3075 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3076 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3077 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3078 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3079 pr_err("VMCB State Save Area:\n");
3080 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3082 save->es.selector, save->es.attrib,
3083 save->es.limit, save->es.base);
3084 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3086 save->cs.selector, save->cs.attrib,
3087 save->cs.limit, save->cs.base);
3088 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3090 save->ss.selector, save->ss.attrib,
3091 save->ss.limit, save->ss.base);
3092 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3094 save->ds.selector, save->ds.attrib,
3095 save->ds.limit, save->ds.base);
3096 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3098 save01->fs.selector, save01->fs.attrib,
3099 save01->fs.limit, save01->fs.base);
3100 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3102 save01->gs.selector, save01->gs.attrib,
3103 save01->gs.limit, save01->gs.base);
3104 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3106 save->gdtr.selector, save->gdtr.attrib,
3107 save->gdtr.limit, save->gdtr.base);
3108 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3110 save01->ldtr.selector, save01->ldtr.attrib,
3111 save01->ldtr.limit, save01->ldtr.base);
3112 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3114 save->idtr.selector, save->idtr.attrib,
3115 save->idtr.limit, save->idtr.base);
3116 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3118 save01->tr.selector, save01->tr.attrib,
3119 save01->tr.limit, save01->tr.base);
3120 pr_err("cpl: %d efer: %016llx\n",
3121 save->cpl, save->efer);
3122 pr_err("%-15s %016llx %-13s %016llx\n",
3123 "cr0:", save->cr0, "cr2:", save->cr2);
3124 pr_err("%-15s %016llx %-13s %016llx\n",
3125 "cr3:", save->cr3, "cr4:", save->cr4);
3126 pr_err("%-15s %016llx %-13s %016llx\n",
3127 "dr6:", save->dr6, "dr7:", save->dr7);
3128 pr_err("%-15s %016llx %-13s %016llx\n",
3129 "rip:", save->rip, "rflags:", save->rflags);
3130 pr_err("%-15s %016llx %-13s %016llx\n",
3131 "rsp:", save->rsp, "rax:", save->rax);
3132 pr_err("%-15s %016llx %-13s %016llx\n",
3133 "star:", save01->star, "lstar:", save01->lstar);
3134 pr_err("%-15s %016llx %-13s %016llx\n",
3135 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3136 pr_err("%-15s %016llx %-13s %016llx\n",
3137 "kernel_gs_base:", save01->kernel_gs_base,
3138 "sysenter_cs:", save01->sysenter_cs);
3139 pr_err("%-15s %016llx %-13s %016llx\n",
3140 "sysenter_esp:", save01->sysenter_esp,
3141 "sysenter_eip:", save01->sysenter_eip);
3142 pr_err("%-15s %016llx %-13s %016llx\n",
3143 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3144 pr_err("%-15s %016llx %-13s %016llx\n",
3145 "br_from:", save->br_from, "br_to:", save->br_to);
3146 pr_err("%-15s %016llx %-13s %016llx\n",
3147 "excp_from:", save->last_excp_from,
3148 "excp_to:", save->last_excp_to);
3151 static bool svm_check_exit_valid(u64 exit_code)
3153 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3154 svm_exit_handlers[exit_code]);
3157 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3159 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3161 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3162 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3163 vcpu->run->internal.ndata = 2;
3164 vcpu->run->internal.data[0] = exit_code;
3165 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3169 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3171 if (!svm_check_exit_valid(exit_code))
3172 return svm_handle_invalid_exit(vcpu, exit_code);
3174 #ifdef CONFIG_RETPOLINE
3175 if (exit_code == SVM_EXIT_MSR)
3176 return msr_interception(vcpu);
3177 else if (exit_code == SVM_EXIT_VINTR)
3178 return interrupt_window_interception(vcpu);
3179 else if (exit_code == SVM_EXIT_INTR)
3180 return intr_interception(vcpu);
3181 else if (exit_code == SVM_EXIT_HLT)
3182 return kvm_emulate_halt(vcpu);
3183 else if (exit_code == SVM_EXIT_NPF)
3184 return npf_interception(vcpu);
3186 return svm_exit_handlers[exit_code](vcpu);
3189 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3190 u64 *info1, u64 *info2,
3191 u32 *intr_info, u32 *error_code)
3193 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3195 *reason = control->exit_code;
3196 *info1 = control->exit_info_1;
3197 *info2 = control->exit_info_2;
3198 *intr_info = control->exit_int_info;
3199 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3200 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3201 *error_code = control->exit_int_info_err;
3206 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3208 struct vcpu_svm *svm = to_svm(vcpu);
3209 struct kvm_run *kvm_run = vcpu->run;
3210 u32 exit_code = svm->vmcb->control.exit_code;
3212 trace_kvm_exit(vcpu, KVM_ISA_SVM);
3214 /* SEV-ES guests must use the CR write traps to track CR registers. */
3215 if (!sev_es_guest(vcpu->kvm)) {
3216 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3217 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3219 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3222 if (is_guest_mode(vcpu)) {
3225 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3227 vmexit = nested_svm_exit_special(svm);
3229 if (vmexit == NESTED_EXIT_CONTINUE)
3230 vmexit = nested_svm_exit_handled(svm);
3232 if (vmexit == NESTED_EXIT_DONE)
3236 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3237 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3238 kvm_run->fail_entry.hardware_entry_failure_reason
3239 = svm->vmcb->control.exit_code;
3240 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3245 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3246 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3247 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3248 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3249 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3251 __func__, svm->vmcb->control.exit_int_info,
3254 if (exit_fastpath != EXIT_FASTPATH_NONE)
3257 return svm_invoke_exit_handler(vcpu, exit_code);
3260 static void reload_tss(struct kvm_vcpu *vcpu)
3262 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3264 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3268 static void pre_svm_run(struct kvm_vcpu *vcpu)
3270 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3271 struct vcpu_svm *svm = to_svm(vcpu);
3274 * If the previous vmrun of the vmcb occurred on a different physical
3275 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3276 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3278 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3279 svm->current_vmcb->asid_generation = 0;
3280 vmcb_mark_all_dirty(svm->vmcb);
3281 svm->current_vmcb->cpu = vcpu->cpu;
3284 if (sev_guest(vcpu->kvm))
3285 return pre_sev_run(svm, vcpu->cpu);
3287 /* FIXME: handle wraparound of asid_generation */
3288 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3292 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3294 struct vcpu_svm *svm = to_svm(vcpu);
3296 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3297 vcpu->arch.hflags |= HF_NMI_MASK;
3298 if (!sev_es_guest(vcpu->kvm))
3299 svm_set_intercept(svm, INTERCEPT_IRET);
3300 ++vcpu->stat.nmi_injections;
3303 static void svm_inject_irq(struct kvm_vcpu *vcpu)
3305 struct vcpu_svm *svm = to_svm(vcpu);
3307 BUG_ON(!(gif_set(svm)));
3309 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3310 ++vcpu->stat.irq_injections;
3312 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3313 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3316 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3317 int trig_mode, int vector)
3320 * vcpu->arch.apicv_active must be read after vcpu->mode.
3321 * Pairs with smp_store_release in vcpu_enter_guest.
3323 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3325 if (!READ_ONCE(vcpu->arch.apicv_active)) {
3326 /* Process the interrupt via inject_pending_event */
3327 kvm_make_request(KVM_REQ_EVENT, vcpu);
3328 kvm_vcpu_kick(vcpu);
3332 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3333 if (in_guest_mode) {
3335 * Signal the doorbell to tell hardware to inject the IRQ. If
3336 * the vCPU exits the guest before the doorbell chimes, hardware
3337 * will automatically process AVIC interrupts at the next VMRUN.
3339 avic_ring_doorbell(vcpu);
3342 * Wake the vCPU if it was blocking. KVM will then detect the
3343 * pending IRQ when checking if the vCPU has a wake event.
3345 kvm_vcpu_wake_up(vcpu);
3349 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3350 int trig_mode, int vector)
3352 kvm_lapic_set_irr(vector, apic);
3355 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3356 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3357 * the read of guest_mode. This guarantees that either VMRUN will see
3358 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3359 * will signal the doorbell if the CPU has already entered the guest.
3361 smp_mb__after_atomic();
3362 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3365 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3367 struct vcpu_svm *svm = to_svm(vcpu);
3370 * SEV-ES guests must always keep the CR intercepts cleared. CR
3371 * tracking is done using the CR write traps.
3373 if (sev_es_guest(vcpu->kvm))
3376 if (nested_svm_virtualize_tpr(vcpu))
3379 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3385 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3388 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3390 struct vcpu_svm *svm = to_svm(vcpu);
3391 struct vmcb *vmcb = svm->vmcb;
3397 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3400 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3401 (vcpu->arch.hflags & HF_NMI_MASK);
3406 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3408 struct vcpu_svm *svm = to_svm(vcpu);
3409 if (svm->nested.nested_run_pending)
3412 if (svm_nmi_blocked(vcpu))
3415 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3416 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3421 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3423 return !!(vcpu->arch.hflags & HF_NMI_MASK);
3426 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3428 struct vcpu_svm *svm = to_svm(vcpu);
3431 vcpu->arch.hflags |= HF_NMI_MASK;
3432 if (!sev_es_guest(vcpu->kvm))
3433 svm_set_intercept(svm, INTERCEPT_IRET);
3435 vcpu->arch.hflags &= ~HF_NMI_MASK;
3436 if (!sev_es_guest(vcpu->kvm))
3437 svm_clr_intercept(svm, INTERCEPT_IRET);
3441 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3443 struct vcpu_svm *svm = to_svm(vcpu);
3444 struct vmcb *vmcb = svm->vmcb;
3449 if (is_guest_mode(vcpu)) {
3450 /* As long as interrupts are being delivered... */
3451 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3452 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3453 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3456 /* ... vmexits aren't blocked by the interrupt shadow */
3457 if (nested_exit_on_intr(svm))
3460 if (!svm_get_if_flag(vcpu))
3464 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3467 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3469 struct vcpu_svm *svm = to_svm(vcpu);
3471 if (svm->nested.nested_run_pending)
3474 if (svm_interrupt_blocked(vcpu))
3478 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3479 * e.g. if the IRQ arrived asynchronously after checking nested events.
3481 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3487 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3489 struct vcpu_svm *svm = to_svm(vcpu);
3492 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3493 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3494 * get that intercept, this function will be called again though and
3495 * we'll get the vintr intercept. However, if the vGIF feature is
3496 * enabled, the STGI interception will not occur. Enable the irq
3497 * window under the assumption that the hardware will set the GIF.
3499 if (vgif_enabled(svm) || gif_set(svm)) {
3501 * IRQ window is not needed when AVIC is enabled,
3502 * unless we have pending ExtINT since it cannot be injected
3503 * via AVIC. In such case, we need to temporarily disable AVIC,
3504 * and fallback to injecting IRQ via V_IRQ.
3506 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3511 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3513 struct vcpu_svm *svm = to_svm(vcpu);
3515 if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3516 return; /* IRET will cause a vm exit */
3518 if (!gif_set(svm)) {
3519 if (vgif_enabled(svm))
3520 svm_set_intercept(svm, INTERCEPT_STGI);
3521 return; /* STGI will cause a vm exit */
3525 * Something prevents NMI from been injected. Single step over possible
3526 * problem (IRET or exception injection or interrupt shadow)
3528 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3529 svm->nmi_singlestep = true;
3530 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3533 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3535 struct vcpu_svm *svm = to_svm(vcpu);
3538 * Flush only the current ASID even if the TLB flush was invoked via
3539 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3540 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3541 * unconditionally does a TLB flush on both nested VM-Enter and nested
3542 * VM-Exit (via kvm_mmu_reset_context()).
3544 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3545 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3547 svm->current_vmcb->asid_generation--;
3550 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3552 struct vcpu_svm *svm = to_svm(vcpu);
3554 invlpga(gva, svm->vmcb->control.asid);
3557 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3559 struct vcpu_svm *svm = to_svm(vcpu);
3561 if (nested_svm_virtualize_tpr(vcpu))
3564 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3565 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3566 kvm_set_cr8(vcpu, cr8);
3570 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3572 struct vcpu_svm *svm = to_svm(vcpu);
3575 if (nested_svm_virtualize_tpr(vcpu) ||
3576 kvm_vcpu_apicv_active(vcpu))
3579 cr8 = kvm_get_cr8(vcpu);
3580 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3581 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3584 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3586 struct vcpu_svm *svm = to_svm(vcpu);
3589 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3590 unsigned int3_injected = svm->int3_injected;
3592 svm->int3_injected = 0;
3595 * If we've made progress since setting HF_IRET_MASK, we've
3596 * executed an IRET and can allow NMI injection.
3598 if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3599 (sev_es_guest(vcpu->kvm) ||
3600 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3601 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3602 kvm_make_request(KVM_REQ_EVENT, vcpu);
3605 vcpu->arch.nmi_injected = false;
3606 kvm_clear_exception_queue(vcpu);
3607 kvm_clear_interrupt_queue(vcpu);
3609 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3612 kvm_make_request(KVM_REQ_EVENT, vcpu);
3614 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3615 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3618 case SVM_EXITINTINFO_TYPE_NMI:
3619 vcpu->arch.nmi_injected = true;
3621 case SVM_EXITINTINFO_TYPE_EXEPT:
3623 * Never re-inject a #VC exception.
3625 if (vector == X86_TRAP_VC)
3629 * In case of software exceptions, do not reinject the vector,
3630 * but re-execute the instruction instead. Rewind RIP first
3631 * if we emulated INT3 before.
3633 if (kvm_exception_is_soft(vector)) {
3634 if (vector == BP_VECTOR && int3_injected &&
3635 kvm_is_linear_rip(vcpu, svm->int3_rip))
3637 kvm_rip_read(vcpu) - int3_injected);
3640 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3641 u32 err = svm->vmcb->control.exit_int_info_err;
3642 kvm_requeue_exception_e(vcpu, vector, err);
3645 kvm_requeue_exception(vcpu, vector);
3647 case SVM_EXITINTINFO_TYPE_INTR:
3648 kvm_queue_interrupt(vcpu, vector, false);
3655 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3657 struct vcpu_svm *svm = to_svm(vcpu);
3658 struct vmcb_control_area *control = &svm->vmcb->control;
3660 control->exit_int_info = control->event_inj;
3661 control->exit_int_info_err = control->event_inj_err;
3662 control->event_inj = 0;
3663 svm_complete_interrupts(vcpu);
3666 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
3671 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3673 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3674 to_svm(vcpu)->vmcb->control.exit_info_1)
3675 return handle_fastpath_set_msr_irqoff(vcpu);
3677 return EXIT_FASTPATH_NONE;
3680 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3682 struct vcpu_svm *svm = to_svm(vcpu);
3683 unsigned long vmcb_pa = svm->current_vmcb->pa;
3685 guest_state_enter_irqoff();
3687 if (sev_es_guest(vcpu->kvm)) {
3688 __svm_sev_es_vcpu_run(vmcb_pa);
3690 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3693 * Use a single vmcb (vmcb01 because it's always valid) for
3694 * context switching guest state via VMLOAD/VMSAVE, that way
3695 * the state doesn't need to be copied between vmcb01 and
3696 * vmcb02 when switching vmcbs for nested virtualization.
3698 vmload(svm->vmcb01.pa);
3699 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3700 vmsave(svm->vmcb01.pa);
3702 vmload(__sme_page_pa(sd->save_area));
3705 guest_state_exit_irqoff();
3708 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3710 struct vcpu_svm *svm = to_svm(vcpu);
3712 trace_kvm_entry(vcpu);
3714 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3715 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3716 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3719 * Disable singlestep if we're injecting an interrupt/exception.
3720 * We don't want our modified rflags to be pushed on the stack where
3721 * we might not be able to easily reset them if we disabled NMI
3724 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3726 * Event injection happens before external interrupts cause a
3727 * vmexit and interrupts are disabled here, so smp_send_reschedule
3728 * is enough to force an immediate vmexit.
3730 disable_nmi_singlestep(svm);
3731 smp_send_reschedule(vcpu->cpu);
3736 sync_lapic_to_cr8(vcpu);
3738 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3739 svm->vmcb->control.asid = svm->asid;
3740 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3742 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3744 svm_hv_update_vp_id(svm->vmcb, vcpu);
3747 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3750 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3751 svm_set_dr6(svm, vcpu->arch.dr6);
3753 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3756 kvm_load_guest_xsave_state(vcpu);
3758 kvm_wait_lapic_expire(vcpu);
3761 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3762 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3763 * is no need to worry about the conditional branch over the wrmsr
3764 * being speculatively taken.
3766 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3767 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3769 svm_vcpu_enter_exit(vcpu);
3772 * We do not use IBRS in the kernel. If this vCPU has used the
3773 * SPEC_CTRL MSR it may have left it on; save the value and
3774 * turn it off. This is much more efficient than blindly adding
3775 * it to the atomic save/restore list. Especially as the former
3776 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3778 * For non-nested case:
3779 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3783 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3786 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3787 unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3788 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3790 if (!sev_es_guest(vcpu->kvm))
3793 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3794 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3796 if (!sev_es_guest(vcpu->kvm)) {
3797 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3798 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3799 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3800 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3802 vcpu->arch.regs_dirty = 0;
3804 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3805 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
3807 kvm_load_host_xsave_state(vcpu);
3810 /* Any pending NMI will happen here */
3812 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3813 kvm_after_interrupt(vcpu);
3815 sync_cr8_to_lapic(vcpu);
3818 if (is_guest_mode(vcpu)) {
3819 nested_sync_control_from_vmcb02(svm);
3821 /* Track VMRUNs that have made past consistency checking */
3822 if (svm->nested.nested_run_pending &&
3823 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3824 ++vcpu->stat.nested_run;
3826 svm->nested.nested_run_pending = 0;
3829 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3830 vmcb_mark_all_clean(svm->vmcb);
3832 /* if exit due to PF check for async PF */
3833 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3834 vcpu->arch.apf.host_apf_flags =
3835 kvm_read_and_reset_apf_flags();
3837 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
3840 * We need to handle MC intercepts here before the vcpu has a chance to
3841 * change the physical cpu
3843 if (unlikely(svm->vmcb->control.exit_code ==
3844 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3845 svm_handle_mce(vcpu);
3847 svm_complete_interrupts(vcpu);
3849 if (is_guest_mode(vcpu))
3850 return EXIT_FASTPATH_NONE;
3852 return svm_exit_handlers_fastpath(vcpu);
3855 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3858 struct vcpu_svm *svm = to_svm(vcpu);
3862 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3863 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3865 hv_track_root_tdp(vcpu, root_hpa);
3867 cr3 = vcpu->arch.cr3;
3868 } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3869 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3871 /* PCID in the guest should be impossible with a 32-bit MMU. */
3872 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3876 svm->vmcb->save.cr3 = cr3;
3877 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3880 static int is_disabled(void)
3884 rdmsrl(MSR_VM_CR, vm_cr);
3885 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3892 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3895 * Patch in the VMMCALL instruction:
3897 hypercall[0] = 0x0f;
3898 hypercall[1] = 0x01;
3899 hypercall[2] = 0xd9;
3902 static int __init svm_check_processor_compat(void)
3908 * The kvm parameter can be NULL (module initialization, or invocation before
3909 * VM creation). Be sure to check the kvm parameter before using it.
3911 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3914 case MSR_IA32_MCG_EXT_CTL:
3915 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3917 case MSR_IA32_SMBASE:
3918 /* SEV-ES guests do not support SMM, so report false */
3919 if (kvm && sev_es_guest(kvm))
3929 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3934 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3936 struct vcpu_svm *svm = to_svm(vcpu);
3937 struct kvm_cpuid_entry2 *best;
3938 struct kvm *kvm = vcpu->kvm;
3940 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3941 boot_cpu_has(X86_FEATURE_XSAVE) &&
3942 boot_cpu_has(X86_FEATURE_XSAVES);
3944 /* Update nrips enabled cache */
3945 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3946 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
3948 svm->tsc_scaling_enabled = tsc_scaling && guest_cpuid_has(vcpu, X86_FEATURE_TSCRATEMSR);
3950 svm_recalc_instruction_intercepts(vcpu, svm);
3952 /* For sev guests, the memory encryption bit is not reserved in CR3. */
3953 if (sev_guest(vcpu->kvm)) {
3954 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3956 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
3959 if (kvm_vcpu_apicv_active(vcpu)) {
3961 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3962 * is exposed to the guest, disable AVIC.
3964 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3965 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_X2APIC);
3968 * Currently, AVIC does not work with nested virtualization.
3969 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3971 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3972 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_NESTED);
3974 init_vmcb_after_set_cpuid(vcpu);
3977 static bool svm_has_wbinvd_exit(void)
3982 #define PRE_EX(exit) { .exit_code = (exit), \
3983 .stage = X86_ICPT_PRE_EXCEPT, }
3984 #define POST_EX(exit) { .exit_code = (exit), \
3985 .stage = X86_ICPT_POST_EXCEPT, }
3986 #define POST_MEM(exit) { .exit_code = (exit), \
3987 .stage = X86_ICPT_POST_MEMACCESS, }
3989 static const struct __x86_intercept {
3991 enum x86_intercept_stage stage;
3992 } x86_intercept_map[] = {
3993 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3994 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3995 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3996 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3997 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3998 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3999 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4000 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4001 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4002 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4003 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4004 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4005 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4006 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4007 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4008 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4009 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4010 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4011 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4012 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4013 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4014 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4015 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4016 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4017 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4018 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4019 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4020 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4021 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4022 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4023 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4024 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4025 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4026 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4027 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4028 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4029 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4030 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4031 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4032 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4033 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4034 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4035 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4036 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4037 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4038 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4039 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4046 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4047 struct x86_instruction_info *info,
4048 enum x86_intercept_stage stage,
4049 struct x86_exception *exception)
4051 struct vcpu_svm *svm = to_svm(vcpu);
4052 int vmexit, ret = X86EMUL_CONTINUE;
4053 struct __x86_intercept icpt_info;
4054 struct vmcb *vmcb = svm->vmcb;
4056 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4059 icpt_info = x86_intercept_map[info->intercept];
4061 if (stage != icpt_info.stage)
4064 switch (icpt_info.exit_code) {
4065 case SVM_EXIT_READ_CR0:
4066 if (info->intercept == x86_intercept_cr_read)
4067 icpt_info.exit_code += info->modrm_reg;
4069 case SVM_EXIT_WRITE_CR0: {
4070 unsigned long cr0, val;
4072 if (info->intercept == x86_intercept_cr_write)
4073 icpt_info.exit_code += info->modrm_reg;
4075 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4076 info->intercept == x86_intercept_clts)
4079 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4080 INTERCEPT_SELECTIVE_CR0)))
4083 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4084 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4086 if (info->intercept == x86_intercept_lmsw) {
4089 /* lmsw can't clear PE - catch this here */
4090 if (cr0 & X86_CR0_PE)
4095 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4099 case SVM_EXIT_READ_DR0:
4100 case SVM_EXIT_WRITE_DR0:
4101 icpt_info.exit_code += info->modrm_reg;
4104 if (info->intercept == x86_intercept_wrmsr)
4105 vmcb->control.exit_info_1 = 1;
4107 vmcb->control.exit_info_1 = 0;
4109 case SVM_EXIT_PAUSE:
4111 * We get this for NOP only, but pause
4112 * is rep not, check this here
4114 if (info->rep_prefix != REPE_PREFIX)
4117 case SVM_EXIT_IOIO: {
4121 if (info->intercept == x86_intercept_in ||
4122 info->intercept == x86_intercept_ins) {
4123 exit_info = ((info->src_val & 0xffff) << 16) |
4125 bytes = info->dst_bytes;
4127 exit_info = (info->dst_val & 0xffff) << 16;
4128 bytes = info->src_bytes;
4131 if (info->intercept == x86_intercept_outs ||
4132 info->intercept == x86_intercept_ins)
4133 exit_info |= SVM_IOIO_STR_MASK;
4135 if (info->rep_prefix)
4136 exit_info |= SVM_IOIO_REP_MASK;
4138 bytes = min(bytes, 4u);
4140 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4142 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4144 vmcb->control.exit_info_1 = exit_info;
4145 vmcb->control.exit_info_2 = info->next_rip;
4153 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4154 if (static_cpu_has(X86_FEATURE_NRIPS))
4155 vmcb->control.next_rip = info->next_rip;
4156 vmcb->control.exit_code = icpt_info.exit_code;
4157 vmexit = nested_svm_exit_handled(svm);
4159 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4166 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4170 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4172 if (!kvm_pause_in_guest(vcpu->kvm))
4173 shrink_ple_window(vcpu);
4176 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4178 /* [63:9] are reserved. */
4179 vcpu->arch.mcg_cap &= 0x1ff;
4182 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4184 struct vcpu_svm *svm = to_svm(vcpu);
4186 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4190 return is_smm(vcpu);
4193 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4195 struct vcpu_svm *svm = to_svm(vcpu);
4196 if (svm->nested.nested_run_pending)
4199 if (svm_smi_blocked(vcpu))
4202 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4203 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4209 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4211 struct vcpu_svm *svm = to_svm(vcpu);
4212 struct kvm_host_map map_save;
4215 if (!is_guest_mode(vcpu))
4218 /* FED8h - SVM Guest */
4219 put_smstate(u64, smstate, 0x7ed8, 1);
4220 /* FEE0h - SVM Guest VMCB Physical Address */
4221 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4223 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4224 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4225 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4227 ret = nested_svm_vmexit(svm);
4232 * KVM uses VMCB01 to store L1 host state while L2 runs but
4233 * VMCB01 is going to be used during SMM and thus the state will
4234 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4235 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4236 * format of the area is identical to guest save area offsetted
4237 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4238 * within 'struct vmcb'). Note: HSAVE area may also be used by
4239 * L1 hypervisor to save additional host context (e.g. KVM does
4240 * that, see svm_prepare_switch_to_guest()) which must be
4243 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4244 &map_save) == -EINVAL)
4247 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4249 svm_copy_vmrun_state(map_save.hva + 0x400,
4250 &svm->vmcb01.ptr->save);
4252 kvm_vcpu_unmap(vcpu, &map_save, true);
4256 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4258 struct vcpu_svm *svm = to_svm(vcpu);
4259 struct kvm_host_map map, map_save;
4260 u64 saved_efer, vmcb12_gpa;
4261 struct vmcb *vmcb12;
4264 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4267 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4268 if (!GET_SMSTATE(u64, smstate, 0x7ed8))
4271 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4274 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4275 if (!(saved_efer & EFER_SVME))
4278 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4279 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4283 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save) == -EINVAL)
4286 if (svm_allocate_nested(svm))
4290 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4291 * used during SMM (see svm_enter_smm())
4294 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4297 * Enter the nested guest now
4300 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4303 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4304 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4305 ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12, false);
4310 svm->nested.nested_run_pending = 1;
4313 kvm_vcpu_unmap(vcpu, &map_save, true);
4315 kvm_vcpu_unmap(vcpu, &map, true);
4319 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4321 struct vcpu_svm *svm = to_svm(vcpu);
4323 if (!gif_set(svm)) {
4324 if (vgif_enabled(svm))
4325 svm_set_intercept(svm, INTERCEPT_STGI);
4326 /* STGI will cause a vm exit */
4328 /* We must be in SMM; RSM will cause a vmexit anyway. */
4332 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4333 void *insn, int insn_len)
4335 bool smep, smap, is_user;
4339 /* Emulation is always possible when KVM has access to all guest state. */
4340 if (!sev_guest(vcpu->kvm))
4343 /* #UD and #GP should never be intercepted for SEV guests. */
4344 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4345 EMULTYPE_TRAP_UD_FORCED |
4346 EMULTYPE_VMWARE_GP));
4349 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4350 * to guest register state.
4352 if (sev_es_guest(vcpu->kvm))
4356 * Emulation is possible if the instruction is already decoded, e.g.
4357 * when completing I/O after returning from userspace.
4359 if (emul_type & EMULTYPE_NO_DECODE)
4363 * Emulation is possible for SEV guests if and only if a prefilled
4364 * buffer containing the bytes of the intercepted instruction is
4365 * available. SEV guest memory is encrypted with a guest specific key
4366 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4369 * Inject #UD if KVM reached this point without an instruction buffer.
4370 * In practice, this path should never be hit by a well-behaved guest,
4371 * e.g. KVM doesn't intercept #UD or #GP for SEV guests, but this path
4372 * is still theoretically reachable, e.g. via unaccelerated fault-like
4373 * AVIC access, and needs to be handled by KVM to avoid putting the
4374 * guest into an infinite loop. Injecting #UD is somewhat arbitrary,
4375 * but its the least awful option given lack of insight into the guest.
4377 if (unlikely(!insn)) {
4378 kvm_queue_exception(vcpu, UD_VECTOR);
4383 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4384 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4385 * the faulting instruction because the code fetch itself faulted, e.g.
4386 * the guest attempted to fetch from emulated MMIO or a guest page
4387 * table used to translate CS:RIP resides in emulated MMIO.
4389 if (likely(insn_len))
4393 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4396 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4397 * possible that CPU microcode implementing DecodeAssist will fail to
4398 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4399 * be '0'. This happens because microcode reads CS:RIP using a _data_
4400 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4401 * gives up and does not fill the instruction bytes buffer.
4403 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4404 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4405 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4406 * GuestIntrBytes field of the VMCB.
4408 * This does _not_ mean that the erratum has been encountered, as the
4409 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4410 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4411 * encountered a reserved/not-present #PF.
4413 * To hit the erratum, the following conditions must be true:
4414 * 1. CR4.SMAP=1 (obviously).
4415 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4416 * have been hit as the guest would have encountered a SMEP
4417 * violation #PF, not a #NPF.
4418 * 3. The #NPF is not due to a code fetch, in which case failure to
4419 * retrieve the instruction bytes is legitimate (see abvoe).
4421 * In addition, don't apply the erratum workaround if the #NPF occurred
4422 * while translating guest page tables (see below).
4424 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4425 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4428 cr4 = kvm_read_cr4(vcpu);
4429 smep = cr4 & X86_CR4_SMEP;
4430 smap = cr4 & X86_CR4_SMAP;
4431 is_user = svm_get_cpl(vcpu) == 3;
4432 if (smap && (!smep || is_user)) {
4433 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4436 * If the fault occurred in userspace, arbitrarily inject #GP
4437 * to avoid killing the guest and to hopefully avoid confusing
4438 * the guest kernel too much, e.g. injecting #PF would not be
4439 * coherent with respect to the guest's page tables. Request
4440 * triple fault if the fault occurred in the kernel as there's
4441 * no fault that KVM can inject without confusing the guest.
4442 * In practice, the triple fault is moot as no sane SEV kernel
4443 * will execute from user memory while also running with SMAP=1.
4446 kvm_inject_gp(vcpu, 0);
4448 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4453 * If the erratum was not hit, simply resume the guest and let it fault
4454 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4455 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4456 * userspace will kill the guest, and letting the emulator read garbage
4457 * will yield random behavior and potentially corrupt the guest.
4459 * Simply resuming the guest is technically not a violation of the SEV
4460 * architecture. AMD's APM states that all code fetches and page table
4461 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4462 * APM also states that encrypted accesses to MMIO are "ignored", but
4463 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4464 * the guest spin is technically "ignoring" the access.
4469 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4471 struct vcpu_svm *svm = to_svm(vcpu);
4474 * TODO: Last condition latch INIT signals on vCPU when
4475 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4476 * To properly emulate the INIT intercept,
4477 * svm_check_nested_events() should call nested_svm_vmexit()
4478 * if an INIT signal is pending.
4480 return !gif_set(svm) ||
4481 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4484 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4486 if (!sev_es_guest(vcpu->kvm))
4487 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4489 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4492 static void svm_vm_destroy(struct kvm *kvm)
4494 avic_vm_destroy(kvm);
4495 sev_vm_destroy(kvm);
4498 static int svm_vm_init(struct kvm *kvm)
4500 if (!pause_filter_count || !pause_filter_thresh)
4501 kvm->arch.pause_in_guest = true;
4504 int ret = avic_vm_init(kvm);
4512 static struct kvm_x86_ops svm_x86_ops __initdata = {
4515 .hardware_unsetup = svm_hardware_unsetup,
4516 .hardware_enable = svm_hardware_enable,
4517 .hardware_disable = svm_hardware_disable,
4518 .has_emulated_msr = svm_has_emulated_msr,
4520 .vcpu_create = svm_vcpu_create,
4521 .vcpu_free = svm_vcpu_free,
4522 .vcpu_reset = svm_vcpu_reset,
4524 .vm_size = sizeof(struct kvm_svm),
4525 .vm_init = svm_vm_init,
4526 .vm_destroy = svm_vm_destroy,
4528 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4529 .vcpu_load = svm_vcpu_load,
4530 .vcpu_put = svm_vcpu_put,
4531 .vcpu_blocking = avic_vcpu_blocking,
4532 .vcpu_unblocking = avic_vcpu_unblocking,
4534 .update_exception_bitmap = svm_update_exception_bitmap,
4535 .get_msr_feature = svm_get_msr_feature,
4536 .get_msr = svm_get_msr,
4537 .set_msr = svm_set_msr,
4538 .get_segment_base = svm_get_segment_base,
4539 .get_segment = svm_get_segment,
4540 .set_segment = svm_set_segment,
4541 .get_cpl = svm_get_cpl,
4542 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4543 .set_cr0 = svm_set_cr0,
4544 .post_set_cr3 = sev_post_set_cr3,
4545 .is_valid_cr4 = svm_is_valid_cr4,
4546 .set_cr4 = svm_set_cr4,
4547 .set_efer = svm_set_efer,
4548 .get_idt = svm_get_idt,
4549 .set_idt = svm_set_idt,
4550 .get_gdt = svm_get_gdt,
4551 .set_gdt = svm_set_gdt,
4552 .set_dr7 = svm_set_dr7,
4553 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4554 .cache_reg = svm_cache_reg,
4555 .get_rflags = svm_get_rflags,
4556 .set_rflags = svm_set_rflags,
4557 .get_if_flag = svm_get_if_flag,
4559 .flush_tlb_all = svm_flush_tlb_current,
4560 .flush_tlb_current = svm_flush_tlb_current,
4561 .flush_tlb_gva = svm_flush_tlb_gva,
4562 .flush_tlb_guest = svm_flush_tlb_current,
4564 .vcpu_pre_run = svm_vcpu_pre_run,
4565 .vcpu_run = svm_vcpu_run,
4566 .handle_exit = svm_handle_exit,
4567 .skip_emulated_instruction = svm_skip_emulated_instruction,
4568 .update_emulated_instruction = NULL,
4569 .set_interrupt_shadow = svm_set_interrupt_shadow,
4570 .get_interrupt_shadow = svm_get_interrupt_shadow,
4571 .patch_hypercall = svm_patch_hypercall,
4572 .inject_irq = svm_inject_irq,
4573 .inject_nmi = svm_inject_nmi,
4574 .queue_exception = svm_queue_exception,
4575 .cancel_injection = svm_cancel_injection,
4576 .interrupt_allowed = svm_interrupt_allowed,
4577 .nmi_allowed = svm_nmi_allowed,
4578 .get_nmi_mask = svm_get_nmi_mask,
4579 .set_nmi_mask = svm_set_nmi_mask,
4580 .enable_nmi_window = svm_enable_nmi_window,
4581 .enable_irq_window = svm_enable_irq_window,
4582 .update_cr8_intercept = svm_update_cr8_intercept,
4583 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4584 .check_apicv_inhibit_reasons = avic_check_apicv_inhibit_reasons,
4585 .apicv_post_state_restore = avic_apicv_post_state_restore,
4587 .get_mt_mask = svm_get_mt_mask,
4588 .get_exit_info = svm_get_exit_info,
4590 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4592 .has_wbinvd_exit = svm_has_wbinvd_exit,
4594 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4595 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4596 .write_tsc_offset = svm_write_tsc_offset,
4597 .write_tsc_multiplier = svm_write_tsc_multiplier,
4599 .load_mmu_pgd = svm_load_mmu_pgd,
4601 .check_intercept = svm_check_intercept,
4602 .handle_exit_irqoff = svm_handle_exit_irqoff,
4604 .request_immediate_exit = __kvm_request_immediate_exit,
4606 .sched_in = svm_sched_in,
4608 .pmu_ops = &amd_pmu_ops,
4609 .nested_ops = &svm_nested_ops,
4611 .deliver_interrupt = svm_deliver_interrupt,
4612 .pi_update_irte = avic_pi_update_irte,
4613 .setup_mce = svm_setup_mce,
4615 .smi_allowed = svm_smi_allowed,
4616 .enter_smm = svm_enter_smm,
4617 .leave_smm = svm_leave_smm,
4618 .enable_smi_window = svm_enable_smi_window,
4620 .mem_enc_ioctl = sev_mem_enc_ioctl,
4621 .mem_enc_register_region = sev_mem_enc_register_region,
4622 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
4624 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
4625 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
4627 .can_emulate_instruction = svm_can_emulate_instruction,
4629 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4631 .msr_filter_changed = svm_msr_filter_changed,
4632 .complete_emulated_msr = svm_complete_emulated_msr,
4634 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4638 * The default MMIO mask is a single bit (excluding the present bit),
4639 * which could conflict with the memory encryption bit. Check for
4640 * memory encryption support and override the default MMIO mask if
4641 * memory encryption is enabled.
4643 static __init void svm_adjust_mmio_mask(void)
4645 unsigned int enc_bit, mask_bit;
4648 /* If there is no memory encryption support, use existing mask */
4649 if (cpuid_eax(0x80000000) < 0x8000001f)
4652 /* If memory encryption is not enabled, use existing mask */
4653 rdmsrl(MSR_AMD64_SYSCFG, msr);
4654 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
4657 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
4658 mask_bit = boot_cpu_data.x86_phys_bits;
4660 /* Increment the mask bit if it is the same as the encryption bit */
4661 if (enc_bit == mask_bit)
4665 * If the mask bit location is below 52, then some bits above the
4666 * physical addressing limit will always be reserved, so use the
4667 * rsvd_bits() function to generate the mask. This mask, along with
4668 * the present bit, will be used to generate a page fault with
4671 * If the mask bit location is 52 (or above), then clear the mask.
4673 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
4675 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
4678 static __init void svm_set_cpu_caps(void)
4684 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
4686 kvm_cpu_cap_set(X86_FEATURE_SVM);
4687 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
4690 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
4693 kvm_cpu_cap_set(X86_FEATURE_NPT);
4696 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
4698 /* Nested VM can receive #VMEXIT instead of triggering #GP */
4699 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
4702 /* CPUID 0x80000008 */
4703 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
4704 boot_cpu_has(X86_FEATURE_AMD_SSBD))
4705 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4707 /* AMD PMU PERFCTR_CORE CPUID */
4708 if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
4709 kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);
4711 /* CPUID 0x8000001F (SME/SEV features) */
4715 static __init int svm_hardware_setup(void)
4718 struct page *iopm_pages;
4721 unsigned int order = get_order(IOPM_SIZE);
4724 * NX is required for shadow paging and for NPT if the NX huge pages
4725 * mitigation is enabled.
4727 if (!boot_cpu_has(X86_FEATURE_NX)) {
4728 pr_err_ratelimited("NX (Execute Disable) not supported\n");
4731 kvm_enable_efer_bits(EFER_NX);
4733 iopm_pages = alloc_pages(GFP_KERNEL, order);
4738 iopm_va = page_address(iopm_pages);
4739 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
4740 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
4742 init_msrpm_offsets();
4744 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
4746 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
4747 kvm_enable_efer_bits(EFER_FFXSR);
4750 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
4751 tsc_scaling = false;
4753 pr_info("TSC scaling supported\n");
4754 kvm_has_tsc_control = true;
4757 kvm_max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
4758 kvm_tsc_scaling_ratio_frac_bits = 32;
4760 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
4762 /* Check for pause filtering support */
4763 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
4764 pause_filter_count = 0;
4765 pause_filter_thresh = 0;
4766 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
4767 pause_filter_thresh = 0;
4771 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
4772 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
4776 * KVM's MMU doesn't support using 2-level paging for itself, and thus
4777 * NPT isn't supported if the host is using 2-level paging since host
4778 * CR4 is unchanged on VMRUN.
4780 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
4781 npt_enabled = false;
4783 if (!boot_cpu_has(X86_FEATURE_NPT))
4784 npt_enabled = false;
4786 /* Force VM NPT level equal to the host's paging level */
4787 kvm_configure_mmu(npt_enabled, get_npt_level(),
4788 get_npt_level(), PG_LEVEL_1G);
4789 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
4791 /* Note, SEV setup consumes npt_enabled. */
4792 sev_hardware_setup();
4794 svm_hv_hardware_setup();
4796 svm_adjust_mmio_mask();
4798 for_each_possible_cpu(cpu) {
4799 r = svm_cpu_init(cpu);
4805 if (!boot_cpu_has(X86_FEATURE_NRIPS))
4809 enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC);
4812 pr_info("AVIC enabled\n");
4814 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
4816 svm_x86_ops.vcpu_blocking = NULL;
4817 svm_x86_ops.vcpu_unblocking = NULL;
4822 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
4823 !IS_ENABLED(CONFIG_X86_64)) {
4826 pr_info("Virtual VMLOAD VMSAVE supported\n");
4830 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
4831 svm_gp_erratum_intercept = false;
4834 if (!boot_cpu_has(X86_FEATURE_VGIF))
4837 pr_info("Virtual GIF supported\n");
4841 if (!boot_cpu_has(X86_FEATURE_LBRV))
4844 pr_info("LBR virtualization supported\n");
4848 pr_info("PMU virtualization is disabled\n");
4853 * It seems that on AMD processors PTE's accessed bit is
4854 * being set by the CPU hardware before the NPF vmexit.
4855 * This is not expected behaviour and our tests fail because
4857 * A workaround here is to disable support for
4858 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
4859 * In this case userspace can know if there is support using
4860 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
4862 * If future AMD CPU models change the behaviour described above,
4863 * this variable can be changed accordingly
4865 allow_smaller_maxphyaddr = !npt_enabled;
4870 svm_hardware_unsetup();
4875 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4876 .cpu_has_kvm_support = has_svm,
4877 .disabled_by_bios = is_disabled,
4878 .hardware_setup = svm_hardware_setup,
4879 .check_processor_compatibility = svm_check_processor_compat,
4881 .runtime_ops = &svm_x86_ops,
4884 static int __init svm_init(void)
4886 __unused_size_checks();
4888 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4889 __alignof__(struct vcpu_svm), THIS_MODULE);
4892 static void __exit svm_exit(void)
4897 module_init(svm_init)
4898 module_exit(svm_exit)