arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #include "kvm_onhyperv.h"
  47 #include "svm_onhyperv.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 #ifdef MODULE
  55 static const struct x86_cpu_id svm_cpu_id[] = {
  56         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  60 #endif
  61
  62 #define SEG_TYPE_LDT 2
  63 #define SEG_TYPE_BUSY_TSS16 3
  64
  65 #define SVM_FEATURE_LBRV           (1 <<  1)
  66 #define SVM_FEATURE_SVML           (1 <<  2)
  67 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  68 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  69 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  70 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  71 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  82
  83 /*
  84  * Set osvw_len to higher value when updated Revision Guides
  85  * are published and we know what the new status bits are
  86  */
  87 static uint64_t osvw_len = 4, osvw_status;
  88
  89 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  90 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  91
  92 static const struct svm_direct_access_msrs {
  93         u32 index;   /* Index of the MSR */
  94         bool always; /* True if intercept is initially cleared */
  95 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  96         { .index = MSR_STAR,                            .always = true  },
  97         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  98         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  99         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
 100 #ifdef CONFIG_X86_64
 101         { .index = MSR_GS_BASE,                         .always = true  },
 102         { .index = MSR_FS_BASE,                         .always = true  },
 103         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 104         { .index = MSR_LSTAR,                           .always = true  },
 105         { .index = MSR_CSTAR,                           .always = true  },
 106         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 107 #endif
 108         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 109         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 110         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 111         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 112         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 113         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 114         { .index = MSR_EFER,                            .always = false },
 115         { .index = MSR_IA32_CR_PAT,                     .always = false },
 116         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 117         { .index = MSR_INVALID,                         .always = false },
 118 };
 119
 120 /*
 121  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 122  * pause_filter_count: On processors that support Pause filtering(indicated
 123  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 124  *      count value. On VMRUN this value is loaded into an internal counter.
 125  *      Each time a pause instruction is executed, this counter is decremented
 126  *      until it reaches zero at which time a #VMEXIT is generated if pause
 127  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 128  *      Intercept Filtering for more details.
 129  *      This also indicate if ple logic enabled.
 130  *
 131  * pause_filter_thresh: In addition, some processor families support advanced
 132  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 133  *      the amount of time a guest is allowed to execute in a pause loop.
 134  *      In this mode, a 16-bit pause filter threshold field is added in the
 135  *      VMCB. The threshold value is a cycle count that is used to reset the
 136  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 137  *      count value from VMCB into an internal counter. Then, on each pause
 138  *      instruction the hardware checks the elapsed number of cycles since
 139  *      the most recent pause instruction against the pause filter threshold.
 140  *      If the elapsed cycle count is greater than the pause filter threshold,
 141  *      then the internal pause count is reloaded from the VMCB and execution
 142  *      continues. If the elapsed cycle count is less than the pause filter
 143  *      threshold, then the internal pause count is decremented. If the count
 144  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 145  *      triggered. If advanced pause filtering is supported and pause filter
 146  *      threshold field is set to zero, the filter will operate in the simpler,
 147  *      count only mode.
 148  */
 149
 150 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 151 module_param(pause_filter_thresh, ushort, 0444);
 152
 153 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 154 module_param(pause_filter_count, ushort, 0444);
 155
 156 /* Default doubles per-vcpu window every exit. */
 157 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 158 module_param(pause_filter_count_grow, ushort, 0444);
 159
 160 /* Default resets per-vcpu window every exit to pause_filter_count. */
 161 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 162 module_param(pause_filter_count_shrink, ushort, 0444);
 163
 164 /* Default is to compute the maximum so we can never overflow. */
 165 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 166 module_param(pause_filter_count_max, ushort, 0444);
 167
 168 /*
 169  * Use nested page tables by default.  Note, NPT may get forced off by
 170  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 171  */
 172 bool npt_enabled = true;
 173 module_param_named(npt, npt_enabled, bool, 0444);
 174
 175 /* allow nested virtualization in KVM/SVM */
 176 static int nested = true;
 177 module_param(nested, int, S_IRUGO);
 178
 179 /* enable/disable Next RIP Save */
 180 static int nrips = true;
 181 module_param(nrips, int, 0444);
 182
 183 /* enable/disable Virtual VMLOAD VMSAVE */
 184 static int vls = true;
 185 module_param(vls, int, 0444);
 186
 187 /* enable/disable Virtual GIF */
 188 static int vgif = true;
 189 module_param(vgif, int, 0444);
 190
 191 /*
 192  * enable / disable AVIC.  Because the defaults differ for APICv
 193  * support between VMX and SVM we cannot use module_param_named.
 194  */
 195 static bool avic;
 196 module_param(avic, bool, 0444);
 197
 198 bool __read_mostly dump_invalid_vmcb;
 199 module_param(dump_invalid_vmcb, bool, 0644);
 200
 201 static bool svm_gp_erratum_intercept = true;
 202
 203 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 204
 205 static unsigned long iopm_base;
 206
 207 struct kvm_ldttss_desc {
 208         u16 limit0;
 209         u16 base0;
 210         unsigned base1:8, type:5, dpl:2, p:1;
 211         unsigned limit1:4, zero0:3, g:1, base2:8;
 212         u32 base3;
 213         u32 zero1;
 214 } __attribute__((packed));
 215
 216 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 217
 218 /*
 219  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 220  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 221  *
 222  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 223  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 224  */
 225 static int tsc_aux_uret_slot __read_mostly = -1;
 226
 227 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 228
 229 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 230 #define MSRS_RANGE_SIZE 2048
 231 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 232
 233 u32 svm_msrpm_offset(u32 msr)
 234 {
 235         u32 offset;
 236         int i;
 237
 238         for (i = 0; i < NUM_MSR_MAPS; i++) {
 239                 if (msr < msrpm_ranges[i] ||
 240                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 241                         continue;
 242
 243                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 244                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 245
 246                 /* Now we have the u8 offset - but need the u32 offset */
 247                 return offset / 4;
 248         }
 249
 250         /* MSR not in any range */
 251         return MSR_INVALID;
 252 }
 253
 254 #define MAX_INST_SIZE 15
 255
 256 static int get_max_npt_level(void)
 257 {
 258 #ifdef CONFIG_X86_64
 259         return PT64_ROOT_4LEVEL;
 260 #else
 261         return PT32E_ROOT_LEVEL;
 262 #endif
 263 }
 264
 265 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 266 {
 267         struct vcpu_svm *svm = to_svm(vcpu);
 268         u64 old_efer = vcpu->arch.efer;
 269         vcpu->arch.efer = efer;
 270
 271         if (!npt_enabled) {
 272                 /* Shadow paging assumes NX to be available.  */
 273                 efer |= EFER_NX;
 274
 275                 if (!(efer & EFER_LMA))
 276                         efer &= ~EFER_LME;
 277         }
 278
 279         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 280                 if (!(efer & EFER_SVME)) {
 281                         svm_leave_nested(svm);
 282                         svm_set_gif(svm, true);
 283                         /* #GP intercept is still needed for vmware backdoor */
 284                         if (!enable_vmware_backdoor)
 285                                 clr_exception_intercept(svm, GP_VECTOR);
 286
 287                         /*
 288                          * Free the nested guest state, unless we are in SMM.
 289                          * In this case we will return to the nested guest
 290                          * as soon as we leave SMM.
 291                          */
 292                         if (!is_smm(vcpu))
 293                                 svm_free_nested(svm);
 294
 295                 } else {
 296                         int ret = svm_allocate_nested(svm);
 297
 298                         if (ret) {
 299                                 vcpu->arch.efer = old_efer;
 300                                 return ret;
 301                         }
 302
 303                         if (svm_gp_erratum_intercept)
 304                                 set_exception_intercept(svm, GP_VECTOR);
 305                 }
 306         }
 307
 308         svm->vmcb->save.efer = efer | EFER_SVME;
 309         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 310         return 0;
 311 }
 312
 313 static int is_external_interrupt(u32 info)
 314 {
 315         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 316         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 317 }
 318
 319 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322         u32 ret = 0;
 323
 324         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 325                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 326         return ret;
 327 }
 328
 329 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 330 {
 331         struct vcpu_svm *svm = to_svm(vcpu);
 332
 333         if (mask == 0)
 334                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 335         else
 336                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 337
 338 }
 339
 340 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 341 {
 342         struct vcpu_svm *svm = to_svm(vcpu);
 343
 344         /*
 345          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 346          * the type of exit and the #VC handler in the guest.
 347          */
 348         if (sev_es_guest(vcpu->kvm))
 349                 goto done;
 350
 351         if (nrips && svm->vmcb->control.next_rip != 0) {
 352                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 353                 svm->next_rip = svm->vmcb->control.next_rip;
 354         }
 355
 356         if (!svm->next_rip) {
 357                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 358                         return 0;
 359         } else {
 360                 kvm_rip_write(vcpu, svm->next_rip);
 361         }
 362
 363 done:
 364         svm_set_interrupt_shadow(vcpu, 0);
 365
 366         return 1;
 367 }
 368
 369 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 370 {
 371         struct vcpu_svm *svm = to_svm(vcpu);
 372         unsigned nr = vcpu->arch.exception.nr;
 373         bool has_error_code = vcpu->arch.exception.has_error_code;
 374         u32 error_code = vcpu->arch.exception.error_code;
 375
 376         kvm_deliver_exception_payload(vcpu);
 377
 378         if (nr == BP_VECTOR && !nrips) {
 379                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 380
 381                 /*
 382                  * For guest debugging where we have to reinject #BP if some
 383                  * INT3 is guest-owned:
 384                  * Emulate nRIP by moving RIP forward. Will fail if injection
 385                  * raises a fault that is not intercepted. Still better than
 386                  * failing in all cases.
 387                  */
 388                 (void)skip_emulated_instruction(vcpu);
 389                 rip = kvm_rip_read(vcpu);
 390                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 391                 svm->int3_injected = rip - old_rip;
 392         }
 393
 394         svm->vmcb->control.event_inj = nr
 395                 | SVM_EVTINJ_VALID
 396                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 397                 | SVM_EVTINJ_TYPE_EXEPT;
 398         svm->vmcb->control.event_inj_err = error_code;
 399 }
 400
 401 static void svm_init_erratum_383(void)
 402 {
 403         u32 low, high;
 404         int err;
 405         u64 val;
 406
 407         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 408                 return;
 409
 410         /* Use _safe variants to not break nested virtualization */
 411         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 412         if (err)
 413                 return;
 414
 415         val |= (1ULL << 47);
 416
 417         low  = lower_32_bits(val);
 418         high = upper_32_bits(val);
 419
 420         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 421
 422         erratum_383_found = true;
 423 }
 424
 425 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 426 {
 427         /*
 428          * Guests should see errata 400 and 415 as fixed (assuming that
 429          * HLT and IO instructions are intercepted).
 430          */
 431         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 432         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 433
 434         /*
 435          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 436          * all osvw.status bits inside that length, including bit 0 (which is
 437          * reserved for erratum 298), are valid. However, if host processor's
 438          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 439          * be conservative here and therefore we tell the guest that erratum 298
 440          * is present (because we really don't know).
 441          */
 442         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 443                 vcpu->arch.osvw.status |= 1;
 444 }
 445
 446 static int has_svm(void)
 447 {
 448         const char *msg;
 449
 450         if (!cpu_has_svm(&msg)) {
 451                 printk(KERN_INFO "has_svm: %s\n", msg);
 452                 return 0;
 453         }
 454
 455         if (sev_active()) {
 456                 pr_info("KVM is unsupported when running as an SEV guest\n");
 457                 return 0;
 458         }
 459
 460         if (pgtable_l5_enabled()) {
 461                 pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
 462                 return 0;
 463         }
 464
 465         return 1;
 466 }
 467
 468 static void svm_hardware_disable(void)
 469 {
 470         /* Make sure we clean up behind us */
 471         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 472                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 473
 474         cpu_svm_disable();
 475
 476         amd_pmu_disable_virt();
 477 }
 478
 479 static int svm_hardware_enable(void)
 480 {
 481
 482         struct svm_cpu_data *sd;
 483         uint64_t efer;
 484         struct desc_struct *gdt;
 485         int me = raw_smp_processor_id();
 486
 487         rdmsrl(MSR_EFER, efer);
 488         if (efer & EFER_SVME)
 489                 return -EBUSY;
 490
 491         if (!has_svm()) {
 492                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 493                 return -EINVAL;
 494         }
 495         sd = per_cpu(svm_data, me);
 496         if (!sd) {
 497                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 498                 return -EINVAL;
 499         }
 500
 501         sd->asid_generation = 1;
 502         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 503         sd->next_asid = sd->max_asid + 1;
 504         sd->min_asid = max_sev_asid + 1;
 505
 506         gdt = get_current_gdt_rw();
 507         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 508
 509         wrmsrl(MSR_EFER, efer | EFER_SVME);
 510
 511         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 512
 513         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 514                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 515                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 516         }
 517
 518
 519         /*
 520          * Get OSVW bits.
 521          *
 522          * Note that it is possible to have a system with mixed processor
 523          * revisions and therefore different OSVW bits. If bits are not the same
 524          * on different processors then choose the worst case (i.e. if erratum
 525          * is present on one processor and not on another then assume that the
 526          * erratum is present everywhere).
 527          */
 528         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 529                 uint64_t len, status = 0;
 530                 int err;
 531
 532                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 533                 if (!err)
 534                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 535                                                       &err);
 536
 537                 if (err)
 538                         osvw_status = osvw_len = 0;
 539                 else {
 540                         if (len < osvw_len)
 541                                 osvw_len = len;
 542                         osvw_status |= status;
 543                         osvw_status &= (1ULL << osvw_len) - 1;
 544                 }
 545         } else
 546                 osvw_status = osvw_len = 0;
 547
 548         svm_init_erratum_383();
 549
 550         amd_pmu_enable_virt();
 551
 552         return 0;
 553 }
 554
 555 static void svm_cpu_uninit(int cpu)
 556 {
 557         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 558
 559         if (!sd)
 560                 return;
 561
 562         per_cpu(svm_data, cpu) = NULL;
 563         kfree(sd->sev_vmcbs);
 564         __free_page(sd->save_area);
 565         kfree(sd);
 566 }
 567
 568 static int svm_cpu_init(int cpu)
 569 {
 570         struct svm_cpu_data *sd;
 571         int ret = -ENOMEM;
 572
 573         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 574         if (!sd)
 575                 return ret;
 576         sd->cpu = cpu;
 577         sd->save_area = alloc_page(GFP_KERNEL);
 578         if (!sd->save_area)
 579                 goto free_cpu_data;
 580
 581         clear_page(page_address(sd->save_area));
 582
 583         ret = sev_cpu_init(sd);
 584         if (ret)
 585                 goto free_save_area;
 586
 587         per_cpu(svm_data, cpu) = sd;
 588
 589         return 0;
 590
 591 free_save_area:
 592         __free_page(sd->save_area);
 593 free_cpu_data:
 594         kfree(sd);
 595         return ret;
 596
 597 }
 598
 599 static int direct_access_msr_slot(u32 msr)
 600 {
 601         u32 i;
 602
 603         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 604                 if (direct_access_msrs[i].index == msr)
 605                         return i;
 606
 607         return -ENOENT;
 608 }
 609
 610 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 611                                      int write)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614         int slot = direct_access_msr_slot(msr);
 615
 616         if (slot == -ENOENT)
 617                 return;
 618
 619         /* Set the shadow bitmaps to the desired intercept states */
 620         if (read)
 621                 set_bit(slot, svm->shadow_msr_intercept.read);
 622         else
 623                 clear_bit(slot, svm->shadow_msr_intercept.read);
 624
 625         if (write)
 626                 set_bit(slot, svm->shadow_msr_intercept.write);
 627         else
 628                 clear_bit(slot, svm->shadow_msr_intercept.write);
 629 }
 630
 631 static bool valid_msr_intercept(u32 index)
 632 {
 633         return direct_access_msr_slot(index) != -ENOENT;
 634 }
 635
 636 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 637 {
 638         u8 bit_write;
 639         unsigned long tmp;
 640         u32 offset;
 641         u32 *msrpm;
 642
 643         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 644                                       to_svm(vcpu)->msrpm;
 645
 646         offset    = svm_msrpm_offset(msr);
 647         bit_write = 2 * (msr & 0x0f) + 1;
 648         tmp       = msrpm[offset];
 649
 650         BUG_ON(offset == MSR_INVALID);
 651
 652         return !!test_bit(bit_write,  &tmp);
 653 }
 654
 655 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 656                                         u32 msr, int read, int write)
 657 {
 658         u8 bit_read, bit_write;
 659         unsigned long tmp;
 660         u32 offset;
 661
 662         /*
 663          * If this warning triggers extend the direct_access_msrs list at the
 664          * beginning of the file
 665          */
 666         WARN_ON(!valid_msr_intercept(msr));
 667
 668         /* Enforce non allowed MSRs to trap */
 669         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 670                 read = 0;
 671
 672         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 673                 write = 0;
 674
 675         offset    = svm_msrpm_offset(msr);
 676         bit_read  = 2 * (msr & 0x0f);
 677         bit_write = 2 * (msr & 0x0f) + 1;
 678         tmp       = msrpm[offset];
 679
 680         BUG_ON(offset == MSR_INVALID);
 681
 682         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 683         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 684
 685         msrpm[offset] = tmp;
 686
 687         svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
 688
 689 }
 690
 691 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 692                           int read, int write)
 693 {
 694         set_shadow_msr_intercept(vcpu, msr, read, write);
 695         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 696 }
 697
 698 u32 *svm_vcpu_alloc_msrpm(void)
 699 {
 700         unsigned int order = get_order(MSRPM_SIZE);
 701         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 702         u32 *msrpm;
 703
 704         if (!pages)
 705                 return NULL;
 706
 707         msrpm = page_address(pages);
 708         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 709
 710         return msrpm;
 711 }
 712
 713 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 714 {
 715         int i;
 716
 717         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 718                 if (!direct_access_msrs[i].always)
 719                         continue;
 720                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 721         }
 722 }
 723
 724
 725 void svm_vcpu_free_msrpm(u32 *msrpm)
 726 {
 727         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 728 }
 729
 730 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 731 {
 732         struct vcpu_svm *svm = to_svm(vcpu);
 733         u32 i;
 734
 735         /*
 736          * Set intercept permissions for all direct access MSRs again. They
 737          * will automatically get filtered through the MSR filter, so we are
 738          * back in sync after this.
 739          */
 740         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 741                 u32 msr = direct_access_msrs[i].index;
 742                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 743                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 744
 745                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 746         }
 747 }
 748
 749 static void add_msr_offset(u32 offset)
 750 {
 751         int i;
 752
 753         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 754
 755                 /* Offset already in list? */
 756                 if (msrpm_offsets[i] == offset)
 757                         return;
 758
 759                 /* Slot used by another offset? */
 760                 if (msrpm_offsets[i] != MSR_INVALID)
 761                         continue;
 762
 763                 /* Add offset to list */
 764                 msrpm_offsets[i] = offset;
 765
 766                 return;
 767         }
 768
 769         /*
 770          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 771          * increase MSRPM_OFFSETS in this case.
 772          */
 773         BUG();
 774 }
 775
 776 static void init_msrpm_offsets(void)
 777 {
 778         int i;
 779
 780         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 781
 782         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 783                 u32 offset;
 784
 785                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 786                 BUG_ON(offset == MSR_INVALID);
 787
 788                 add_msr_offset(offset);
 789         }
 790 }
 791
 792 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795
 796         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 798         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 799         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 800         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 801 }
 802
 803 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 804 {
 805         struct vcpu_svm *svm = to_svm(vcpu);
 806
 807         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 808         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 809         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 810         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 811         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 812 }
 813
 814 void disable_nmi_singlestep(struct vcpu_svm *svm)
 815 {
 816         svm->nmi_singlestep = false;
 817
 818         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 819                 /* Clear our flags if they were not set by the guest */
 820                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 821                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 822                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 823                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 824         }
 825 }
 826
 827 static void grow_ple_window(struct kvm_vcpu *vcpu)
 828 {
 829         struct vcpu_svm *svm = to_svm(vcpu);
 830         struct vmcb_control_area *control = &svm->vmcb->control;
 831         int old = control->pause_filter_count;
 832
 833         control->pause_filter_count = __grow_ple_window(old,
 834                                                         pause_filter_count,
 835                                                         pause_filter_count_grow,
 836                                                         pause_filter_count_max);
 837
 838         if (control->pause_filter_count != old) {
 839                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 840                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 841                                             control->pause_filter_count, old);
 842         }
 843 }
 844
 845 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 846 {
 847         struct vcpu_svm *svm = to_svm(vcpu);
 848         struct vmcb_control_area *control = &svm->vmcb->control;
 849         int old = control->pause_filter_count;
 850
 851         control->pause_filter_count =
 852                                 __shrink_ple_window(old,
 853                                                     pause_filter_count,
 854                                                     pause_filter_count_shrink,
 855                                                     pause_filter_count);
 856         if (control->pause_filter_count != old) {
 857                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 858                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 859                                             control->pause_filter_count, old);
 860         }
 861 }
 862
 863 /*
 864  * The default MMIO mask is a single bit (excluding the present bit),
 865  * which could conflict with the memory encryption bit. Check for
 866  * memory encryption support and override the default MMIO mask if
 867  * memory encryption is enabled.
 868  */
 869 static __init void svm_adjust_mmio_mask(void)
 870 {
 871         unsigned int enc_bit, mask_bit;
 872         u64 msr, mask;
 873
 874         /* If there is no memory encryption support, use existing mask */
 875         if (cpuid_eax(0x80000000) < 0x8000001f)
 876                 return;
 877
 878         /* If memory encryption is not enabled, use existing mask */
 879         rdmsrl(MSR_AMD64_SYSCFG, msr);
 880         if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
 881                 return;
 882
 883         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 884         mask_bit = boot_cpu_data.x86_phys_bits;
 885
 886         /* Increment the mask bit if it is the same as the encryption bit */
 887         if (enc_bit == mask_bit)
 888                 mask_bit++;
 889
 890         /*
 891          * If the mask bit location is below 52, then some bits above the
 892          * physical addressing limit will always be reserved, so use the
 893          * rsvd_bits() function to generate the mask. This mask, along with
 894          * the present bit, will be used to generate a page fault with
 895          * PFER.RSV = 1.
 896          *
 897          * If the mask bit location is 52 (or above), then clear the mask.
 898          */
 899         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 900
 901         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 902 }
 903
 904 static void svm_hardware_teardown(void)
 905 {
 906         int cpu;
 907
 908         sev_hardware_teardown();
 909
 910         for_each_possible_cpu(cpu)
 911                 svm_cpu_uninit(cpu);
 912
 913         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 914         get_order(IOPM_SIZE));
 915         iopm_base = 0;
 916 }
 917
 918 static __init void svm_set_cpu_caps(void)
 919 {
 920         kvm_set_cpu_caps();
 921
 922         supported_xss = 0;
 923
 924         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 925         if (nested) {
 926                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 927
 928                 if (nrips)
 929                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 930
 931                 if (npt_enabled)
 932                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 933
 934                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 935                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 936         }
 937
 938         /* CPUID 0x80000008 */
 939         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 940             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 941                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 942
 943         /* CPUID 0x8000001F (SME/SEV features) */
 944         sev_set_cpu_caps();
 945 }
 946
 947 static __init int svm_hardware_setup(void)
 948 {
 949         int cpu;
 950         struct page *iopm_pages;
 951         void *iopm_va;
 952         int r;
 953         unsigned int order = get_order(IOPM_SIZE);
 954
 955         /*
 956          * NX is required for shadow paging and for NPT if the NX huge pages
 957          * mitigation is enabled.
 958          */
 959         if (!boot_cpu_has(X86_FEATURE_NX)) {
 960                 pr_err_ratelimited("NX (Execute Disable) not supported\n");
 961                 return -EOPNOTSUPP;
 962         }
 963         kvm_enable_efer_bits(EFER_NX);
 964
 965         iopm_pages = alloc_pages(GFP_KERNEL, order);
 966
 967         if (!iopm_pages)
 968                 return -ENOMEM;
 969
 970         iopm_va = page_address(iopm_pages);
 971         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 972         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 973
 974         init_msrpm_offsets();
 975
 976         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 977
 978         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 979                 kvm_enable_efer_bits(EFER_FFXSR);
 980
 981         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 982                 kvm_has_tsc_control = true;
 983                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 984                 kvm_tsc_scaling_ratio_frac_bits = 32;
 985         }
 986
 987         tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 988
 989         /* Check for pause filtering support */
 990         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 991                 pause_filter_count = 0;
 992                 pause_filter_thresh = 0;
 993         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 994                 pause_filter_thresh = 0;
 995         }
 996
 997         if (nested) {
 998                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 999                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1000         }
1001
1002         /*
1003          * KVM's MMU doesn't support using 2-level paging for itself, and thus
1004          * NPT isn't supported if the host is using 2-level paging since host
1005          * CR4 is unchanged on VMRUN.
1006          */
1007         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
1008                 npt_enabled = false;
1009
1010         if (!boot_cpu_has(X86_FEATURE_NPT))
1011                 npt_enabled = false;
1012
1013         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1014         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1015
1016         /* Note, SEV setup consumes npt_enabled. */
1017         sev_hardware_setup();
1018
1019         svm_hv_hardware_setup();
1020
1021         svm_adjust_mmio_mask();
1022
1023         for_each_possible_cpu(cpu) {
1024                 r = svm_cpu_init(cpu);
1025                 if (r)
1026                         goto err;
1027         }
1028
1029         if (nrips) {
1030                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1031                         nrips = false;
1032         }
1033
1034         enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC);
1035
1036         if (enable_apicv) {
1037                 pr_info("AVIC enabled\n");
1038
1039                 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1040         }
1041
1042         if (vls) {
1043                 if (!npt_enabled ||
1044                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1045                     !IS_ENABLED(CONFIG_X86_64)) {
1046                         vls = false;
1047                 } else {
1048                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1049                 }
1050         }
1051
1052         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1053                 svm_gp_erratum_intercept = false;
1054
1055         if (vgif) {
1056                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1057                         vgif = false;
1058                 else
1059                         pr_info("Virtual GIF supported\n");
1060         }
1061
1062         svm_set_cpu_caps();
1063
1064         /*
1065          * It seems that on AMD processors PTE's accessed bit is
1066          * being set by the CPU hardware before the NPF vmexit.
1067          * This is not expected behaviour and our tests fail because
1068          * of it.
1069          * A workaround here is to disable support for
1070          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1071          * In this case userspace can know if there is support using
1072          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1073          * it
1074          * If future AMD CPU models change the behaviour described above,
1075          * this variable can be changed accordingly
1076          */
1077         allow_smaller_maxphyaddr = !npt_enabled;
1078
1079         return 0;
1080
1081 err:
1082         svm_hardware_teardown();
1083         return r;
1084 }
1085
1086 static void init_seg(struct vmcb_seg *seg)
1087 {
1088         seg->selector = 0;
1089         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1090                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1091         seg->limit = 0xffff;
1092         seg->base = 0;
1093 }
1094
1095 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1096 {
1097         seg->selector = 0;
1098         seg->attrib = SVM_SELECTOR_P_MASK | type;
1099         seg->limit = 0xffff;
1100         seg->base = 0;
1101 }
1102
1103 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1104 {
1105         struct vcpu_svm *svm = to_svm(vcpu);
1106
1107         return svm->nested.ctl.tsc_offset;
1108 }
1109
1110 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1111 {
1112         return kvm_default_tsc_scaling_ratio;
1113 }
1114
1115 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1116 {
1117         struct vcpu_svm *svm = to_svm(vcpu);
1118
1119         svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1120         svm->vmcb->control.tsc_offset = offset;
1121         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1122 }
1123
1124 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1125 {
1126         wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
1127 }
1128
1129 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1130 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1131                                               struct vcpu_svm *svm)
1132 {
1133         /*
1134          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1135          * roots, or if INVPCID is disabled in the guest to inject #UD.
1136          */
1137         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1138                 if (!npt_enabled ||
1139                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1140                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1141                 else
1142                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1143         }
1144
1145         if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1146                 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1147                         svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1148                 else
1149                         svm_set_intercept(svm, INTERCEPT_RDTSCP);
1150         }
1151 }
1152
1153 static void init_vmcb(struct kvm_vcpu *vcpu)
1154 {
1155         struct vcpu_svm *svm = to_svm(vcpu);
1156         struct vmcb_control_area *control = &svm->vmcb->control;
1157         struct vmcb_save_area *save = &svm->vmcb->save;
1158
1159         vcpu->arch.hflags = 0;
1160
1161         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1162         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1163         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1164         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1165         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1166         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1167         if (!kvm_vcpu_apicv_active(vcpu))
1168                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1169
1170         set_dr_intercepts(svm);
1171
1172         set_exception_intercept(svm, PF_VECTOR);
1173         set_exception_intercept(svm, UD_VECTOR);
1174         set_exception_intercept(svm, MC_VECTOR);
1175         set_exception_intercept(svm, AC_VECTOR);
1176         set_exception_intercept(svm, DB_VECTOR);
1177         /*
1178          * Guest access to VMware backdoor ports could legitimately
1179          * trigger #GP because of TSS I/O permission bitmap.
1180          * We intercept those #GP and allow access to them anyway
1181          * as VMware does.
1182          */
1183         if (enable_vmware_backdoor)
1184                 set_exception_intercept(svm, GP_VECTOR);
1185
1186         svm_set_intercept(svm, INTERCEPT_INTR);
1187         svm_set_intercept(svm, INTERCEPT_NMI);
1188         svm_set_intercept(svm, INTERCEPT_SMI);
1189         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1190         svm_set_intercept(svm, INTERCEPT_RDPMC);
1191         svm_set_intercept(svm, INTERCEPT_CPUID);
1192         svm_set_intercept(svm, INTERCEPT_INVD);
1193         svm_set_intercept(svm, INTERCEPT_INVLPG);
1194         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1195         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1196         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1197         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1198         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1199         svm_set_intercept(svm, INTERCEPT_VMRUN);
1200         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1201         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1202         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1203         svm_set_intercept(svm, INTERCEPT_STGI);
1204         svm_set_intercept(svm, INTERCEPT_CLGI);
1205         svm_set_intercept(svm, INTERCEPT_SKINIT);
1206         svm_set_intercept(svm, INTERCEPT_WBINVD);
1207         svm_set_intercept(svm, INTERCEPT_XSETBV);
1208         svm_set_intercept(svm, INTERCEPT_RDPRU);
1209         svm_set_intercept(svm, INTERCEPT_RSM);
1210
1211         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1212                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1213                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1214         }
1215
1216         if (!kvm_hlt_in_guest(vcpu->kvm))
1217                 svm_set_intercept(svm, INTERCEPT_HLT);
1218
1219         control->iopm_base_pa = __sme_set(iopm_base);
1220         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1221         control->int_ctl = V_INTR_MASKING_MASK;
1222
1223         init_seg(&save->es);
1224         init_seg(&save->ss);
1225         init_seg(&save->ds);
1226         init_seg(&save->fs);
1227         init_seg(&save->gs);
1228
1229         save->cs.selector = 0xf000;
1230         save->cs.base = 0xffff0000;
1231         /* Executable/Readable Code Segment */
1232         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1233                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1234         save->cs.limit = 0xffff;
1235
1236         save->gdtr.limit = 0xffff;
1237         save->idtr.limit = 0xffff;
1238
1239         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1240         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1241
1242         svm_set_cr4(vcpu, 0);
1243         svm_set_efer(vcpu, 0);
1244         save->dr6 = 0xffff0ff0;
1245         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
1246         save->rip = 0x0000fff0;
1247         vcpu->arch.regs[VCPU_REGS_RIP] = save->rip;
1248
1249         /*
1250          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1251          * It also updates the guest-visible cr0 value.
1252          */
1253         svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1254         kvm_mmu_reset_context(vcpu);
1255
1256         save->cr4 = X86_CR4_PAE;
1257         /* rdx = ?? */
1258
1259         if (npt_enabled) {
1260                 /* Setup VMCB for Nested Paging */
1261                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1262                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1263                 clr_exception_intercept(svm, PF_VECTOR);
1264                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1265                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1266                 save->g_pat = vcpu->arch.pat;
1267                 save->cr3 = 0;
1268                 save->cr4 = 0;
1269         }
1270         svm->current_vmcb->asid_generation = 0;
1271         svm->asid = 0;
1272
1273         svm->nested.vmcb12_gpa = INVALID_GPA;
1274         svm->nested.last_vmcb12_gpa = INVALID_GPA;
1275         vcpu->arch.hflags = 0;
1276
1277         if (!kvm_pause_in_guest(vcpu->kvm)) {
1278                 control->pause_filter_count = pause_filter_count;
1279                 if (pause_filter_thresh)
1280                         control->pause_filter_thresh = pause_filter_thresh;
1281                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1282         } else {
1283                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1284         }
1285
1286         svm_recalc_instruction_intercepts(vcpu, svm);
1287
1288         /*
1289          * If the host supports V_SPEC_CTRL then disable the interception
1290          * of MSR_IA32_SPEC_CTRL.
1291          */
1292         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1293                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1294
1295         if (kvm_vcpu_apicv_active(vcpu))
1296                 avic_init_vmcb(svm);
1297
1298         if (vgif) {
1299                 svm_clr_intercept(svm, INTERCEPT_STGI);
1300                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1301                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1302         }
1303
1304         if (sev_guest(vcpu->kvm)) {
1305                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1306                 clr_exception_intercept(svm, UD_VECTOR);
1307
1308                 if (sev_es_guest(vcpu->kvm)) {
1309                         /* Perform SEV-ES specific VMCB updates */
1310                         sev_es_init_vmcb(svm);
1311                 }
1312         }
1313
1314         svm_hv_init_vmcb(svm->vmcb);
1315
1316         vmcb_mark_all_dirty(svm->vmcb);
1317
1318         enable_gif(svm);
1319
1320 }
1321
1322 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1323 {
1324         struct vcpu_svm *svm = to_svm(vcpu);
1325         u32 dummy;
1326         u32 eax = 1;
1327
1328         svm->spec_ctrl = 0;
1329         svm->virt_spec_ctrl = 0;
1330
1331         if (!init_event) {
1332                 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1333                                        MSR_IA32_APICBASE_ENABLE;
1334                 if (kvm_vcpu_is_reset_bsp(vcpu))
1335                         vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1336         }
1337         init_vmcb(vcpu);
1338
1339         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1340         kvm_rdx_write(vcpu, eax);
1341
1342         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1343                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1344 }
1345
1346 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1347 {
1348         svm->current_vmcb = target_vmcb;
1349         svm->vmcb = target_vmcb->ptr;
1350 }
1351
1352 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1353 {
1354         struct vcpu_svm *svm;
1355         struct page *vmcb01_page;
1356         struct page *vmsa_page = NULL;
1357         int err;
1358
1359         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1360         svm = to_svm(vcpu);
1361
1362         err = -ENOMEM;
1363         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1364         if (!vmcb01_page)
1365                 goto out;
1366
1367         if (sev_es_guest(vcpu->kvm)) {
1368                 /*
1369                  * SEV-ES guests require a separate VMSA page used to contain
1370                  * the encrypted register state of the guest.
1371                  */
1372                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1373                 if (!vmsa_page)
1374                         goto error_free_vmcb_page;
1375
1376                 /*
1377                  * SEV-ES guests maintain an encrypted version of their FPU
1378                  * state which is restored and saved on VMRUN and VMEXIT.
1379                  * Free the fpu structure to prevent KVM from attempting to
1380                  * access the FPU state.
1381                  */
1382                 kvm_free_guest_fpu(vcpu);
1383         }
1384
1385         err = avic_init_vcpu(svm);
1386         if (err)
1387                 goto error_free_vmsa_page;
1388
1389         /* We initialize this flag to true to make sure that the is_running
1390          * bit would be set the first time the vcpu is loaded.
1391          */
1392         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1393                 svm->avic_is_running = true;
1394
1395         svm->msrpm = svm_vcpu_alloc_msrpm();
1396         if (!svm->msrpm) {
1397                 err = -ENOMEM;
1398                 goto error_free_vmsa_page;
1399         }
1400
1401         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1402
1403         svm->vmcb01.ptr = page_address(vmcb01_page);
1404         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1405
1406         if (vmsa_page)
1407                 svm->vmsa = page_address(vmsa_page);
1408
1409         svm->guest_state_loaded = false;
1410
1411         svm_switch_vmcb(svm, &svm->vmcb01);
1412         init_vmcb(vcpu);
1413
1414         svm_init_osvw(vcpu);
1415         vcpu->arch.microcode_version = 0x01000065;
1416
1417         if (sev_es_guest(vcpu->kvm))
1418                 /* Perform SEV-ES specific VMCB creation updates */
1419                 sev_es_create_vcpu(svm);
1420
1421         return 0;
1422
1423 error_free_vmsa_page:
1424         if (vmsa_page)
1425                 __free_page(vmsa_page);
1426 error_free_vmcb_page:
1427         __free_page(vmcb01_page);
1428 out:
1429         return err;
1430 }
1431
1432 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1433 {
1434         int i;
1435
1436         for_each_online_cpu(i)
1437                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1438 }
1439
1440 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1441 {
1442         struct vcpu_svm *svm = to_svm(vcpu);
1443
1444         /*
1445          * The vmcb page can be recycled, causing a false negative in
1446          * svm_vcpu_load(). So, ensure that no logical CPU has this
1447          * vmcb page recorded as its current vmcb.
1448          */
1449         svm_clear_current_vmcb(svm->vmcb);
1450
1451         svm_free_nested(svm);
1452
1453         sev_free_vcpu(vcpu);
1454
1455         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1456         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1457 }
1458
1459 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1460 {
1461         struct vcpu_svm *svm = to_svm(vcpu);
1462         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1463
1464         if (sev_es_guest(vcpu->kvm))
1465                 sev_es_unmap_ghcb(svm);
1466
1467         if (svm->guest_state_loaded)
1468                 return;
1469
1470         /*
1471          * Save additional host state that will be restored on VMEXIT (sev-es)
1472          * or subsequent vmload of host save area.
1473          */
1474         if (sev_es_guest(vcpu->kvm)) {
1475                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1476         } else {
1477                 vmsave(__sme_page_pa(sd->save_area));
1478         }
1479
1480         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1481                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1482                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1483                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1484                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1485                 }
1486         }
1487
1488         if (likely(tsc_aux_uret_slot >= 0))
1489                 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1490
1491         svm->guest_state_loaded = true;
1492 }
1493
1494 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1495 {
1496         to_svm(vcpu)->guest_state_loaded = false;
1497 }
1498
1499 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1500 {
1501         struct vcpu_svm *svm = to_svm(vcpu);
1502         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1503
1504         if (sd->current_vmcb != svm->vmcb) {
1505                 sd->current_vmcb = svm->vmcb;
1506                 indirect_branch_prediction_barrier();
1507         }
1508         avic_vcpu_load(vcpu, cpu);
1509 }
1510
1511 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1512 {
1513         avic_vcpu_put(vcpu);
1514         svm_prepare_host_switch(vcpu);
1515
1516         ++vcpu->stat.host_state_reload;
1517 }
1518
1519 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1520 {
1521         struct vcpu_svm *svm = to_svm(vcpu);
1522         unsigned long rflags = svm->vmcb->save.rflags;
1523
1524         if (svm->nmi_singlestep) {
1525                 /* Hide our flags if they were not set by the guest */
1526                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1527                         rflags &= ~X86_EFLAGS_TF;
1528                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1529                         rflags &= ~X86_EFLAGS_RF;
1530         }
1531         return rflags;
1532 }
1533
1534 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1535 {
1536         if (to_svm(vcpu)->nmi_singlestep)
1537                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1538
1539        /*
1540         * Any change of EFLAGS.VM is accompanied by a reload of SS
1541         * (caused by either a task switch or an inter-privilege IRET),
1542         * so we do not need to update the CPL here.
1543         */
1544         to_svm(vcpu)->vmcb->save.rflags = rflags;
1545 }
1546
1547 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1548 {
1549         switch (reg) {
1550         case VCPU_EXREG_PDPTR:
1551                 BUG_ON(!npt_enabled);
1552                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1553                 break;
1554         default:
1555                 WARN_ON_ONCE(1);
1556         }
1557 }
1558
1559 static void svm_set_vintr(struct vcpu_svm *svm)
1560 {
1561         struct vmcb_control_area *control;
1562
1563         /* The following fields are ignored when AVIC is enabled */
1564         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1565         svm_set_intercept(svm, INTERCEPT_VINTR);
1566
1567         /*
1568          * This is just a dummy VINTR to actually cause a vmexit to happen.
1569          * Actual injection of virtual interrupts happens through EVENTINJ.
1570          */
1571         control = &svm->vmcb->control;
1572         control->int_vector = 0x0;
1573         control->int_ctl &= ~V_INTR_PRIO_MASK;
1574         control->int_ctl |= V_IRQ_MASK |
1575                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1576         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1577 }
1578
1579 static void svm_clear_vintr(struct vcpu_svm *svm)
1580 {
1581         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1582         svm_clr_intercept(svm, INTERCEPT_VINTR);
1583
1584         /* Drop int_ctl fields related to VINTR injection.  */
1585         svm->vmcb->control.int_ctl &= mask;
1586         if (is_guest_mode(&svm->vcpu)) {
1587                 svm->vmcb01.ptr->control.int_ctl &= mask;
1588
1589                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1590                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1591                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1592         }
1593
1594         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1595 }
1596
1597 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1598 {
1599         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1600         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1601
1602         switch (seg) {
1603         case VCPU_SREG_CS: return &save->cs;
1604         case VCPU_SREG_DS: return &save->ds;
1605         case VCPU_SREG_ES: return &save->es;
1606         case VCPU_SREG_FS: return &save01->fs;
1607         case VCPU_SREG_GS: return &save01->gs;
1608         case VCPU_SREG_SS: return &save->ss;
1609         case VCPU_SREG_TR: return &save01->tr;
1610         case VCPU_SREG_LDTR: return &save01->ldtr;
1611         }
1612         BUG();
1613         return NULL;
1614 }
1615
1616 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1617 {
1618         struct vmcb_seg *s = svm_seg(vcpu, seg);
1619
1620         return s->base;
1621 }
1622
1623 static void svm_get_segment(struct kvm_vcpu *vcpu,
1624                             struct kvm_segment *var, int seg)
1625 {
1626         struct vmcb_seg *s = svm_seg(vcpu, seg);
1627
1628         var->base = s->base;
1629         var->limit = s->limit;
1630         var->selector = s->selector;
1631         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1632         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1633         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1634         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1635         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1636         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1637         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1638
1639         /*
1640          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1641          * However, the SVM spec states that the G bit is not observed by the
1642          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1643          * So let's synthesize a legal G bit for all segments, this helps
1644          * running KVM nested. It also helps cross-vendor migration, because
1645          * Intel's vmentry has a check on the 'G' bit.
1646          */
1647         var->g = s->limit > 0xfffff;
1648
1649         /*
1650          * AMD's VMCB does not have an explicit unusable field, so emulate it
1651          * for cross vendor migration purposes by "not present"
1652          */
1653         var->unusable = !var->present;
1654
1655         switch (seg) {
1656         case VCPU_SREG_TR:
1657                 /*
1658                  * Work around a bug where the busy flag in the tr selector
1659                  * isn't exposed
1660                  */
1661                 var->type |= 0x2;
1662                 break;
1663         case VCPU_SREG_DS:
1664         case VCPU_SREG_ES:
1665         case VCPU_SREG_FS:
1666         case VCPU_SREG_GS:
1667                 /*
1668                  * The accessed bit must always be set in the segment
1669                  * descriptor cache, although it can be cleared in the
1670                  * descriptor, the cached bit always remains at 1. Since
1671                  * Intel has a check on this, set it here to support
1672                  * cross-vendor migration.
1673                  */
1674                 if (!var->unusable)
1675                         var->type |= 0x1;
1676                 break;
1677         case VCPU_SREG_SS:
1678                 /*
1679                  * On AMD CPUs sometimes the DB bit in the segment
1680                  * descriptor is left as 1, although the whole segment has
1681                  * been made unusable. Clear it here to pass an Intel VMX
1682                  * entry check when cross vendor migrating.
1683                  */
1684                 if (var->unusable)
1685                         var->db = 0;
1686                 /* This is symmetric with svm_set_segment() */
1687                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1688                 break;
1689         }
1690 }
1691
1692 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1693 {
1694         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1695
1696         return save->cpl;
1697 }
1698
1699 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1700 {
1701         struct vcpu_svm *svm = to_svm(vcpu);
1702
1703         dt->size = svm->vmcb->save.idtr.limit;
1704         dt->address = svm->vmcb->save.idtr.base;
1705 }
1706
1707 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1708 {
1709         struct vcpu_svm *svm = to_svm(vcpu);
1710
1711         svm->vmcb->save.idtr.limit = dt->size;
1712         svm->vmcb->save.idtr.base = dt->address ;
1713         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1714 }
1715
1716 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1717 {
1718         struct vcpu_svm *svm = to_svm(vcpu);
1719
1720         dt->size = svm->vmcb->save.gdtr.limit;
1721         dt->address = svm->vmcb->save.gdtr.base;
1722 }
1723
1724 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1725 {
1726         struct vcpu_svm *svm = to_svm(vcpu);
1727
1728         svm->vmcb->save.gdtr.limit = dt->size;
1729         svm->vmcb->save.gdtr.base = dt->address ;
1730         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1731 }
1732
1733 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1734 {
1735         struct vcpu_svm *svm = to_svm(vcpu);
1736         u64 hcr0 = cr0;
1737
1738 #ifdef CONFIG_X86_64
1739         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1740                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1741                         vcpu->arch.efer |= EFER_LMA;
1742                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1743                 }
1744
1745                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1746                         vcpu->arch.efer &= ~EFER_LMA;
1747                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1748                 }
1749         }
1750 #endif
1751         vcpu->arch.cr0 = cr0;
1752
1753         if (!npt_enabled)
1754                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1755
1756         /*
1757          * re-enable caching here because the QEMU bios
1758          * does not do it - this results in some delay at
1759          * reboot
1760          */
1761         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1762                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1763
1764         svm->vmcb->save.cr0 = hcr0;
1765         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1766
1767         /*
1768          * SEV-ES guests must always keep the CR intercepts cleared. CR
1769          * tracking is done using the CR write traps.
1770          */
1771         if (sev_es_guest(vcpu->kvm))
1772                 return;
1773
1774         if (hcr0 == cr0) {
1775                 /* Selective CR0 write remains on.  */
1776                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1777                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1778         } else {
1779                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1780                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1781         }
1782 }
1783
1784 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1785 {
1786         return true;
1787 }
1788
1789 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1790 {
1791         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1792         unsigned long old_cr4 = vcpu->arch.cr4;
1793
1794         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1795                 svm_flush_tlb(vcpu);
1796
1797         vcpu->arch.cr4 = cr4;
1798         if (!npt_enabled)
1799                 cr4 |= X86_CR4_PAE;
1800         cr4 |= host_cr4_mce;
1801         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1802         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1803
1804         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1805                 kvm_update_cpuid_runtime(vcpu);
1806 }
1807
1808 static void svm_set_segment(struct kvm_vcpu *vcpu,
1809                             struct kvm_segment *var, int seg)
1810 {
1811         struct vcpu_svm *svm = to_svm(vcpu);
1812         struct vmcb_seg *s = svm_seg(vcpu, seg);
1813
1814         s->base = var->base;
1815         s->limit = var->limit;
1816         s->selector = var->selector;
1817         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1818         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1819         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1820         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1821         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1822         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1823         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1824         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1825
1826         /*
1827          * This is always accurate, except if SYSRET returned to a segment
1828          * with SS.DPL != 3.  Intel does not have this quirk, and always
1829          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1830          * would entail passing the CPL to userspace and back.
1831          */
1832         if (seg == VCPU_SREG_SS)
1833                 /* This is symmetric with svm_get_segment() */
1834                 svm->vmcb->save.cpl = (var->dpl & 3);
1835
1836         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1837 }
1838
1839 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1840 {
1841         struct vcpu_svm *svm = to_svm(vcpu);
1842
1843         clr_exception_intercept(svm, BP_VECTOR);
1844
1845         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1846                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1847                         set_exception_intercept(svm, BP_VECTOR);
1848         }
1849 }
1850
1851 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1852 {
1853         if (sd->next_asid > sd->max_asid) {
1854                 ++sd->asid_generation;
1855                 sd->next_asid = sd->min_asid;
1856                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1857                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1858         }
1859
1860         svm->current_vmcb->asid_generation = sd->asid_generation;
1861         svm->asid = sd->next_asid++;
1862 }
1863
1864 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1865 {
1866         struct vmcb *vmcb = svm->vmcb;
1867
1868         if (svm->vcpu.arch.guest_state_protected)
1869                 return;
1870
1871         if (unlikely(value != vmcb->save.dr6)) {
1872                 vmcb->save.dr6 = value;
1873                 vmcb_mark_dirty(vmcb, VMCB_DR);
1874         }
1875 }
1876
1877 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1878 {
1879         struct vcpu_svm *svm = to_svm(vcpu);
1880
1881         if (vcpu->arch.guest_state_protected)
1882                 return;
1883
1884         get_debugreg(vcpu->arch.db[0], 0);
1885         get_debugreg(vcpu->arch.db[1], 1);
1886         get_debugreg(vcpu->arch.db[2], 2);
1887         get_debugreg(vcpu->arch.db[3], 3);
1888         /*
1889          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1890          * because db_interception might need it.  We can do it before vmentry.
1891          */
1892         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1893         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1894         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1895         set_dr_intercepts(svm);
1896 }
1897
1898 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1899 {
1900         struct vcpu_svm *svm = to_svm(vcpu);
1901
1902         if (vcpu->arch.guest_state_protected)
1903                 return;
1904
1905         svm->vmcb->save.dr7 = value;
1906         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1907 }
1908
1909 static int pf_interception(struct kvm_vcpu *vcpu)
1910 {
1911         struct vcpu_svm *svm = to_svm(vcpu);
1912
1913         u64 fault_address = svm->vmcb->control.exit_info_2;
1914         u64 error_code = svm->vmcb->control.exit_info_1;
1915
1916         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1917                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1918                         svm->vmcb->control.insn_bytes : NULL,
1919                         svm->vmcb->control.insn_len);
1920 }
1921
1922 static int npf_interception(struct kvm_vcpu *vcpu)
1923 {
1924         struct vcpu_svm *svm = to_svm(vcpu);
1925
1926         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1927         u64 error_code = svm->vmcb->control.exit_info_1;
1928
1929         trace_kvm_page_fault(fault_address, error_code);
1930         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1931                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1932                         svm->vmcb->control.insn_bytes : NULL,
1933                         svm->vmcb->control.insn_len);
1934 }
1935
1936 static int db_interception(struct kvm_vcpu *vcpu)
1937 {
1938         struct kvm_run *kvm_run = vcpu->run;
1939         struct vcpu_svm *svm = to_svm(vcpu);
1940
1941         if (!(vcpu->guest_debug &
1942               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1943                 !svm->nmi_singlestep) {
1944                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1945                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1946                 return 1;
1947         }
1948
1949         if (svm->nmi_singlestep) {
1950                 disable_nmi_singlestep(svm);
1951                 /* Make sure we check for pending NMIs upon entry */
1952                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1953         }
1954
1955         if (vcpu->guest_debug &
1956             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1957                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1958                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1959                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1960                 kvm_run->debug.arch.pc =
1961                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1962                 kvm_run->debug.arch.exception = DB_VECTOR;
1963                 return 0;
1964         }
1965
1966         return 1;
1967 }
1968
1969 static int bp_interception(struct kvm_vcpu *vcpu)
1970 {
1971         struct vcpu_svm *svm = to_svm(vcpu);
1972         struct kvm_run *kvm_run = vcpu->run;
1973
1974         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1975         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1976         kvm_run->debug.arch.exception = BP_VECTOR;
1977         return 0;
1978 }
1979
1980 static int ud_interception(struct kvm_vcpu *vcpu)
1981 {
1982         return handle_ud(vcpu);
1983 }
1984
1985 static int ac_interception(struct kvm_vcpu *vcpu)
1986 {
1987         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1988         return 1;
1989 }
1990
1991 static bool is_erratum_383(void)
1992 {
1993         int err, i;
1994         u64 value;
1995
1996         if (!erratum_383_found)
1997                 return false;
1998
1999         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2000         if (err)
2001                 return false;
2002
2003         /* Bit 62 may or may not be set for this mce */
2004         value &= ~(1ULL << 62);
2005
2006         if (value != 0xb600000000010015ULL)
2007                 return false;
2008
2009         /* Clear MCi_STATUS registers */
2010         for (i = 0; i < 6; ++i)
2011                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2012
2013         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2014         if (!err) {
2015                 u32 low, high;
2016
2017                 value &= ~(1ULL << 2);
2018                 low    = lower_32_bits(value);
2019                 high   = upper_32_bits(value);
2020
2021                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2022         }
2023
2024         /* Flush tlb to evict multi-match entries */
2025         __flush_tlb_all();
2026
2027         return true;
2028 }
2029
2030 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2031 {
2032         if (is_erratum_383()) {
2033                 /*
2034                  * Erratum 383 triggered. Guest state is corrupt so kill the
2035                  * guest.
2036                  */
2037                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2038
2039                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2040
2041                 return;
2042         }
2043
2044         /*
2045          * On an #MC intercept the MCE handler is not called automatically in
2046          * the host. So do it by hand here.
2047          */
2048         kvm_machine_check();
2049 }
2050
2051 static int mc_interception(struct kvm_vcpu *vcpu)
2052 {
2053         return 1;
2054 }
2055
2056 static int shutdown_interception(struct kvm_vcpu *vcpu)
2057 {
2058         struct kvm_run *kvm_run = vcpu->run;
2059         struct vcpu_svm *svm = to_svm(vcpu);
2060
2061         /*
2062          * The VM save area has already been encrypted so it
2063          * cannot be reinitialized - just terminate.
2064          */
2065         if (sev_es_guest(vcpu->kvm))
2066                 return -EINVAL;
2067
2068         /*
2069          * VMCB is undefined after a SHUTDOWN intercept
2070          * so reinitialize it.
2071          */
2072         clear_page(svm->vmcb);
2073         init_vmcb(vcpu);
2074
2075         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2076         return 0;
2077 }
2078
2079 static int io_interception(struct kvm_vcpu *vcpu)
2080 {
2081         struct vcpu_svm *svm = to_svm(vcpu);
2082         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2083         int size, in, string;
2084         unsigned port;
2085
2086         ++vcpu->stat.io_exits;
2087         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2088         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2089         port = io_info >> 16;
2090         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2091
2092         if (string) {
2093                 if (sev_es_guest(vcpu->kvm))
2094                         return sev_es_string_io(svm, size, port, in);
2095                 else
2096                         return kvm_emulate_instruction(vcpu, 0);
2097         }
2098
2099         svm->next_rip = svm->vmcb->control.exit_info_2;
2100
2101         return kvm_fast_pio(vcpu, size, port, in);
2102 }
2103
2104 static int nmi_interception(struct kvm_vcpu *vcpu)
2105 {
2106         return 1;
2107 }
2108
2109 static int intr_interception(struct kvm_vcpu *vcpu)
2110 {
2111         ++vcpu->stat.irq_exits;
2112         return 1;
2113 }
2114
2115 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2116 {
2117         struct vcpu_svm *svm = to_svm(vcpu);
2118         struct vmcb *vmcb12;
2119         struct kvm_host_map map;
2120         int ret;
2121
2122         if (nested_svm_check_permissions(vcpu))
2123                 return 1;
2124
2125         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2126         if (ret) {
2127                 if (ret == -EINVAL)
2128                         kvm_inject_gp(vcpu, 0);
2129                 return 1;
2130         }
2131
2132         vmcb12 = map.hva;
2133
2134         ret = kvm_skip_emulated_instruction(vcpu);
2135
2136         if (vmload) {
2137                 nested_svm_vmloadsave(vmcb12, svm->vmcb);
2138                 svm->sysenter_eip_hi = 0;
2139                 svm->sysenter_esp_hi = 0;
2140         } else
2141                 nested_svm_vmloadsave(svm->vmcb, vmcb12);
2142
2143         kvm_vcpu_unmap(vcpu, &map, true);
2144
2145         return ret;
2146 }
2147
2148 static int vmload_interception(struct kvm_vcpu *vcpu)
2149 {
2150         return vmload_vmsave_interception(vcpu, true);
2151 }
2152
2153 static int vmsave_interception(struct kvm_vcpu *vcpu)
2154 {
2155         return vmload_vmsave_interception(vcpu, false);
2156 }
2157
2158 static int vmrun_interception(struct kvm_vcpu *vcpu)
2159 {
2160         if (nested_svm_check_permissions(vcpu))
2161                 return 1;
2162
2163         return nested_svm_vmrun(vcpu);
2164 }
2165
2166 enum {
2167         NONE_SVM_INSTR,
2168         SVM_INSTR_VMRUN,
2169         SVM_INSTR_VMLOAD,
2170         SVM_INSTR_VMSAVE,
2171 };
2172
2173 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2174 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2175 {
2176         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2177
2178         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2179                 return NONE_SVM_INSTR;
2180
2181         switch (ctxt->modrm) {
2182         case 0xd8: /* VMRUN */
2183                 return SVM_INSTR_VMRUN;
2184         case 0xda: /* VMLOAD */
2185                 return SVM_INSTR_VMLOAD;
2186         case 0xdb: /* VMSAVE */
2187                 return SVM_INSTR_VMSAVE;
2188         default:
2189                 break;
2190         }
2191
2192         return NONE_SVM_INSTR;
2193 }
2194
2195 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2196 {
2197         const int guest_mode_exit_codes[] = {
2198                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2199                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2200                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2201         };
2202         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2203                 [SVM_INSTR_VMRUN] = vmrun_interception,
2204                 [SVM_INSTR_VMLOAD] = vmload_interception,
2205                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2206         };
2207         struct vcpu_svm *svm = to_svm(vcpu);
2208         int ret;
2209
2210         if (is_guest_mode(vcpu)) {
2211                 /* Returns '1' or -errno on failure, '0' on success. */
2212                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2213                 if (ret)
2214                         return ret;
2215                 return 1;
2216         }
2217         return svm_instr_handlers[opcode](vcpu);
2218 }
2219
2220 /*
2221  * #GP handling code. Note that #GP can be triggered under the following two
2222  * cases:
2223  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2224  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2225  *      regions (e.g. SMM memory on host).
2226  *   2) VMware backdoor
2227  */
2228 static int gp_interception(struct kvm_vcpu *vcpu)
2229 {
2230         struct vcpu_svm *svm = to_svm(vcpu);
2231         u32 error_code = svm->vmcb->control.exit_info_1;
2232         int opcode;
2233
2234         /* Both #GP cases have zero error_code */
2235         if (error_code)
2236                 goto reinject;
2237
2238         /* Decode the instruction for usage later */
2239         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2240                 goto reinject;
2241
2242         opcode = svm_instr_opcode(vcpu);
2243
2244         if (opcode == NONE_SVM_INSTR) {
2245                 if (!enable_vmware_backdoor)
2246                         goto reinject;
2247
2248                 /*
2249                  * VMware backdoor emulation on #GP interception only handles
2250                  * IN{S}, OUT{S}, and RDPMC.
2251                  */
2252                 if (!is_guest_mode(vcpu))
2253                         return kvm_emulate_instruction(vcpu,
2254                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2255         } else
2256                 return emulate_svm_instr(vcpu, opcode);
2257
2258 reinject:
2259         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2260         return 1;
2261 }
2262
2263 void svm_set_gif(struct vcpu_svm *svm, bool value)
2264 {
2265         if (value) {
2266                 /*
2267                  * If VGIF is enabled, the STGI intercept is only added to
2268                  * detect the opening of the SMI/NMI window; remove it now.
2269                  * Likewise, clear the VINTR intercept, we will set it
2270                  * again while processing KVM_REQ_EVENT if needed.
2271                  */
2272                 if (vgif_enabled(svm))
2273                         svm_clr_intercept(svm, INTERCEPT_STGI);
2274                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2275                         svm_clear_vintr(svm);
2276
2277                 enable_gif(svm);
2278                 if (svm->vcpu.arch.smi_pending ||
2279                     svm->vcpu.arch.nmi_pending ||
2280                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2281                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2282         } else {
2283                 disable_gif(svm);
2284
2285                 /*
2286                  * After a CLGI no interrupts should come.  But if vGIF is
2287                  * in use, we still rely on the VINTR intercept (rather than
2288                  * STGI) to detect an open interrupt window.
2289                 */
2290                 if (!vgif_enabled(svm))
2291                         svm_clear_vintr(svm);
2292         }
2293 }
2294
2295 static int stgi_interception(struct kvm_vcpu *vcpu)
2296 {
2297         int ret;
2298
2299         if (nested_svm_check_permissions(vcpu))
2300                 return 1;
2301
2302         ret = kvm_skip_emulated_instruction(vcpu);
2303         svm_set_gif(to_svm(vcpu), true);
2304         return ret;
2305 }
2306
2307 static int clgi_interception(struct kvm_vcpu *vcpu)
2308 {
2309         int ret;
2310
2311         if (nested_svm_check_permissions(vcpu))
2312                 return 1;
2313
2314         ret = kvm_skip_emulated_instruction(vcpu);
2315         svm_set_gif(to_svm(vcpu), false);
2316         return ret;
2317 }
2318
2319 static int invlpga_interception(struct kvm_vcpu *vcpu)
2320 {
2321         gva_t gva = kvm_rax_read(vcpu);
2322         u32 asid = kvm_rcx_read(vcpu);
2323
2324         /* FIXME: Handle an address size prefix. */
2325         if (!is_long_mode(vcpu))
2326                 gva = (u32)gva;
2327
2328         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2329
2330         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2331         kvm_mmu_invlpg(vcpu, gva);
2332
2333         return kvm_skip_emulated_instruction(vcpu);
2334 }
2335
2336 static int skinit_interception(struct kvm_vcpu *vcpu)
2337 {
2338         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2339
2340         kvm_queue_exception(vcpu, UD_VECTOR);
2341         return 1;
2342 }
2343
2344 static int task_switch_interception(struct kvm_vcpu *vcpu)
2345 {
2346         struct vcpu_svm *svm = to_svm(vcpu);
2347         u16 tss_selector;
2348         int reason;
2349         int int_type = svm->vmcb->control.exit_int_info &
2350                 SVM_EXITINTINFO_TYPE_MASK;
2351         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2352         uint32_t type =
2353                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2354         uint32_t idt_v =
2355                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2356         bool has_error_code = false;
2357         u32 error_code = 0;
2358
2359         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2360
2361         if (svm->vmcb->control.exit_info_2 &
2362             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2363                 reason = TASK_SWITCH_IRET;
2364         else if (svm->vmcb->control.exit_info_2 &
2365                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2366                 reason = TASK_SWITCH_JMP;
2367         else if (idt_v)
2368                 reason = TASK_SWITCH_GATE;
2369         else
2370                 reason = TASK_SWITCH_CALL;
2371
2372         if (reason == TASK_SWITCH_GATE) {
2373                 switch (type) {
2374                 case SVM_EXITINTINFO_TYPE_NMI:
2375                         vcpu->arch.nmi_injected = false;
2376                         break;
2377                 case SVM_EXITINTINFO_TYPE_EXEPT:
2378                         if (svm->vmcb->control.exit_info_2 &
2379                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2380                                 has_error_code = true;
2381                                 error_code =
2382                                         (u32)svm->vmcb->control.exit_info_2;
2383                         }
2384                         kvm_clear_exception_queue(vcpu);
2385                         break;
2386                 case SVM_EXITINTINFO_TYPE_INTR:
2387                         kvm_clear_interrupt_queue(vcpu);
2388                         break;
2389                 default:
2390                         break;
2391                 }
2392         }
2393
2394         if (reason != TASK_SWITCH_GATE ||
2395             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2396             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2397              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2398                 if (!skip_emulated_instruction(vcpu))
2399                         return 0;
2400         }
2401
2402         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2403                 int_vec = -1;
2404
2405         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2406                                has_error_code, error_code);
2407 }
2408
2409 static int iret_interception(struct kvm_vcpu *vcpu)
2410 {
2411         struct vcpu_svm *svm = to_svm(vcpu);
2412
2413         ++vcpu->stat.nmi_window_exits;
2414         vcpu->arch.hflags |= HF_IRET_MASK;
2415         if (!sev_es_guest(vcpu->kvm)) {
2416                 svm_clr_intercept(svm, INTERCEPT_IRET);
2417                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2418         }
2419         kvm_make_request(KVM_REQ_EVENT, vcpu);
2420         return 1;
2421 }
2422
2423 static int invlpg_interception(struct kvm_vcpu *vcpu)
2424 {
2425         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2426                 return kvm_emulate_instruction(vcpu, 0);
2427
2428         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2429         return kvm_skip_emulated_instruction(vcpu);
2430 }
2431
2432 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2433 {
2434         return kvm_emulate_instruction(vcpu, 0);
2435 }
2436
2437 static int rsm_interception(struct kvm_vcpu *vcpu)
2438 {
2439         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2440 }
2441
2442 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2443                                             unsigned long val)
2444 {
2445         struct vcpu_svm *svm = to_svm(vcpu);
2446         unsigned long cr0 = vcpu->arch.cr0;
2447         bool ret = false;
2448
2449         if (!is_guest_mode(vcpu) ||
2450             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2451                 return false;
2452
2453         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2454         val &= ~SVM_CR0_SELECTIVE_MASK;
2455
2456         if (cr0 ^ val) {
2457                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2458                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2459         }
2460
2461         return ret;
2462 }
2463
2464 #define CR_VALID (1ULL << 63)
2465
2466 static int cr_interception(struct kvm_vcpu *vcpu)
2467 {
2468         struct vcpu_svm *svm = to_svm(vcpu);
2469         int reg, cr;
2470         unsigned long val;
2471         int err;
2472
2473         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2474                 return emulate_on_interception(vcpu);
2475
2476         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2477                 return emulate_on_interception(vcpu);
2478
2479         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2480         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2481                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2482         else
2483                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2484
2485         err = 0;
2486         if (cr >= 16) { /* mov to cr */
2487                 cr -= 16;
2488                 val = kvm_register_read(vcpu, reg);
2489                 trace_kvm_cr_write(cr, val);
2490                 switch (cr) {
2491                 case 0:
2492                         if (!check_selective_cr0_intercepted(vcpu, val))
2493                                 err = kvm_set_cr0(vcpu, val);
2494                         else
2495                                 return 1;
2496
2497                         break;
2498                 case 3:
2499                         err = kvm_set_cr3(vcpu, val);
2500                         break;
2501                 case 4:
2502                         err = kvm_set_cr4(vcpu, val);
2503                         break;
2504                 case 8:
2505                         err = kvm_set_cr8(vcpu, val);
2506                         break;
2507                 default:
2508                         WARN(1, "unhandled write to CR%d", cr);
2509                         kvm_queue_exception(vcpu, UD_VECTOR);
2510                         return 1;
2511                 }
2512         } else { /* mov from cr */
2513                 switch (cr) {
2514                 case 0:
2515                         val = kvm_read_cr0(vcpu);
2516                         break;
2517                 case 2:
2518                         val = vcpu->arch.cr2;
2519                         break;
2520                 case 3:
2521                         val = kvm_read_cr3(vcpu);
2522                         break;
2523                 case 4:
2524                         val = kvm_read_cr4(vcpu);
2525                         break;
2526                 case 8:
2527                         val = kvm_get_cr8(vcpu);
2528                         break;
2529                 default:
2530                         WARN(1, "unhandled read from CR%d", cr);
2531                         kvm_queue_exception(vcpu, UD_VECTOR);
2532                         return 1;
2533                 }
2534                 kvm_register_write(vcpu, reg, val);
2535                 trace_kvm_cr_read(cr, val);
2536         }
2537         return kvm_complete_insn_gp(vcpu, err);
2538 }
2539
2540 static int cr_trap(struct kvm_vcpu *vcpu)
2541 {
2542         struct vcpu_svm *svm = to_svm(vcpu);
2543         unsigned long old_value, new_value;
2544         unsigned int cr;
2545         int ret = 0;
2546
2547         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2548
2549         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2550         switch (cr) {
2551         case 0:
2552                 old_value = kvm_read_cr0(vcpu);
2553                 svm_set_cr0(vcpu, new_value);
2554
2555                 kvm_post_set_cr0(vcpu, old_value, new_value);
2556                 break;
2557         case 4:
2558                 old_value = kvm_read_cr4(vcpu);
2559                 svm_set_cr4(vcpu, new_value);
2560
2561                 kvm_post_set_cr4(vcpu, old_value, new_value);
2562                 break;
2563         case 8:
2564                 ret = kvm_set_cr8(vcpu, new_value);
2565                 break;
2566         default:
2567                 WARN(1, "unhandled CR%d write trap", cr);
2568                 kvm_queue_exception(vcpu, UD_VECTOR);
2569                 return 1;
2570         }
2571
2572         return kvm_complete_insn_gp(vcpu, ret);
2573 }
2574
2575 static int dr_interception(struct kvm_vcpu *vcpu)
2576 {
2577         struct vcpu_svm *svm = to_svm(vcpu);
2578         int reg, dr;
2579         unsigned long val;
2580         int err = 0;
2581
2582         if (vcpu->guest_debug == 0) {
2583                 /*
2584                  * No more DR vmexits; force a reload of the debug registers
2585                  * and reenter on this instruction.  The next vmexit will
2586                  * retrieve the full state of the debug registers.
2587                  */
2588                 clr_dr_intercepts(svm);
2589                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2590                 return 1;
2591         }
2592
2593         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2594                 return emulate_on_interception(vcpu);
2595
2596         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2597         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2598         if (dr >= 16) { /* mov to DRn  */
2599                 dr -= 16;
2600                 val = kvm_register_read(vcpu, reg);
2601                 err = kvm_set_dr(vcpu, dr, val);
2602         } else {
2603                 kvm_get_dr(vcpu, dr, &val);
2604                 kvm_register_write(vcpu, reg, val);
2605         }
2606
2607         return kvm_complete_insn_gp(vcpu, err);
2608 }
2609
2610 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2611 {
2612         int r;
2613
2614         u8 cr8_prev = kvm_get_cr8(vcpu);
2615         /* instruction emulation calls kvm_set_cr8() */
2616         r = cr_interception(vcpu);
2617         if (lapic_in_kernel(vcpu))
2618                 return r;
2619         if (cr8_prev <= kvm_get_cr8(vcpu))
2620                 return r;
2621         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2622         return 0;
2623 }
2624
2625 static int efer_trap(struct kvm_vcpu *vcpu)
2626 {
2627         struct msr_data msr_info;
2628         int ret;
2629
2630         /*
2631          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2632          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2633          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2634          * the guest doesn't have X86_FEATURE_SVM.
2635          */
2636         msr_info.host_initiated = false;
2637         msr_info.index = MSR_EFER;
2638         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2639         ret = kvm_set_msr_common(vcpu, &msr_info);
2640
2641         return kvm_complete_insn_gp(vcpu, ret);
2642 }
2643
2644 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2645 {
2646         msr->data = 0;
2647
2648         switch (msr->index) {
2649         case MSR_F10H_DECFG:
2650                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2651                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2652                 break;
2653         case MSR_IA32_PERF_CAPABILITIES:
2654                 return 0;
2655         default:
2656                 return KVM_MSR_RET_INVALID;
2657         }
2658
2659         return 0;
2660 }
2661
2662 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2663 {
2664         struct vcpu_svm *svm = to_svm(vcpu);
2665
2666         switch (msr_info->index) {
2667         case MSR_STAR:
2668                 msr_info->data = svm->vmcb01.ptr->save.star;
2669                 break;
2670 #ifdef CONFIG_X86_64
2671         case MSR_LSTAR:
2672                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2673                 break;
2674         case MSR_CSTAR:
2675                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2676                 break;
2677         case MSR_KERNEL_GS_BASE:
2678                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2679                 break;
2680         case MSR_SYSCALL_MASK:
2681                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2682                 break;
2683 #endif
2684         case MSR_IA32_SYSENTER_CS:
2685                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2686                 break;
2687         case MSR_IA32_SYSENTER_EIP:
2688                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2689                 if (guest_cpuid_is_intel(vcpu))
2690                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2691                 break;
2692         case MSR_IA32_SYSENTER_ESP:
2693                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2694                 if (guest_cpuid_is_intel(vcpu))
2695                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2696                 break;
2697         case MSR_TSC_AUX:
2698                 msr_info->data = svm->tsc_aux;
2699                 break;
2700         /*
2701          * Nobody will change the following 5 values in the VMCB so we can
2702          * safely return them on rdmsr. They will always be 0 until LBRV is
2703          * implemented.
2704          */
2705         case MSR_IA32_DEBUGCTLMSR:
2706                 msr_info->data = svm->vmcb->save.dbgctl;
2707                 break;
2708         case MSR_IA32_LASTBRANCHFROMIP:
2709                 msr_info->data = svm->vmcb->save.br_from;
2710                 break;
2711         case MSR_IA32_LASTBRANCHTOIP:
2712                 msr_info->data = svm->vmcb->save.br_to;
2713                 break;
2714         case MSR_IA32_LASTINTFROMIP:
2715                 msr_info->data = svm->vmcb->save.last_excp_from;
2716                 break;
2717         case MSR_IA32_LASTINTTOIP:
2718                 msr_info->data = svm->vmcb->save.last_excp_to;
2719                 break;
2720         case MSR_VM_HSAVE_PA:
2721                 msr_info->data = svm->nested.hsave_msr;
2722                 break;
2723         case MSR_VM_CR:
2724                 msr_info->data = svm->nested.vm_cr_msr;
2725                 break;
2726         case MSR_IA32_SPEC_CTRL:
2727                 if (!msr_info->host_initiated &&
2728                     !guest_has_spec_ctrl_msr(vcpu))
2729                         return 1;
2730
2731                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2732                         msr_info->data = svm->vmcb->save.spec_ctrl;
2733                 else
2734                         msr_info->data = svm->spec_ctrl;
2735                 break;
2736         case MSR_AMD64_VIRT_SPEC_CTRL:
2737                 if (!msr_info->host_initiated &&
2738                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2739                         return 1;
2740
2741                 msr_info->data = svm->virt_spec_ctrl;
2742                 break;
2743         case MSR_F15H_IC_CFG: {
2744
2745                 int family, model;
2746
2747                 family = guest_cpuid_family(vcpu);
2748                 model  = guest_cpuid_model(vcpu);
2749
2750                 if (family < 0 || model < 0)
2751                         return kvm_get_msr_common(vcpu, msr_info);
2752
2753                 msr_info->data = 0;
2754
2755                 if (family == 0x15 &&
2756                     (model >= 0x2 && model < 0x20))
2757                         msr_info->data = 0x1E;
2758                 }
2759                 break;
2760         case MSR_F10H_DECFG:
2761                 msr_info->data = svm->msr_decfg;
2762                 break;
2763         default:
2764                 return kvm_get_msr_common(vcpu, msr_info);
2765         }
2766         return 0;
2767 }
2768
2769 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2770 {
2771         struct vcpu_svm *svm = to_svm(vcpu);
2772         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2773                 return kvm_complete_insn_gp(vcpu, err);
2774
2775         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2776         ghcb_set_sw_exit_info_2(svm->ghcb,
2777                                 X86_TRAP_GP |
2778                                 SVM_EVTINJ_TYPE_EXEPT |
2779                                 SVM_EVTINJ_VALID);
2780         return 1;
2781 }
2782
2783 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2784 {
2785         struct vcpu_svm *svm = to_svm(vcpu);
2786         int svm_dis, chg_mask;
2787
2788         if (data & ~SVM_VM_CR_VALID_MASK)
2789                 return 1;
2790
2791         chg_mask = SVM_VM_CR_VALID_MASK;
2792
2793         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2794                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2795
2796         svm->nested.vm_cr_msr &= ~chg_mask;
2797         svm->nested.vm_cr_msr |= (data & chg_mask);
2798
2799         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2800
2801         /* check for svm_disable while efer.svme is set */
2802         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2803                 return 1;
2804
2805         return 0;
2806 }
2807
2808 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2809 {
2810         struct vcpu_svm *svm = to_svm(vcpu);
2811         int r;
2812
2813         u32 ecx = msr->index;
2814         u64 data = msr->data;
2815         switch (ecx) {
2816         case MSR_IA32_CR_PAT:
2817                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2818                         return 1;
2819                 vcpu->arch.pat = data;
2820                 svm->vmcb01.ptr->save.g_pat = data;
2821                 if (is_guest_mode(vcpu))
2822                         nested_vmcb02_compute_g_pat(svm);
2823                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2824                 break;
2825         case MSR_IA32_SPEC_CTRL:
2826                 if (!msr->host_initiated &&
2827                     !guest_has_spec_ctrl_msr(vcpu))
2828                         return 1;
2829
2830                 if (kvm_spec_ctrl_test_value(data))
2831                         return 1;
2832
2833                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2834                         svm->vmcb->save.spec_ctrl = data;
2835                 else
2836                         svm->spec_ctrl = data;
2837                 if (!data)
2838                         break;
2839
2840                 /*
2841                  * For non-nested:
2842                  * When it's written (to non-zero) for the first time, pass
2843                  * it through.
2844                  *
2845                  * For nested:
2846                  * The handling of the MSR bitmap for L2 guests is done in
2847                  * nested_svm_vmrun_msrpm.
2848                  * We update the L1 MSR bit as well since it will end up
2849                  * touching the MSR anyway now.
2850                  */
2851                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2852                 break;
2853         case MSR_IA32_PRED_CMD:
2854                 if (!msr->host_initiated &&
2855                     !guest_has_pred_cmd_msr(vcpu))
2856                         return 1;
2857
2858                 if (data & ~PRED_CMD_IBPB)
2859                         return 1;
2860                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2861                         return 1;
2862                 if (!data)
2863                         break;
2864
2865                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2866                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2867                 break;
2868         case MSR_AMD64_VIRT_SPEC_CTRL:
2869                 if (!msr->host_initiated &&
2870                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2871                         return 1;
2872
2873                 if (data & ~SPEC_CTRL_SSBD)
2874                         return 1;
2875
2876                 svm->virt_spec_ctrl = data;
2877                 break;
2878         case MSR_STAR:
2879                 svm->vmcb01.ptr->save.star = data;
2880                 break;
2881 #ifdef CONFIG_X86_64
2882         case MSR_LSTAR:
2883                 svm->vmcb01.ptr->save.lstar = data;
2884                 break;
2885         case MSR_CSTAR:
2886                 svm->vmcb01.ptr->save.cstar = data;
2887                 break;
2888         case MSR_KERNEL_GS_BASE:
2889                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2890                 break;
2891         case MSR_SYSCALL_MASK:
2892                 svm->vmcb01.ptr->save.sfmask = data;
2893                 break;
2894 #endif
2895         case MSR_IA32_SYSENTER_CS:
2896                 svm->vmcb01.ptr->save.sysenter_cs = data;
2897                 break;
2898         case MSR_IA32_SYSENTER_EIP:
2899                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2900                 /*
2901                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2902                  * when we spoof an Intel vendor ID (for cross vendor migration).
2903                  * In this case we use this intercept to track the high
2904                  * 32 bit part of these msrs to support Intel's
2905                  * implementation of SYSENTER/SYSEXIT.
2906                  */
2907                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2908                 break;
2909         case MSR_IA32_SYSENTER_ESP:
2910                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2911                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2912                 break;
2913         case MSR_TSC_AUX:
2914                 /*
2915                  * TSC_AUX is usually changed only during boot and never read
2916                  * directly.  Intercept TSC_AUX instead of exposing it to the
2917                  * guest via direct_access_msrs, and switch it via user return.
2918                  */
2919                 preempt_disable();
2920                 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2921                 preempt_enable();
2922                 if (r)
2923                         return 1;
2924
2925                 svm->tsc_aux = data;
2926                 break;
2927         case MSR_IA32_DEBUGCTLMSR:
2928                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2929                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2930                                     __func__, data);
2931                         break;
2932                 }
2933                 if (data & DEBUGCTL_RESERVED_BITS)
2934                         return 1;
2935
2936                 svm->vmcb->save.dbgctl = data;
2937                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2938                 if (data & (1ULL<<0))
2939                         svm_enable_lbrv(vcpu);
2940                 else
2941                         svm_disable_lbrv(vcpu);
2942                 break;
2943         case MSR_VM_HSAVE_PA:
2944                 svm->nested.hsave_msr = data;
2945                 break;
2946         case MSR_VM_CR:
2947                 return svm_set_vm_cr(vcpu, data);
2948         case MSR_VM_IGNNE:
2949                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2950                 break;
2951         case MSR_F10H_DECFG: {
2952                 struct kvm_msr_entry msr_entry;
2953
2954                 msr_entry.index = msr->index;
2955                 if (svm_get_msr_feature(&msr_entry))
2956                         return 1;
2957
2958                 /* Check the supported bits */
2959                 if (data & ~msr_entry.data)
2960                         return 1;
2961
2962                 /* Don't allow the guest to change a bit, #GP */
2963                 if (!msr->host_initiated && (data ^ msr_entry.data))
2964                         return 1;
2965
2966                 svm->msr_decfg = data;
2967                 break;
2968         }
2969         case MSR_IA32_APICBASE:
2970                 if (kvm_vcpu_apicv_active(vcpu))
2971                         avic_update_vapic_bar(to_svm(vcpu), data);
2972                 fallthrough;
2973         default:
2974                 return kvm_set_msr_common(vcpu, msr);
2975         }
2976         return 0;
2977 }
2978
2979 static int msr_interception(struct kvm_vcpu *vcpu)
2980 {
2981         if (to_svm(vcpu)->vmcb->control.exit_info_1)
2982                 return kvm_emulate_wrmsr(vcpu);
2983         else
2984                 return kvm_emulate_rdmsr(vcpu);
2985 }
2986
2987 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2988 {
2989         kvm_make_request(KVM_REQ_EVENT, vcpu);
2990         svm_clear_vintr(to_svm(vcpu));
2991
2992         /*
2993          * For AVIC, the only reason to end up here is ExtINTs.
2994          * In this case AVIC was temporarily disabled for
2995          * requesting the IRQ window and we have to re-enable it.
2996          */
2997         svm_toggle_avic_for_irq_window(vcpu, true);
2998
2999         ++vcpu->stat.irq_window_exits;
3000         return 1;
3001 }
3002
3003 static int pause_interception(struct kvm_vcpu *vcpu)
3004 {
3005         bool in_kernel;
3006
3007         /*
3008          * CPL is not made available for an SEV-ES guest, therefore
3009          * vcpu->arch.preempted_in_kernel can never be true.  Just
3010          * set in_kernel to false as well.
3011          */
3012         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3013
3014         if (!kvm_pause_in_guest(vcpu->kvm))
3015                 grow_ple_window(vcpu);
3016
3017         kvm_vcpu_on_spin(vcpu, in_kernel);
3018         return kvm_skip_emulated_instruction(vcpu);
3019 }
3020
3021 static int invpcid_interception(struct kvm_vcpu *vcpu)
3022 {
3023         struct vcpu_svm *svm = to_svm(vcpu);
3024         unsigned long type;
3025         gva_t gva;
3026
3027         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3028                 kvm_queue_exception(vcpu, UD_VECTOR);
3029                 return 1;
3030         }
3031
3032         /*
3033          * For an INVPCID intercept:
3034          * EXITINFO1 provides the linear address of the memory operand.
3035          * EXITINFO2 provides the contents of the register operand.
3036          */
3037         type = svm->vmcb->control.exit_info_2;
3038         gva = svm->vmcb->control.exit_info_1;
3039
3040         if (type > 3) {
3041                 kvm_inject_gp(vcpu, 0);
3042                 return 1;
3043         }
3044
3045         return kvm_handle_invpcid(vcpu, type, gva);
3046 }
3047
3048 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3049         [SVM_EXIT_READ_CR0]                     = cr_interception,
3050         [SVM_EXIT_READ_CR3]                     = cr_interception,
3051         [SVM_EXIT_READ_CR4]                     = cr_interception,
3052         [SVM_EXIT_READ_CR8]                     = cr_interception,
3053         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3054         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3055         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3056         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3057         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3058         [SVM_EXIT_READ_DR0]                     = dr_interception,
3059         [SVM_EXIT_READ_DR1]                     = dr_interception,
3060         [SVM_EXIT_READ_DR2]                     = dr_interception,
3061         [SVM_EXIT_READ_DR3]                     = dr_interception,
3062         [SVM_EXIT_READ_DR4]                     = dr_interception,
3063         [SVM_EXIT_READ_DR5]                     = dr_interception,
3064         [SVM_EXIT_READ_DR6]                     = dr_interception,
3065         [SVM_EXIT_READ_DR7]                     = dr_interception,
3066         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3067         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3068         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3069         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3070         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3071         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3072         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3073         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3074         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3075         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3076         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3077         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3078         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3079         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3080         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3081         [SVM_EXIT_INTR]                         = intr_interception,
3082         [SVM_EXIT_NMI]                          = nmi_interception,
3083         [SVM_EXIT_SMI]                          = kvm_emulate_as_nop,
3084         [SVM_EXIT_INIT]                         = kvm_emulate_as_nop,
3085         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3086         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3087         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3088         [SVM_EXIT_IRET]                         = iret_interception,
3089         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3090         [SVM_EXIT_PAUSE]                        = pause_interception,
3091         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3092         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3093         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3094         [SVM_EXIT_IOIO]                         = io_interception,
3095         [SVM_EXIT_MSR]                          = msr_interception,
3096         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3097         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3098         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3099         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3100         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3101         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3102         [SVM_EXIT_STGI]                         = stgi_interception,
3103         [SVM_EXIT_CLGI]                         = clgi_interception,
3104         [SVM_EXIT_SKINIT]                       = skinit_interception,
3105         [SVM_EXIT_RDTSCP]                       = kvm_handle_invalid_op,
3106         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3107         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3108         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3109         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3110         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3111         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3112         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3113         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3114         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3115         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3116         [SVM_EXIT_NPF]                          = npf_interception,
3117         [SVM_EXIT_RSM]                          = rsm_interception,
3118         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3119         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3120         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3121 };
3122
3123 static void dump_vmcb(struct kvm_vcpu *vcpu)
3124 {
3125         struct vcpu_svm *svm = to_svm(vcpu);
3126         struct vmcb_control_area *control = &svm->vmcb->control;
3127         struct vmcb_save_area *save = &svm->vmcb->save;
3128         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3129
3130         if (!dump_invalid_vmcb) {
3131                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3132                 return;
3133         }
3134
3135         pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3136                svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3137         pr_err("VMCB Control Area:\n");
3138         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3139         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3140         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3141         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3142         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3143         pr_err("%-20s%08x %08x\n", "intercepts:",
3144               control->intercepts[INTERCEPT_WORD3],
3145                control->intercepts[INTERCEPT_WORD4]);
3146         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3147         pr_err("%-20s%d\n", "pause filter threshold:",
3148                control->pause_filter_thresh);
3149         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3150         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3151         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3152         pr_err("%-20s%d\n", "asid:", control->asid);
3153         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3154         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3155         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3156         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3157         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3158         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3159         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3160         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3161         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3162         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3163         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3164         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3165         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3166         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3167         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3168         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3169         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3170         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3171         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3172         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3173         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3174         pr_err("VMCB State Save Area:\n");
3175         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3176                "es:",
3177                save->es.selector, save->es.attrib,
3178                save->es.limit, save->es.base);
3179         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3180                "cs:",
3181                save->cs.selector, save->cs.attrib,
3182                save->cs.limit, save->cs.base);
3183         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3184                "ss:",
3185                save->ss.selector, save->ss.attrib,
3186                save->ss.limit, save->ss.base);
3187         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3188                "ds:",
3189                save->ds.selector, save->ds.attrib,
3190                save->ds.limit, save->ds.base);
3191         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3192                "fs:",
3193                save01->fs.selector, save01->fs.attrib,
3194                save01->fs.limit, save01->fs.base);
3195         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3196                "gs:",
3197                save01->gs.selector, save01->gs.attrib,
3198                save01->gs.limit, save01->gs.base);
3199         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3200                "gdtr:",
3201                save->gdtr.selector, save->gdtr.attrib,
3202                save->gdtr.limit, save->gdtr.base);
3203         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3204                "ldtr:",
3205                save01->ldtr.selector, save01->ldtr.attrib,
3206                save01->ldtr.limit, save01->ldtr.base);
3207         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3208                "idtr:",
3209                save->idtr.selector, save->idtr.attrib,
3210                save->idtr.limit, save->idtr.base);
3211         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3212                "tr:",
3213                save01->tr.selector, save01->tr.attrib,
3214                save01->tr.limit, save01->tr.base);
3215         pr_err("cpl:            %d                efer:         %016llx\n",
3216                 save->cpl, save->efer);
3217         pr_err("%-15s %016llx %-13s %016llx\n",
3218                "cr0:", save->cr0, "cr2:", save->cr2);
3219         pr_err("%-15s %016llx %-13s %016llx\n",
3220                "cr3:", save->cr3, "cr4:", save->cr4);
3221         pr_err("%-15s %016llx %-13s %016llx\n",
3222                "dr6:", save->dr6, "dr7:", save->dr7);
3223         pr_err("%-15s %016llx %-13s %016llx\n",
3224                "rip:", save->rip, "rflags:", save->rflags);
3225         pr_err("%-15s %016llx %-13s %016llx\n",
3226                "rsp:", save->rsp, "rax:", save->rax);
3227         pr_err("%-15s %016llx %-13s %016llx\n",
3228                "star:", save01->star, "lstar:", save01->lstar);
3229         pr_err("%-15s %016llx %-13s %016llx\n",
3230                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3231         pr_err("%-15s %016llx %-13s %016llx\n",
3232                "kernel_gs_base:", save01->kernel_gs_base,
3233                "sysenter_cs:", save01->sysenter_cs);
3234         pr_err("%-15s %016llx %-13s %016llx\n",
3235                "sysenter_esp:", save01->sysenter_esp,
3236                "sysenter_eip:", save01->sysenter_eip);
3237         pr_err("%-15s %016llx %-13s %016llx\n",
3238                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3239         pr_err("%-15s %016llx %-13s %016llx\n",
3240                "br_from:", save->br_from, "br_to:", save->br_to);
3241         pr_err("%-15s %016llx %-13s %016llx\n",
3242                "excp_from:", save->last_excp_from,
3243                "excp_to:", save->last_excp_to);
3244 }
3245
3246 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3247 {
3248         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3249             svm_exit_handlers[exit_code])
3250                 return 0;
3251
3252         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3253         dump_vmcb(vcpu);
3254         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3255         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3256         vcpu->run->internal.ndata = 2;
3257         vcpu->run->internal.data[0] = exit_code;
3258         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3259
3260         return -EINVAL;
3261 }
3262
3263 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3264 {
3265         if (svm_handle_invalid_exit(vcpu, exit_code))
3266                 return 0;
3267
3268 #ifdef CONFIG_RETPOLINE
3269         if (exit_code == SVM_EXIT_MSR)
3270                 return msr_interception(vcpu);
3271         else if (exit_code == SVM_EXIT_VINTR)
3272                 return interrupt_window_interception(vcpu);
3273         else if (exit_code == SVM_EXIT_INTR)
3274                 return intr_interception(vcpu);
3275         else if (exit_code == SVM_EXIT_HLT)
3276                 return kvm_emulate_halt(vcpu);
3277         else if (exit_code == SVM_EXIT_NPF)
3278                 return npf_interception(vcpu);
3279 #endif
3280         return svm_exit_handlers[exit_code](vcpu);
3281 }
3282
3283 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3284                               u32 *intr_info, u32 *error_code)
3285 {
3286         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3287
3288         *info1 = control->exit_info_1;
3289         *info2 = control->exit_info_2;
3290         *intr_info = control->exit_int_info;
3291         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3292             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3293                 *error_code = control->exit_int_info_err;
3294         else
3295                 *error_code = 0;
3296 }
3297
3298 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3299 {
3300         struct vcpu_svm *svm = to_svm(vcpu);
3301         struct kvm_run *kvm_run = vcpu->run;
3302         u32 exit_code = svm->vmcb->control.exit_code;
3303
3304         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3305
3306         /* SEV-ES guests must use the CR write traps to track CR registers. */
3307         if (!sev_es_guest(vcpu->kvm)) {
3308                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3309                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3310                 if (npt_enabled)
3311                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3312         }
3313
3314         if (is_guest_mode(vcpu)) {
3315                 int vmexit;
3316
3317                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3318
3319                 vmexit = nested_svm_exit_special(svm);
3320
3321                 if (vmexit == NESTED_EXIT_CONTINUE)
3322                         vmexit = nested_svm_exit_handled(svm);
3323
3324                 if (vmexit == NESTED_EXIT_DONE)
3325                         return 1;
3326         }
3327
3328         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3329                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3330                 kvm_run->fail_entry.hardware_entry_failure_reason
3331                         = svm->vmcb->control.exit_code;
3332                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3333                 dump_vmcb(vcpu);
3334                 return 0;
3335         }
3336
3337         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3338             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3339             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3340             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3341                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3342                        "exit_code 0x%x\n",
3343                        __func__, svm->vmcb->control.exit_int_info,
3344                        exit_code);
3345
3346         if (exit_fastpath != EXIT_FASTPATH_NONE)
3347                 return 1;
3348
3349         return svm_invoke_exit_handler(vcpu, exit_code);
3350 }
3351
3352 static void reload_tss(struct kvm_vcpu *vcpu)
3353 {
3354         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3355
3356         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3357         load_TR_desc();
3358 }
3359
3360 static void pre_svm_run(struct kvm_vcpu *vcpu)
3361 {
3362         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3363         struct vcpu_svm *svm = to_svm(vcpu);
3364
3365         /*
3366          * If the previous vmrun of the vmcb occurred on a different physical
3367          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3368          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3369          */
3370         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3371                 svm->current_vmcb->asid_generation = 0;
3372                 vmcb_mark_all_dirty(svm->vmcb);
3373                 svm->current_vmcb->cpu = vcpu->cpu;
3374         }
3375
3376         if (sev_guest(vcpu->kvm))
3377                 return pre_sev_run(svm, vcpu->cpu);
3378
3379         /* FIXME: handle wraparound of asid_generation */
3380         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3381                 new_asid(svm, sd);
3382 }
3383
3384 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3385 {
3386         struct vcpu_svm *svm = to_svm(vcpu);
3387
3388         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3389         vcpu->arch.hflags |= HF_NMI_MASK;
3390         if (!sev_es_guest(vcpu->kvm))
3391                 svm_set_intercept(svm, INTERCEPT_IRET);
3392         ++vcpu->stat.nmi_injections;
3393 }
3394
3395 static void svm_set_irq(struct kvm_vcpu *vcpu)
3396 {
3397         struct vcpu_svm *svm = to_svm(vcpu);
3398
3399         BUG_ON(!(gif_set(svm)));
3400
3401         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3402         ++vcpu->stat.irq_injections;
3403
3404         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3405                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3406 }
3407
3408 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3409 {
3410         struct vcpu_svm *svm = to_svm(vcpu);
3411
3412         /*
3413          * SEV-ES guests must always keep the CR intercepts cleared. CR
3414          * tracking is done using the CR write traps.
3415          */
3416         if (sev_es_guest(vcpu->kvm))
3417                 return;
3418
3419         if (nested_svm_virtualize_tpr(vcpu))
3420                 return;
3421
3422         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3423
3424         if (irr == -1)
3425                 return;
3426
3427         if (tpr >= irr)
3428                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3429 }
3430
3431 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3432 {
3433         struct vcpu_svm *svm = to_svm(vcpu);
3434         struct vmcb *vmcb = svm->vmcb;
3435         bool ret;
3436
3437         if (!gif_set(svm))
3438                 return true;
3439
3440         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3441                 return false;
3442
3443         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3444               (vcpu->arch.hflags & HF_NMI_MASK);
3445
3446         return ret;
3447 }
3448
3449 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3450 {
3451         struct vcpu_svm *svm = to_svm(vcpu);
3452         if (svm->nested.nested_run_pending)
3453                 return -EBUSY;
3454
3455         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3456         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3457                 return -EBUSY;
3458
3459         return !svm_nmi_blocked(vcpu);
3460 }
3461
3462 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3463 {
3464         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3465 }
3466
3467 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3468 {
3469         struct vcpu_svm *svm = to_svm(vcpu);
3470
3471         if (masked) {
3472                 vcpu->arch.hflags |= HF_NMI_MASK;
3473                 if (!sev_es_guest(vcpu->kvm))
3474                         svm_set_intercept(svm, INTERCEPT_IRET);
3475         } else {
3476                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3477                 if (!sev_es_guest(vcpu->kvm))
3478                         svm_clr_intercept(svm, INTERCEPT_IRET);
3479         }
3480 }
3481
3482 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3483 {
3484         struct vcpu_svm *svm = to_svm(vcpu);
3485         struct vmcb *vmcb = svm->vmcb;
3486
3487         if (!gif_set(svm))
3488                 return true;
3489
3490         if (sev_es_guest(vcpu->kvm)) {
3491                 /*
3492                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3493                  * bit to determine the state of the IF flag.
3494                  */
3495                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3496                         return true;
3497         } else if (is_guest_mode(vcpu)) {
3498                 /* As long as interrupts are being delivered...  */
3499                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3500                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3501                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3502                         return true;
3503
3504                 /* ... vmexits aren't blocked by the interrupt shadow  */
3505                 if (nested_exit_on_intr(svm))
3506                         return false;
3507         } else {
3508                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3509                         return true;
3510         }
3511
3512         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3513 }
3514
3515 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3516 {
3517         struct vcpu_svm *svm = to_svm(vcpu);
3518         if (svm->nested.nested_run_pending)
3519                 return -EBUSY;
3520
3521         /*
3522          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3523          * e.g. if the IRQ arrived asynchronously after checking nested events.
3524          */
3525         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3526                 return -EBUSY;
3527
3528         return !svm_interrupt_blocked(vcpu);
3529 }
3530
3531 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3532 {
3533         struct vcpu_svm *svm = to_svm(vcpu);
3534
3535         /*
3536          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3537          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3538          * get that intercept, this function will be called again though and
3539          * we'll get the vintr intercept. However, if the vGIF feature is
3540          * enabled, the STGI interception will not occur. Enable the irq
3541          * window under the assumption that the hardware will set the GIF.
3542          */
3543         if (vgif_enabled(svm) || gif_set(svm)) {
3544                 /*
3545                  * IRQ window is not needed when AVIC is enabled,
3546                  * unless we have pending ExtINT since it cannot be injected
3547                  * via AVIC. In such case, we need to temporarily disable AVIC,
3548                  * and fallback to injecting IRQ via V_IRQ.
3549                  */
3550                 svm_toggle_avic_for_irq_window(vcpu, false);
3551                 svm_set_vintr(svm);
3552         }
3553 }
3554
3555 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3556 {
3557         struct vcpu_svm *svm = to_svm(vcpu);
3558
3559         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3560                 return; /* IRET will cause a vm exit */
3561
3562         if (!gif_set(svm)) {
3563                 if (vgif_enabled(svm))
3564                         svm_set_intercept(svm, INTERCEPT_STGI);
3565                 return; /* STGI will cause a vm exit */
3566         }
3567
3568         /*
3569          * Something prevents NMI from been injected. Single step over possible
3570          * problem (IRET or exception injection or interrupt shadow)
3571          */
3572         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3573         svm->nmi_singlestep = true;
3574         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3575 }
3576
3577 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3578 {
3579         return 0;
3580 }
3581
3582 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3583 {
3584         return 0;
3585 }
3586
3587 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3588 {
3589         struct vcpu_svm *svm = to_svm(vcpu);
3590
3591         /*
3592          * Flush only the current ASID even if the TLB flush was invoked via
3593          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3594          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3595          * unconditionally does a TLB flush on both nested VM-Enter and nested
3596          * VM-Exit (via kvm_mmu_reset_context()).
3597          */
3598         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3599                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3600         else
3601                 svm->current_vmcb->asid_generation--;
3602 }
3603
3604 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3605 {
3606         struct vcpu_svm *svm = to_svm(vcpu);
3607
3608         invlpga(gva, svm->vmcb->control.asid);
3609 }
3610
3611 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3612 {
3613         struct vcpu_svm *svm = to_svm(vcpu);
3614
3615         if (nested_svm_virtualize_tpr(vcpu))
3616                 return;
3617
3618         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3619                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3620                 kvm_set_cr8(vcpu, cr8);
3621         }
3622 }
3623
3624 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3625 {
3626         struct vcpu_svm *svm = to_svm(vcpu);
3627         u64 cr8;
3628
3629         if (nested_svm_virtualize_tpr(vcpu) ||
3630             kvm_vcpu_apicv_active(vcpu))
3631                 return;
3632
3633         cr8 = kvm_get_cr8(vcpu);
3634         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3635         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3636 }
3637
3638 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3639 {
3640         struct vcpu_svm *svm = to_svm(vcpu);
3641         u8 vector;
3642         int type;
3643         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3644         unsigned int3_injected = svm->int3_injected;
3645
3646         svm->int3_injected = 0;
3647
3648         /*
3649          * If we've made progress since setting HF_IRET_MASK, we've
3650          * executed an IRET and can allow NMI injection.
3651          */
3652         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3653             (sev_es_guest(vcpu->kvm) ||
3654              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3655                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3656                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3657         }
3658
3659         vcpu->arch.nmi_injected = false;
3660         kvm_clear_exception_queue(vcpu);
3661         kvm_clear_interrupt_queue(vcpu);
3662
3663         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3664                 return;
3665
3666         kvm_make_request(KVM_REQ_EVENT, vcpu);
3667
3668         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3669         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3670
3671         switch (type) {
3672         case SVM_EXITINTINFO_TYPE_NMI:
3673                 vcpu->arch.nmi_injected = true;
3674                 break;
3675         case SVM_EXITINTINFO_TYPE_EXEPT:
3676                 /*
3677                  * Never re-inject a #VC exception.
3678                  */
3679                 if (vector == X86_TRAP_VC)
3680                         break;
3681
3682                 /*
3683                  * In case of software exceptions, do not reinject the vector,
3684                  * but re-execute the instruction instead. Rewind RIP first
3685                  * if we emulated INT3 before.
3686                  */
3687                 if (kvm_exception_is_soft(vector)) {
3688                         if (vector == BP_VECTOR && int3_injected &&
3689                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3690                                 kvm_rip_write(vcpu,
3691                                               kvm_rip_read(vcpu) - int3_injected);
3692                         break;
3693                 }
3694                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3695                         u32 err = svm->vmcb->control.exit_int_info_err;
3696                         kvm_requeue_exception_e(vcpu, vector, err);
3697
3698                 } else
3699                         kvm_requeue_exception(vcpu, vector);
3700                 break;
3701         case SVM_EXITINTINFO_TYPE_INTR:
3702                 kvm_queue_interrupt(vcpu, vector, false);
3703                 break;
3704         default:
3705                 break;
3706         }
3707 }
3708
3709 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3710 {
3711         struct vcpu_svm *svm = to_svm(vcpu);
3712         struct vmcb_control_area *control = &svm->vmcb->control;
3713
3714         control->exit_int_info = control->event_inj;
3715         control->exit_int_info_err = control->event_inj_err;
3716         control->event_inj = 0;
3717         svm_complete_interrupts(vcpu);
3718 }
3719
3720 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3721 {
3722         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3723             to_svm(vcpu)->vmcb->control.exit_info_1)
3724                 return handle_fastpath_set_msr_irqoff(vcpu);
3725
3726         return EXIT_FASTPATH_NONE;
3727 }
3728
3729 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3730 {
3731         struct vcpu_svm *svm = to_svm(vcpu);
3732         unsigned long vmcb_pa = svm->current_vmcb->pa;
3733
3734         kvm_guest_enter_irqoff();
3735
3736         if (sev_es_guest(vcpu->kvm)) {
3737                 __svm_sev_es_vcpu_run(vmcb_pa);
3738         } else {
3739                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3740
3741                 /*
3742                  * Use a single vmcb (vmcb01 because it's always valid) for
3743                  * context switching guest state via VMLOAD/VMSAVE, that way
3744                  * the state doesn't need to be copied between vmcb01 and
3745                  * vmcb02 when switching vmcbs for nested virtualization.
3746                  */
3747                 vmload(svm->vmcb01.pa);
3748                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3749                 vmsave(svm->vmcb01.pa);
3750
3751                 vmload(__sme_page_pa(sd->save_area));
3752         }
3753
3754         kvm_guest_exit_irqoff();
3755 }
3756
3757 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3758 {
3759         struct vcpu_svm *svm = to_svm(vcpu);
3760
3761         trace_kvm_entry(vcpu);
3762
3763         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3764         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3765         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3766
3767         /*
3768          * Disable singlestep if we're injecting an interrupt/exception.
3769          * We don't want our modified rflags to be pushed on the stack where
3770          * we might not be able to easily reset them if we disabled NMI
3771          * singlestep later.
3772          */
3773         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3774                 /*
3775                  * Event injection happens before external interrupts cause a
3776                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3777                  * is enough to force an immediate vmexit.
3778                  */
3779                 disable_nmi_singlestep(svm);
3780                 smp_send_reschedule(vcpu->cpu);
3781         }
3782
3783         pre_svm_run(vcpu);
3784
3785         sync_lapic_to_cr8(vcpu);
3786
3787         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3788                 svm->vmcb->control.asid = svm->asid;
3789                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3790         }
3791         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3792
3793         svm_hv_update_vp_id(svm->vmcb, vcpu);
3794
3795         /*
3796          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3797          * of a #DB.
3798          */
3799         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3800                 svm_set_dr6(svm, vcpu->arch.dr6);
3801         else
3802                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3803
3804         clgi();
3805         kvm_load_guest_xsave_state(vcpu);
3806
3807         kvm_wait_lapic_expire(vcpu);
3808
3809         /*
3810          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3811          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3812          * is no need to worry about the conditional branch over the wrmsr
3813          * being speculatively taken.
3814          */
3815         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3816                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3817
3818         svm_vcpu_enter_exit(vcpu);
3819
3820         /*
3821          * We do not use IBRS in the kernel. If this vCPU has used the
3822          * SPEC_CTRL MSR it may have left it on; save the value and
3823          * turn it off. This is much more efficient than blindly adding
3824          * it to the atomic save/restore list. Especially as the former
3825          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3826          *
3827          * For non-nested case:
3828          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3829          * save it.
3830          *
3831          * For nested case:
3832          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3833          * save it.
3834          */
3835         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3836             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3837                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3838
3839         if (!sev_es_guest(vcpu->kvm))
3840                 reload_tss(vcpu);
3841
3842         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3843                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3844
3845         if (!sev_es_guest(vcpu->kvm)) {
3846                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3847                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3848                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3849                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3850         }
3851
3852         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3853                 kvm_before_interrupt(vcpu);
3854
3855         kvm_load_host_xsave_state(vcpu);
3856         stgi();
3857
3858         /* Any pending NMI will happen here */
3859
3860         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3861                 kvm_after_interrupt(vcpu);
3862
3863         sync_cr8_to_lapic(vcpu);
3864
3865         svm->next_rip = 0;
3866         if (is_guest_mode(vcpu)) {
3867                 nested_sync_control_from_vmcb02(svm);
3868
3869                 /* Track VMRUNs that have made past consistency checking */
3870                 if (svm->nested.nested_run_pending &&
3871                     svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3872                         ++vcpu->stat.nested_run;
3873
3874                 svm->nested.nested_run_pending = 0;
3875         }
3876
3877         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3878         vmcb_mark_all_clean(svm->vmcb);
3879
3880         /* if exit due to PF check for async PF */
3881         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3882                 vcpu->arch.apf.host_apf_flags =
3883                         kvm_read_and_reset_apf_flags();
3884
3885         if (npt_enabled)
3886                 kvm_register_clear_available(vcpu, VCPU_EXREG_PDPTR);
3887
3888         /*
3889          * We need to handle MC intercepts here before the vcpu has a chance to
3890          * change the physical cpu
3891          */
3892         if (unlikely(svm->vmcb->control.exit_code ==
3893                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3894                 svm_handle_mce(vcpu);
3895
3896         svm_complete_interrupts(vcpu);
3897
3898         if (is_guest_mode(vcpu))
3899                 return EXIT_FASTPATH_NONE;
3900
3901         return svm_exit_handlers_fastpath(vcpu);
3902 }
3903
3904 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3905                              int root_level)
3906 {
3907         struct vcpu_svm *svm = to_svm(vcpu);
3908         unsigned long cr3;
3909
3910         if (npt_enabled) {
3911                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3912                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3913
3914                 hv_track_root_tdp(vcpu, root_hpa);
3915
3916                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3917                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3918                         return;
3919                 cr3 = vcpu->arch.cr3;
3920         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3921                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3922         } else {
3923                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3924                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3925                 cr3 = root_hpa;
3926         }
3927
3928         svm->vmcb->save.cr3 = cr3;
3929         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3930 }
3931
3932 static int is_disabled(void)
3933 {
3934         u64 vm_cr;
3935
3936         rdmsrl(MSR_VM_CR, vm_cr);
3937         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3938                 return 1;
3939
3940         return 0;
3941 }
3942
3943 static void
3944 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3945 {
3946         /*
3947          * Patch in the VMMCALL instruction:
3948          */
3949         hypercall[0] = 0x0f;
3950         hypercall[1] = 0x01;
3951         hypercall[2] = 0xd9;
3952 }
3953
3954 static int __init svm_check_processor_compat(void)
3955 {
3956         return 0;
3957 }
3958
3959 static bool svm_cpu_has_accelerated_tpr(void)
3960 {
3961         return false;
3962 }
3963
3964 /*
3965  * The kvm parameter can be NULL (module initialization, or invocation before
3966  * VM creation). Be sure to check the kvm parameter before using it.
3967  */
3968 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3969 {
3970         switch (index) {
3971         case MSR_IA32_MCG_EXT_CTL:
3972         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3973                 return false;
3974         case MSR_IA32_SMBASE:
3975                 /* SEV-ES guests do not support SMM, so report false */
3976                 if (kvm && sev_es_guest(kvm))
3977                         return false;
3978                 break;
3979         default:
3980                 break;
3981         }
3982
3983         return true;
3984 }
3985
3986 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3987 {
3988         return 0;
3989 }
3990
3991 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3992 {
3993         struct vcpu_svm *svm = to_svm(vcpu);
3994         struct kvm_cpuid_entry2 *best;
3995
3996         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3997                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3998                                     boot_cpu_has(X86_FEATURE_XSAVES);
3999
4000         /* Update nrips enabled cache */
4001         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4002                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4003
4004         svm_recalc_instruction_intercepts(vcpu, svm);
4005
4006         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4007         if (sev_guest(vcpu->kvm)) {
4008                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4009                 if (best)
4010                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4011         }
4012
4013         if (kvm_vcpu_apicv_active(vcpu)) {
4014                 /*
4015                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4016                  * is exposed to the guest, disable AVIC.
4017                  */
4018                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4019                         kvm_request_apicv_update(vcpu->kvm, false,
4020                                                  APICV_INHIBIT_REASON_X2APIC);
4021
4022                 /*
4023                  * Currently, AVIC does not work with nested virtualization.
4024                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4025                  */
4026                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4027                         kvm_request_apicv_update(vcpu->kvm, false,
4028                                                  APICV_INHIBIT_REASON_NESTED);
4029         }
4030
4031         if (guest_cpuid_is_intel(vcpu)) {
4032                 /*
4033                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
4034                  * accesses because the processor only stores 32 bits.
4035                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4036                  */
4037                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4038                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4039                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4040
4041                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4042                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4043         } else {
4044                 /*
4045                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4046                  * in VMCB and clear intercepts to avoid #VMEXIT.
4047                  */
4048                 if (vls) {
4049                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4050                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4051                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4052                 }
4053                 /* No need to intercept these MSRs */
4054                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4055                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4056         }
4057 }
4058
4059 static bool svm_has_wbinvd_exit(void)
4060 {
4061         return true;
4062 }
4063
4064 #define PRE_EX(exit)  { .exit_code = (exit), \
4065                         .stage = X86_ICPT_PRE_EXCEPT, }
4066 #define POST_EX(exit) { .exit_code = (exit), \
4067                         .stage = X86_ICPT_POST_EXCEPT, }
4068 #define POST_MEM(exit) { .exit_code = (exit), \
4069                         .stage = X86_ICPT_POST_MEMACCESS, }
4070
4071 static const struct __x86_intercept {
4072         u32 exit_code;
4073         enum x86_intercept_stage stage;
4074 } x86_intercept_map[] = {
4075         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4076         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4077         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4078         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4079         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4080         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4081         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4082         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4083         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4084         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4085         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4086         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4087         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4088         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4089         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4090         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4091         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4092         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4093         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4094         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4095         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4096         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4097         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4098         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4099         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4100         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4101         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4102         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4103         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4104         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4105         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4106         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4107         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4108         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4109         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4110         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4111         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4112         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4113         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4114         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4115         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4116         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4117         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4118         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4119         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4120         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4121         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4122 };
4123
4124 #undef PRE_EX
4125 #undef POST_EX
4126 #undef POST_MEM
4127
4128 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4129                                struct x86_instruction_info *info,
4130                                enum x86_intercept_stage stage,
4131                                struct x86_exception *exception)
4132 {
4133         struct vcpu_svm *svm = to_svm(vcpu);
4134         int vmexit, ret = X86EMUL_CONTINUE;
4135         struct __x86_intercept icpt_info;
4136         struct vmcb *vmcb = svm->vmcb;
4137
4138         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4139                 goto out;
4140
4141         icpt_info = x86_intercept_map[info->intercept];
4142
4143         if (stage != icpt_info.stage)
4144                 goto out;
4145
4146         switch (icpt_info.exit_code) {
4147         case SVM_EXIT_READ_CR0:
4148                 if (info->intercept == x86_intercept_cr_read)
4149                         icpt_info.exit_code += info->modrm_reg;
4150                 break;
4151         case SVM_EXIT_WRITE_CR0: {
4152                 unsigned long cr0, val;
4153
4154                 if (info->intercept == x86_intercept_cr_write)
4155                         icpt_info.exit_code += info->modrm_reg;
4156
4157                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4158                     info->intercept == x86_intercept_clts)
4159                         break;
4160
4161                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4162                                         INTERCEPT_SELECTIVE_CR0)))
4163                         break;
4164
4165                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4166                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4167
4168                 if (info->intercept == x86_intercept_lmsw) {
4169                         cr0 &= 0xfUL;
4170                         val &= 0xfUL;
4171                         /* lmsw can't clear PE - catch this here */
4172                         if (cr0 & X86_CR0_PE)
4173                                 val |= X86_CR0_PE;
4174                 }
4175
4176                 if (cr0 ^ val)
4177                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4178
4179                 break;
4180         }
4181         case SVM_EXIT_READ_DR0:
4182         case SVM_EXIT_WRITE_DR0:
4183                 icpt_info.exit_code += info->modrm_reg;
4184                 break;
4185         case SVM_EXIT_MSR:
4186                 if (info->intercept == x86_intercept_wrmsr)
4187                         vmcb->control.exit_info_1 = 1;
4188                 else
4189                         vmcb->control.exit_info_1 = 0;
4190                 break;
4191         case SVM_EXIT_PAUSE:
4192                 /*
4193                  * We get this for NOP only, but pause
4194                  * is rep not, check this here
4195                  */
4196                 if (info->rep_prefix != REPE_PREFIX)
4197                         goto out;
4198                 break;
4199         case SVM_EXIT_IOIO: {
4200                 u64 exit_info;
4201                 u32 bytes;
4202
4203                 if (info->intercept == x86_intercept_in ||
4204                     info->intercept == x86_intercept_ins) {
4205                         exit_info = ((info->src_val & 0xffff) << 16) |
4206                                 SVM_IOIO_TYPE_MASK;
4207                         bytes = info->dst_bytes;
4208                 } else {
4209                         exit_info = (info->dst_val & 0xffff) << 16;
4210                         bytes = info->src_bytes;
4211                 }
4212
4213                 if (info->intercept == x86_intercept_outs ||
4214                     info->intercept == x86_intercept_ins)
4215                         exit_info |= SVM_IOIO_STR_MASK;
4216
4217                 if (info->rep_prefix)
4218                         exit_info |= SVM_IOIO_REP_MASK;
4219
4220                 bytes = min(bytes, 4u);
4221
4222                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4223
4224                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4225
4226                 vmcb->control.exit_info_1 = exit_info;
4227                 vmcb->control.exit_info_2 = info->next_rip;
4228
4229                 break;
4230         }
4231         default:
4232                 break;
4233         }
4234
4235         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4236         if (static_cpu_has(X86_FEATURE_NRIPS))
4237                 vmcb->control.next_rip  = info->next_rip;
4238         vmcb->control.exit_code = icpt_info.exit_code;
4239         vmexit = nested_svm_exit_handled(svm);
4240
4241         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4242                                            : X86EMUL_CONTINUE;
4243
4244 out:
4245         return ret;
4246 }
4247
4248 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4249 {
4250 }
4251
4252 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4253 {
4254         if (!kvm_pause_in_guest(vcpu->kvm))
4255                 shrink_ple_window(vcpu);
4256 }
4257
4258 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4259 {
4260         /* [63:9] are reserved. */
4261         vcpu->arch.mcg_cap &= 0x1ff;
4262 }
4263
4264 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4265 {
4266         struct vcpu_svm *svm = to_svm(vcpu);
4267
4268         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4269         if (!gif_set(svm))
4270                 return true;
4271
4272         return is_smm(vcpu);
4273 }
4274
4275 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4276 {
4277         struct vcpu_svm *svm = to_svm(vcpu);
4278         if (svm->nested.nested_run_pending)
4279                 return -EBUSY;
4280
4281         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4282         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4283                 return -EBUSY;
4284
4285         return !svm_smi_blocked(vcpu);
4286 }
4287
4288 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4289 {
4290         struct vcpu_svm *svm = to_svm(vcpu);
4291         int ret;
4292
4293         if (is_guest_mode(vcpu)) {
4294                 /* FED8h - SVM Guest */
4295                 put_smstate(u64, smstate, 0x7ed8, 1);
4296                 /* FEE0h - SVM Guest VMCB Physical Address */
4297                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4298
4299                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4300                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4301                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4302
4303                 ret = nested_svm_vmexit(svm);
4304                 if (ret)
4305                         return ret;
4306         }
4307         return 0;
4308 }
4309
4310 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4311 {
4312         struct vcpu_svm *svm = to_svm(vcpu);
4313         struct kvm_host_map map;
4314         int ret = 0;
4315
4316         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4317                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4318                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4319                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4320
4321                 if (guest) {
4322                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4323                                 return 1;
4324
4325                         if (!(saved_efer & EFER_SVME))
4326                                 return 1;
4327
4328                         if (kvm_vcpu_map(vcpu,
4329                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4330                                 return 1;
4331
4332                         if (svm_allocate_nested(svm))
4333                                 return 1;
4334
4335                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva);
4336                         kvm_vcpu_unmap(vcpu, &map, true);
4337                 }
4338         }
4339
4340         return ret;
4341 }
4342
4343 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4344 {
4345         struct vcpu_svm *svm = to_svm(vcpu);
4346
4347         if (!gif_set(svm)) {
4348                 if (vgif_enabled(svm))
4349                         svm_set_intercept(svm, INTERCEPT_STGI);
4350                 /* STGI will cause a vm exit */
4351         } else {
4352                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4353         }
4354 }
4355
4356 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4357 {
4358         bool smep, smap, is_user;
4359         unsigned long cr4;
4360
4361         /*
4362          * When the guest is an SEV-ES guest, emulation is not possible.
4363          */
4364         if (sev_es_guest(vcpu->kvm))
4365                 return false;
4366
4367         /*
4368          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4369          *
4370          * Errata:
4371          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4372          * possible that CPU microcode implementing DecodeAssist will fail
4373          * to read bytes of instruction which caused #NPF. In this case,
4374          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4375          * return 0 instead of the correct guest instruction bytes.
4376          *
4377          * This happens because CPU microcode reading instruction bytes
4378          * uses a special opcode which attempts to read data using CPL=0
4379          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4380          * fault, it gives up and returns no instruction bytes.
4381          *
4382          * Detection:
4383          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4384          * returned 0 in GuestIntrBytes field of the VMCB.
4385          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4386          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4387          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4388          * a SMEP fault instead of #NPF).
4389          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4390          * As most guests enable SMAP if they have also enabled SMEP, use above
4391          * logic in order to attempt minimize false-positive of detecting errata
4392          * while still preserving all cases semantic correctness.
4393          *
4394          * Workaround:
4395          * To determine what instruction the guest was executing, the hypervisor
4396          * will have to decode the instruction at the instruction pointer.
4397          *
4398          * In non SEV guest, hypervisor will be able to read the guest
4399          * memory to decode the instruction pointer when insn_len is zero
4400          * so we return true to indicate that decoding is possible.
4401          *
4402          * But in the SEV guest, the guest memory is encrypted with the
4403          * guest specific key and hypervisor will not be able to decode the
4404          * instruction pointer so we will not able to workaround it. Lets
4405          * print the error and request to kill the guest.
4406          */
4407         if (likely(!insn || insn_len))
4408                 return true;
4409
4410         /*
4411          * If RIP is invalid, go ahead with emulation which will cause an
4412          * internal error exit.
4413          */
4414         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4415                 return true;
4416
4417         cr4 = kvm_read_cr4(vcpu);
4418         smep = cr4 & X86_CR4_SMEP;
4419         smap = cr4 & X86_CR4_SMAP;
4420         is_user = svm_get_cpl(vcpu) == 3;
4421         if (smap && (!smep || is_user)) {
4422                 if (!sev_guest(vcpu->kvm))
4423                         return true;
4424
4425                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4426                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4427         }
4428
4429         return false;
4430 }
4431
4432 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4433 {
4434         struct vcpu_svm *svm = to_svm(vcpu);
4435
4436         /*
4437          * TODO: Last condition latch INIT signals on vCPU when
4438          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4439          * To properly emulate the INIT intercept,
4440          * svm_check_nested_events() should call nested_svm_vmexit()
4441          * if an INIT signal is pending.
4442          */
4443         return !gif_set(svm) ||
4444                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4445 }
4446
4447 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4448 {
4449         if (!sev_es_guest(vcpu->kvm))
4450                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4451
4452         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4453 }
4454
4455 static void svm_vm_destroy(struct kvm *kvm)
4456 {
4457         avic_vm_destroy(kvm);
4458         sev_vm_destroy(kvm);
4459 }
4460
4461 static int svm_vm_init(struct kvm *kvm)
4462 {
4463         if (!pause_filter_count || !pause_filter_thresh)
4464                 kvm->arch.pause_in_guest = true;
4465
4466         if (enable_apicv) {
4467                 int ret = avic_vm_init(kvm);
4468                 if (ret)
4469                         return ret;
4470         }
4471
4472         return 0;
4473 }
4474
4475 static struct kvm_x86_ops svm_x86_ops __initdata = {
4476         .hardware_unsetup = svm_hardware_teardown,
4477         .hardware_enable = svm_hardware_enable,
4478         .hardware_disable = svm_hardware_disable,
4479         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4480         .has_emulated_msr = svm_has_emulated_msr,
4481
4482         .vcpu_create = svm_create_vcpu,
4483         .vcpu_free = svm_free_vcpu,
4484         .vcpu_reset = svm_vcpu_reset,
4485
4486         .vm_size = sizeof(struct kvm_svm),
4487         .vm_init = svm_vm_init,
4488         .vm_destroy = svm_vm_destroy,
4489
4490         .prepare_guest_switch = svm_prepare_guest_switch,
4491         .vcpu_load = svm_vcpu_load,
4492         .vcpu_put = svm_vcpu_put,
4493         .vcpu_blocking = svm_vcpu_blocking,
4494         .vcpu_unblocking = svm_vcpu_unblocking,
4495
4496         .update_exception_bitmap = svm_update_exception_bitmap,
4497         .get_msr_feature = svm_get_msr_feature,
4498         .get_msr = svm_get_msr,
4499         .set_msr = svm_set_msr,
4500         .get_segment_base = svm_get_segment_base,
4501         .get_segment = svm_get_segment,
4502         .set_segment = svm_set_segment,
4503         .get_cpl = svm_get_cpl,
4504         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4505         .set_cr0 = svm_set_cr0,
4506         .is_valid_cr4 = svm_is_valid_cr4,
4507         .set_cr4 = svm_set_cr4,
4508         .set_efer = svm_set_efer,
4509         .get_idt = svm_get_idt,
4510         .set_idt = svm_set_idt,
4511         .get_gdt = svm_get_gdt,
4512         .set_gdt = svm_set_gdt,
4513         .set_dr7 = svm_set_dr7,
4514         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4515         .cache_reg = svm_cache_reg,
4516         .get_rflags = svm_get_rflags,
4517         .set_rflags = svm_set_rflags,
4518
4519         .tlb_flush_all = svm_flush_tlb,
4520         .tlb_flush_current = svm_flush_tlb,
4521         .tlb_flush_gva = svm_flush_tlb_gva,
4522         .tlb_flush_guest = svm_flush_tlb,
4523
4524         .run = svm_vcpu_run,
4525         .handle_exit = handle_exit,
4526         .skip_emulated_instruction = skip_emulated_instruction,
4527         .update_emulated_instruction = NULL,
4528         .set_interrupt_shadow = svm_set_interrupt_shadow,
4529         .get_interrupt_shadow = svm_get_interrupt_shadow,
4530         .patch_hypercall = svm_patch_hypercall,
4531         .set_irq = svm_set_irq,
4532         .set_nmi = svm_inject_nmi,
4533         .queue_exception = svm_queue_exception,
4534         .cancel_injection = svm_cancel_injection,
4535         .interrupt_allowed = svm_interrupt_allowed,
4536         .nmi_allowed = svm_nmi_allowed,
4537         .get_nmi_mask = svm_get_nmi_mask,
4538         .set_nmi_mask = svm_set_nmi_mask,
4539         .enable_nmi_window = svm_enable_nmi_window,
4540         .enable_irq_window = svm_enable_irq_window,
4541         .update_cr8_intercept = svm_update_cr8_intercept,
4542         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4543         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4544         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4545         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4546         .load_eoi_exitmap = svm_load_eoi_exitmap,
4547         .hwapic_irr_update = svm_hwapic_irr_update,
4548         .hwapic_isr_update = svm_hwapic_isr_update,
4549         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4550         .apicv_post_state_restore = avic_post_state_restore,
4551
4552         .set_tss_addr = svm_set_tss_addr,
4553         .set_identity_map_addr = svm_set_identity_map_addr,
4554         .get_mt_mask = svm_get_mt_mask,
4555
4556         .get_exit_info = svm_get_exit_info,
4557
4558         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4559
4560         .has_wbinvd_exit = svm_has_wbinvd_exit,
4561
4562         .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4563         .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4564         .write_tsc_offset = svm_write_tsc_offset,
4565         .write_tsc_multiplier = svm_write_tsc_multiplier,
4566
4567         .load_mmu_pgd = svm_load_mmu_pgd,
4568
4569         .check_intercept = svm_check_intercept,
4570         .handle_exit_irqoff = svm_handle_exit_irqoff,
4571
4572         .request_immediate_exit = __kvm_request_immediate_exit,
4573
4574         .sched_in = svm_sched_in,
4575
4576         .pmu_ops = &amd_pmu_ops,
4577         .nested_ops = &svm_nested_ops,
4578
4579         .deliver_posted_interrupt = svm_deliver_avic_intr,
4580         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4581         .update_pi_irte = svm_update_pi_irte,
4582         .setup_mce = svm_setup_mce,
4583
4584         .smi_allowed = svm_smi_allowed,
4585         .enter_smm = svm_enter_smm,
4586         .leave_smm = svm_leave_smm,
4587         .enable_smi_window = svm_enable_smi_window,
4588
4589         .mem_enc_op = svm_mem_enc_op,
4590         .mem_enc_reg_region = svm_register_enc_region,
4591         .mem_enc_unreg_region = svm_unregister_enc_region,
4592
4593         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4594
4595         .can_emulate_instruction = svm_can_emulate_instruction,
4596
4597         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4598
4599         .msr_filter_changed = svm_msr_filter_changed,
4600         .complete_emulated_msr = svm_complete_emulated_msr,
4601
4602         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4603 };
4604
4605 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4606         .cpu_has_kvm_support = has_svm,
4607         .disabled_by_bios = is_disabled,
4608         .hardware_setup = svm_hardware_setup,
4609         .check_processor_compatibility = svm_check_processor_compat,
4610
4611         .runtime_ops = &svm_x86_ops,
4612 };
4613
4614 static int __init svm_init(void)
4615 {
4616         __unused_size_checks();
4617
4618         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4619                         __alignof__(struct vcpu_svm), THIS_MODULE);
4620 }
4621
4622 static void __exit svm_exit(void)
4623 {
4624         kvm_exit();
4625 }
4626
4627 module_init(svm_init)
4628 module_exit(svm_exit)