arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 rmtfs_mem: memory@94600000 {
 114                         compatible = "qcom,rmtfs-mem";
 115                         reg = <0x0 0x94600000 0x0 0x200000>;
 116                         no-map;
 117
 118                         qcom,client-id = <1>;
 119                         qcom,vmid = <15>;
 120                 };
 121         };
 122
 123         cpus {
 124                 #address-cells = <2>;
 125                 #size-cells = <0>;
 126
 127                 CPU0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo468";
 130                         reg = <0x0 0x0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 133                                            &LITTLE_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         capacity-dmips-mhz = <1024>;
 136                         dynamic-power-coefficient = <100>;
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 139                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 140                         next-level-cache = <&L2_0>;
 141                         #cooling-cells = <2>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         L2_0: l2-cache {
 144                                 compatible = "cache";
 145                                 next-level-cache = <&L3_0>;
 146                                 L3_0: l3-cache {
 147                                         compatible = "cache";
 148                                 };
 149                         };
 150                 };
 151
 152                 CPU1: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo468";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 158                                            &LITTLE_CPU_SLEEP_1
 159                                            &CLUSTER_SLEEP_0>;
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <100>;
 162                         next-level-cache = <&L2_100>;
 163                         operating-points-v2 = <&cpu0_opp_table>;
 164                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 165                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 166                         #cooling-cells = <2>;
 167                         qcom,freq-domain = <&cpufreq_hw 0>;
 168                         L2_100: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU2: cpu@200 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo468";
 177                         reg = <0x0 0x200>;
 178                         enable-method = "psci";
 179                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 180                                            &LITTLE_CPU_SLEEP_1
 181                                            &CLUSTER_SLEEP_0>;
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <100>;
 184                         next-level-cache = <&L2_200>;
 185                         operating-points-v2 = <&cpu0_opp_table>;
 186                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         #cooling-cells = <2>;
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         L2_200: l2-cache {
 191                                 compatible = "cache";
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU3: cpu@300 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo468";
 199                         reg = <0x0 0x300>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 202                                            &LITTLE_CPU_SLEEP_1
 203                                            &CLUSTER_SLEEP_0>;
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <100>;
 206                         next-level-cache = <&L2_300>;
 207                         operating-points-v2 = <&cpu0_opp_table>;
 208                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 209                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 210                         #cooling-cells = <2>;
 211                         qcom,freq-domain = <&cpufreq_hw 0>;
 212                         L2_300: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 CPU4: cpu@400 {
 219                         device_type = "cpu";
 220                         compatible = "qcom,kryo468";
 221                         reg = <0x0 0x400>;
 222                         enable-method = "psci";
 223                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 224                                            &LITTLE_CPU_SLEEP_1
 225                                            &CLUSTER_SLEEP_0>;
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <100>;
 228                         next-level-cache = <&L2_400>;
 229                         operating-points-v2 = <&cpu0_opp_table>;
 230                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 231                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 232                         #cooling-cells = <2>;
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         L2_400: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU5: cpu@500 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo468";
 243                         reg = <0x0 0x500>;
 244                         enable-method = "psci";
 245                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 246                                            &LITTLE_CPU_SLEEP_1
 247                                            &CLUSTER_SLEEP_0>;
 248                         capacity-dmips-mhz = <1024>;
 249                         dynamic-power-coefficient = <100>;
 250                         next-level-cache = <&L2_500>;
 251                         operating-points-v2 = <&cpu0_opp_table>;
 252                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 254                         #cooling-cells = <2>;
 255                         qcom,freq-domain = <&cpufreq_hw 0>;
 256                         L2_500: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU6: cpu@600 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo468";
 265                         reg = <0x0 0x600>;
 266                         enable-method = "psci";
 267                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 268                                            &BIG_CPU_SLEEP_1
 269                                            &CLUSTER_SLEEP_0>;
 270                         capacity-dmips-mhz = <1740>;
 271                         dynamic-power-coefficient = <405>;
 272                         next-level-cache = <&L2_600>;
 273                         operating-points-v2 = <&cpu6_opp_table>;
 274                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 275                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 276                         #cooling-cells = <2>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         L2_600: l2-cache {
 279                                 compatible = "cache";
 280                                 next-level-cache = <&L3_0>;
 281                         };
 282                 };
 283
 284                 CPU7: cpu@700 {
 285                         device_type = "cpu";
 286                         compatible = "qcom,kryo468";
 287                         reg = <0x0 0x700>;
 288                         enable-method = "psci";
 289                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 290                                            &BIG_CPU_SLEEP_1
 291                                            &CLUSTER_SLEEP_0>;
 292                         capacity-dmips-mhz = <1740>;
 293                         dynamic-power-coefficient = <405>;
 294                         next-level-cache = <&L2_700>;
 295                         operating-points-v2 = <&cpu6_opp_table>;
 296                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 297                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 298                         #cooling-cells = <2>;
 299                         qcom,freq-domain = <&cpufreq_hw 1>;
 300                         L2_700: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 cpu-map {
 307                         cluster0 {
 308                                 core0 {
 309                                         cpu = <&CPU0>;
 310                                 };
 311
 312                                 core1 {
 313                                         cpu = <&CPU1>;
 314                                 };
 315
 316                                 core2 {
 317                                         cpu = <&CPU2>;
 318                                 };
 319
 320                                 core3 {
 321                                         cpu = <&CPU3>;
 322                                 };
 323
 324                                 core4 {
 325                                         cpu = <&CPU4>;
 326                                 };
 327
 328                                 core5 {
 329                                         cpu = <&CPU5>;
 330                                 };
 331
 332                                 core6 {
 333                                         cpu = <&CPU6>;
 334                                 };
 335
 336                                 core7 {
 337                                         cpu = <&CPU7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 idle-states {
 343                         entry-method = "psci";
 344
 345                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 346                                 compatible = "arm,idle-state";
 347                                 idle-state-name = "little-power-down";
 348                                 arm,psci-suspend-param = <0x40000003>;
 349                                 entry-latency-us = <549>;
 350                                 exit-latency-us = <901>;
 351                                 min-residency-us = <1774>;
 352                                 local-timer-stop;
 353                         };
 354
 355                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 356                                 compatible = "arm,idle-state";
 357                                 idle-state-name = "little-rail-power-down";
 358                                 arm,psci-suspend-param = <0x40000004>;
 359                                 entry-latency-us = <702>;
 360                                 exit-latency-us = <915>;
 361                                 min-residency-us = <4001>;
 362                                 local-timer-stop;
 363                         };
 364
 365                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 366                                 compatible = "arm,idle-state";
 367                                 idle-state-name = "big-power-down";
 368                                 arm,psci-suspend-param = <0x40000003>;
 369                                 entry-latency-us = <523>;
 370                                 exit-latency-us = <1244>;
 371                                 min-residency-us = <2207>;
 372                                 local-timer-stop;
 373                         };
 374
 375                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 376                                 compatible = "arm,idle-state";
 377                                 idle-state-name = "big-rail-power-down";
 378                                 arm,psci-suspend-param = <0x40000004>;
 379                                 entry-latency-us = <526>;
 380                                 exit-latency-us = <1854>;
 381                                 min-residency-us = <5555>;
 382                                 local-timer-stop;
 383                         };
 384
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "arm,idle-state";
 387                                 idle-state-name = "cluster-power-down";
 388                                 arm,psci-suspend-param = <0x40003444>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9926>;
 392                                 local-timer-stop;
 393                         };
 394                 };
 395         };
 396
 397         cpu0_opp_table: cpu0_opp_table {
 398                 compatible = "operating-points-v2";
 399                 opp-shared;
 400
 401                 cpu0_opp1: opp-300000000 {
 402                         opp-hz = /bits/ 64 <300000000>;
 403                         opp-peak-kBps = <1200000 4800000>;
 404                 };
 405
 406                 cpu0_opp2: opp-576000000 {
 407                         opp-hz = /bits/ 64 <576000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp3: opp-768000000 {
 412                         opp-hz = /bits/ 64 <768000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp4: opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <1804000 8908800>;
 419                 };
 420
 421                 cpu0_opp5: opp-1248000000 {
 422                         opp-hz = /bits/ 64 <1248000000>;
 423                         opp-peak-kBps = <2188000 12902400>;
 424                 };
 425
 426                 cpu0_opp6: opp-1324800000 {
 427                         opp-hz = /bits/ 64 <1324800000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp7: opp-1516800000 {
 432                         opp-hz = /bits/ 64 <1516800000>;
 433                         opp-peak-kBps = <3072000 15052800>;
 434                 };
 435
 436                 cpu0_opp8: opp-1612800000 {
 437                         opp-hz = /bits/ 64 <1612800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp9: opp-1708800000 {
 442                         opp-hz = /bits/ 64 <1708800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp10: opp-1804800000 {
 447                         opp-hz = /bits/ 64 <1804800000>;
 448                         opp-peak-kBps = <4068000 22425600>;
 449                 };
 450         };
 451
 452         cpu6_opp_table: cpu6_opp_table {
 453                 compatible = "operating-points-v2";
 454                 opp-shared;
 455
 456                 cpu6_opp1: opp-300000000 {
 457                         opp-hz = /bits/ 64 <300000000>;
 458                         opp-peak-kBps = <2188000 8908800>;
 459                 };
 460
 461                 cpu6_opp2: opp-652800000 {
 462                         opp-hz = /bits/ 64 <652800000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp3: opp-825600000 {
 467                         opp-hz = /bits/ 64 <825600000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp4: opp-979200000 {
 472                         opp-hz = /bits/ 64 <979200000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp5: opp-1113600000 {
 477                         opp-hz = /bits/ 64 <1113600000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp6: opp-1267200000 {
 482                         opp-hz = /bits/ 64 <1267200000>;
 483                         opp-peak-kBps = <4068000 12902400>;
 484                 };
 485
 486                 cpu6_opp7: opp-1555200000 {
 487                         opp-hz = /bits/ 64 <1555200000>;
 488                         opp-peak-kBps = <4068000 15052800>;
 489                 };
 490
 491                 cpu6_opp8: opp-1708800000 {
 492                         opp-hz = /bits/ 64 <1708800000>;
 493                         opp-peak-kBps = <6220000 19353600>;
 494                 };
 495
 496                 cpu6_opp9: opp-1843200000 {
 497                         opp-hz = /bits/ 64 <1843200000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp10: opp-1900800000 {
 502                         opp-hz = /bits/ 64 <1900800000>;
 503                         opp-peak-kBps = <6220000 22425600>;
 504                 };
 505
 506                 cpu6_opp11: opp-1996800000 {
 507                         opp-hz = /bits/ 64 <1996800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp12: opp-2112000000 {
 512                         opp-hz = /bits/ 64 <2112000000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp13: opp-2208000000 {
 517                         opp-hz = /bits/ 64 <2208000000>;
 518                         opp-peak-kBps = <7216000 22425600>;
 519                 };
 520
 521                 cpu6_opp14: opp-2323200000 {
 522                         opp-hz = /bits/ 64 <2323200000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp15: opp-2400000000 {
 527                         opp-hz = /bits/ 64 <2400000000>;
 528                         opp-peak-kBps = <8532000 23347200>;
 529                 };
 530
 531                 cpu6_opp16: opp-2553600000 {
 532                         opp-hz = /bits/ 64 <2553600000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535         };
 536
 537         memory@80000000 {
 538                 device_type = "memory";
 539                 /* We expect the bootloader to fill in the size */
 540                 reg = <0 0x80000000 0 0>;
 541         };
 542
 543         pmu {
 544                 compatible = "arm,armv8-pmuv3";
 545                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 546         };
 547
 548         firmware {
 549                 scm {
 550                         compatible = "qcom,scm-sc7180", "qcom,scm";
 551                 };
 552         };
 553
 554         tcsr_mutex: hwlock {
 555                 compatible = "qcom,tcsr-mutex";
 556                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 557                 #hwlock-cells = <1>;
 558         };
 559
 560         smem {
 561                 compatible = "qcom,smem";
 562                 memory-region = <&smem_mem>;
 563                 hwlocks = <&tcsr_mutex 3>;
 564         };
 565
 566         smp2p-cdsp {
 567                 compatible = "qcom,smp2p";
 568                 qcom,smem = <94>, <432>;
 569
 570                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 571
 572                 mboxes = <&apss_shared 6>;
 573
 574                 qcom,local-pid = <0>;
 575                 qcom,remote-pid = <5>;
 576
 577                 cdsp_smp2p_out: master-kernel {
 578                         qcom,entry-name = "master-kernel";
 579                         #qcom,smem-state-cells = <1>;
 580                 };
 581
 582                 cdsp_smp2p_in: slave-kernel {
 583                         qcom,entry-name = "slave-kernel";
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588         };
 589
 590         smp2p-lpass {
 591                 compatible = "qcom,smp2p";
 592                 qcom,smem = <443>, <429>;
 593
 594                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 595
 596                 mboxes = <&apss_shared 10>;
 597
 598                 qcom,local-pid = <0>;
 599                 qcom,remote-pid = <2>;
 600
 601                 adsp_smp2p_out: master-kernel {
 602                         qcom,entry-name = "master-kernel";
 603                         #qcom,smem-state-cells = <1>;
 604                 };
 605
 606                 adsp_smp2p_in: slave-kernel {
 607                         qcom,entry-name = "slave-kernel";
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612         };
 613
 614         smp2p-mpss {
 615                 compatible = "qcom,smp2p";
 616                 qcom,smem = <435>, <428>;
 617                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&apss_shared 14>;
 619                 qcom,local-pid = <0>;
 620                 qcom,remote-pid = <1>;
 621
 622                 modem_smp2p_out: master-kernel {
 623                         qcom,entry-name = "master-kernel";
 624                         #qcom,smem-state-cells = <1>;
 625                 };
 626
 627                 modem_smp2p_in: slave-kernel {
 628                         qcom,entry-name = "slave-kernel";
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 ipa_smp2p_out: ipa-ap-to-modem {
 634                         qcom,entry-name = "ipa";
 635                         #qcom,smem-state-cells = <1>;
 636                 };
 637
 638                 ipa_smp2p_in: ipa-modem-to-ap {
 639                         qcom,entry-name = "ipa";
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                 };
 643         };
 644
 645         psci {
 646                 compatible = "arm,psci-1.0";
 647                 method = "smc";
 648         };
 649
 650         soc: soc@0 {
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 ranges = <0 0 0 0 0x10 0>;
 654                 dma-ranges = <0 0 0 0 0x10 0>;
 655                 compatible = "simple-bus";
 656
 657                 gcc: clock-controller@100000 {
 658                         compatible = "qcom,gcc-sc7180";
 659                         reg = <0 0x00100000 0 0x1f0000>;
 660                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 661                                  <&rpmhcc RPMH_CXO_CLK_A>,
 662                                  <&sleep_clk>;
 663                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 664                         #clock-cells = <1>;
 665                         #reset-cells = <1>;
 666                         #power-domain-cells = <1>;
 667                 };
 668
 669                 qfprom: efuse@784000 {
 670                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 671                         reg = <0 0x00784000 0 0x8ff>,
 672                               <0 0x00780000 0 0x7a0>,
 673                               <0 0x00782000 0 0x100>,
 674                               <0 0x00786000 0 0x1fff>;
 675
 676                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 677                         clock-names = "core";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680
 681                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 682                                 reg = <0x25b 0x1>;
 683                                 bits = <1 3>;
 684                         };
 685
 686                         gpu_speed_bin: gpu_speed_bin@1d2 {
 687                                 reg = <0x1d2 0x2>;
 688                                 bits = <5 8>;
 689                         };
 690                 };
 691
 692                 sdhc_1: sdhci@7c4000 {
 693                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 694                         reg = <0 0x7c4000 0 0x1000>,
 695                                 <0 0x07c5000 0 0x1000>;
 696                         reg-names = "hc", "cqhci";
 697
 698                         iommus = <&apps_smmu 0x60 0x0>;
 699                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 700                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 701                         interrupt-names = "hc_irq", "pwr_irq";
 702
 703                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 704                                  <&gcc GCC_SDCC1_AHB_CLK>,
 705                                  <&rpmhcc RPMH_CXO_CLK>;
 706                         clock-names = "core", "iface", "xo";
 707                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 708                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 709                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 710                         power-domains = <&rpmhpd SC7180_CX>;
 711                         operating-points-v2 = <&sdhc1_opp_table>;
 712
 713                         bus-width = <8>;
 714                         non-removable;
 715                         supports-cqe;
 716
 717                         mmc-ddr-1_8v;
 718                         mmc-hs200-1_8v;
 719                         mmc-hs400-1_8v;
 720                         mmc-hs400-enhanced-strobe;
 721
 722                         status = "disabled";
 723
 724                         sdhc1_opp_table: sdhc1-opp-table {
 725                                 compatible = "operating-points-v2";
 726
 727                                 opp-100000000 {
 728                                         opp-hz = /bits/ 64 <100000000>;
 729                                         required-opps = <&rpmhpd_opp_low_svs>;
 730                                         opp-peak-kBps = <1800000 600000>;
 731                                         opp-avg-kBps = <100000 0>;
 732                                 };
 733
 734                                 opp-384000000 {
 735                                         opp-hz = /bits/ 64 <384000000>;
 736                                         required-opps = <&rpmhpd_opp_nom>;
 737                                         opp-peak-kBps = <5400000 1600000>;
 738                                         opp-avg-kBps = <390000 0>;
 739                                 };
 740                         };
 741                 };
 742
 743                 qup_opp_table: qup-opp-table {
 744                         compatible = "operating-points-v2";
 745
 746                         opp-75000000 {
 747                                 opp-hz = /bits/ 64 <75000000>;
 748                                 required-opps = <&rpmhpd_opp_low_svs>;
 749                         };
 750
 751                         opp-100000000 {
 752                                 opp-hz = /bits/ 64 <100000000>;
 753                                 required-opps = <&rpmhpd_opp_svs>;
 754                         };
 755
 756                         opp-128000000 {
 757                                 opp-hz = /bits/ 64 <128000000>;
 758                                 required-opps = <&rpmhpd_opp_nom>;
 759                         };
 760                 };
 761
 762                 qupv3_id_0: geniqup@8c0000 {
 763                         compatible = "qcom,geni-se-qup";
 764                         reg = <0 0x008c0000 0 0x6000>;
 765                         clock-names = "m-ahb", "s-ahb";
 766                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 767                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 768                         #address-cells = <2>;
 769                         #size-cells = <2>;
 770                         ranges;
 771                         iommus = <&apps_smmu 0x43 0x0>;
 772                         status = "disabled";
 773
 774                         i2c0: i2c@880000 {
 775                                 compatible = "qcom,geni-i2c";
 776                                 reg = <0 0x00880000 0 0x4000>;
 777                                 clock-names = "se";
 778                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 779                                 pinctrl-names = "default";
 780                                 pinctrl-0 = <&qup_i2c0_default>;
 781                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 782                                 #address-cells = <1>;
 783                                 #size-cells = <0>;
 784                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 785                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 786                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 787                                 interconnect-names = "qup-core", "qup-config",
 788                                                         "qup-memory";
 789                                 power-domains = <&rpmhpd SC7180_CX>;
 790                                 required-opps = <&rpmhpd_opp_low_svs>;
 791                                 status = "disabled";
 792                         };
 793
 794                         spi0: spi@880000 {
 795                                 compatible = "qcom,geni-spi";
 796                                 reg = <0 0x00880000 0 0x4000>;
 797                                 clock-names = "se";
 798                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 799                                 pinctrl-names = "default";
 800                                 pinctrl-0 = <&qup_spi0_default>;
 801                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 802                                 #address-cells = <1>;
 803                                 #size-cells = <0>;
 804                                 power-domains = <&rpmhpd SC7180_CX>;
 805                                 operating-points-v2 = <&qup_opp_table>;
 806                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 807                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 808                                 interconnect-names = "qup-core", "qup-config";
 809                                 status = "disabled";
 810                         };
 811
 812                         uart0: serial@880000 {
 813                                 compatible = "qcom,geni-uart";
 814                                 reg = <0 0x00880000 0 0x4000>;
 815                                 clock-names = "se";
 816                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 817                                 pinctrl-names = "default";
 818                                 pinctrl-0 = <&qup_uart0_default>;
 819                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 820                                 power-domains = <&rpmhpd SC7180_CX>;
 821                                 operating-points-v2 = <&qup_opp_table>;
 822                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 823                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 824                                 interconnect-names = "qup-core", "qup-config";
 825                                 status = "disabled";
 826                         };
 827
 828                         i2c1: i2c@884000 {
 829                                 compatible = "qcom,geni-i2c";
 830                                 reg = <0 0x00884000 0 0x4000>;
 831                                 clock-names = "se";
 832                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 833                                 pinctrl-names = "default";
 834                                 pinctrl-0 = <&qup_i2c1_default>;
 835                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 839                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 840                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 841                                 interconnect-names = "qup-core", "qup-config",
 842                                                         "qup-memory";
 843                                 power-domains = <&rpmhpd SC7180_CX>;
 844                                 required-opps = <&rpmhpd_opp_low_svs>;
 845                                 status = "disabled";
 846                         };
 847
 848                         spi1: spi@884000 {
 849                                 compatible = "qcom,geni-spi";
 850                                 reg = <0 0x00884000 0 0x4000>;
 851                                 clock-names = "se";
 852                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 853                                 pinctrl-names = "default";
 854                                 pinctrl-0 = <&qup_spi1_default>;
 855                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 856                                 #address-cells = <1>;
 857                                 #size-cells = <0>;
 858                                 power-domains = <&rpmhpd SC7180_CX>;
 859                                 operating-points-v2 = <&qup_opp_table>;
 860                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 861                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 862                                 interconnect-names = "qup-core", "qup-config";
 863                                 status = "disabled";
 864                         };
 865
 866                         uart1: serial@884000 {
 867                                 compatible = "qcom,geni-uart";
 868                                 reg = <0 0x00884000 0 0x4000>;
 869                                 clock-names = "se";
 870                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 871                                 pinctrl-names = "default";
 872                                 pinctrl-0 = <&qup_uart1_default>;
 873                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 874                                 power-domains = <&rpmhpd SC7180_CX>;
 875                                 operating-points-v2 = <&qup_opp_table>;
 876                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 877                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 878                                 interconnect-names = "qup-core", "qup-config";
 879                                 status = "disabled";
 880                         };
 881
 882                         i2c2: i2c@888000 {
 883                                 compatible = "qcom,geni-i2c";
 884                                 reg = <0 0x00888000 0 0x4000>;
 885                                 clock-names = "se";
 886                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 887                                 pinctrl-names = "default";
 888                                 pinctrl-0 = <&qup_i2c2_default>;
 889                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 890                                 #address-cells = <1>;
 891                                 #size-cells = <0>;
 892                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 893                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 894                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 895                                 interconnect-names = "qup-core", "qup-config",
 896                                                         "qup-memory";
 897                                 power-domains = <&rpmhpd SC7180_CX>;
 898                                 required-opps = <&rpmhpd_opp_low_svs>;
 899                                 status = "disabled";
 900                         };
 901
 902                         uart2: serial@888000 {
 903                                 compatible = "qcom,geni-uart";
 904                                 reg = <0 0x00888000 0 0x4000>;
 905                                 clock-names = "se";
 906                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 907                                 pinctrl-names = "default";
 908                                 pinctrl-0 = <&qup_uart2_default>;
 909                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 910                                 power-domains = <&rpmhpd SC7180_CX>;
 911                                 operating-points-v2 = <&qup_opp_table>;
 912                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 913                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 914                                 interconnect-names = "qup-core", "qup-config";
 915                                 status = "disabled";
 916                         };
 917
 918                         i2c3: i2c@88c000 {
 919                                 compatible = "qcom,geni-i2c";
 920                                 reg = <0 0x0088c000 0 0x4000>;
 921                                 clock-names = "se";
 922                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 923                                 pinctrl-names = "default";
 924                                 pinctrl-0 = <&qup_i2c3_default>;
 925                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 926                                 #address-cells = <1>;
 927                                 #size-cells = <0>;
 928                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 929                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 930                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 931                                 interconnect-names = "qup-core", "qup-config",
 932                                                         "qup-memory";
 933                                 power-domains = <&rpmhpd SC7180_CX>;
 934                                 required-opps = <&rpmhpd_opp_low_svs>;
 935                                 status = "disabled";
 936                         };
 937
 938                         spi3: spi@88c000 {
 939                                 compatible = "qcom,geni-spi";
 940                                 reg = <0 0x0088c000 0 0x4000>;
 941                                 clock-names = "se";
 942                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 943                                 pinctrl-names = "default";
 944                                 pinctrl-0 = <&qup_spi3_default>;
 945                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 946                                 #address-cells = <1>;
 947                                 #size-cells = <0>;
 948                                 power-domains = <&rpmhpd SC7180_CX>;
 949                                 operating-points-v2 = <&qup_opp_table>;
 950                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 951                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 952                                 interconnect-names = "qup-core", "qup-config";
 953                                 status = "disabled";
 954                         };
 955
 956                         uart3: serial@88c000 {
 957                                 compatible = "qcom,geni-uart";
 958                                 reg = <0 0x0088c000 0 0x4000>;
 959                                 clock-names = "se";
 960                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 961                                 pinctrl-names = "default";
 962                                 pinctrl-0 = <&qup_uart3_default>;
 963                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 964                                 power-domains = <&rpmhpd SC7180_CX>;
 965                                 operating-points-v2 = <&qup_opp_table>;
 966                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 967                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 968                                 interconnect-names = "qup-core", "qup-config";
 969                                 status = "disabled";
 970                         };
 971
 972                         i2c4: i2c@890000 {
 973                                 compatible = "qcom,geni-i2c";
 974                                 reg = <0 0x00890000 0 0x4000>;
 975                                 clock-names = "se";
 976                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 977                                 pinctrl-names = "default";
 978                                 pinctrl-0 = <&qup_i2c4_default>;
 979                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 980                                 #address-cells = <1>;
 981                                 #size-cells = <0>;
 982                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 983                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 984                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 985                                 interconnect-names = "qup-core", "qup-config",
 986                                                         "qup-memory";
 987                                 power-domains = <&rpmhpd SC7180_CX>;
 988                                 required-opps = <&rpmhpd_opp_low_svs>;
 989                                 status = "disabled";
 990                         };
 991
 992                         uart4: serial@890000 {
 993                                 compatible = "qcom,geni-uart";
 994                                 reg = <0 0x00890000 0 0x4000>;
 995                                 clock-names = "se";
 996                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 997                                 pinctrl-names = "default";
 998                                 pinctrl-0 = <&qup_uart4_default>;
 999                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1000                                 power-domains = <&rpmhpd SC7180_CX>;
1001                                 operating-points-v2 = <&qup_opp_table>;
1002                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1003                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1004                                 interconnect-names = "qup-core", "qup-config";
1005                                 status = "disabled";
1006                         };
1007
1008                         i2c5: i2c@894000 {
1009                                 compatible = "qcom,geni-i2c";
1010                                 reg = <0 0x00894000 0 0x4000>;
1011                                 clock-names = "se";
1012                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&qup_i2c5_default>;
1015                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1016                                 #address-cells = <1>;
1017                                 #size-cells = <0>;
1018                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1019                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1020                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1021                                 interconnect-names = "qup-core", "qup-config",
1022                                                         "qup-memory";
1023                                 power-domains = <&rpmhpd SC7180_CX>;
1024                                 required-opps = <&rpmhpd_opp_low_svs>;
1025                                 status = "disabled";
1026                         };
1027
1028                         spi5: spi@894000 {
1029                                 compatible = "qcom,geni-spi";
1030                                 reg = <0 0x00894000 0 0x4000>;
1031                                 clock-names = "se";
1032                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1033                                 pinctrl-names = "default";
1034                                 pinctrl-0 = <&qup_spi5_default>;
1035                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1036                                 #address-cells = <1>;
1037                                 #size-cells = <0>;
1038                                 power-domains = <&rpmhpd SC7180_CX>;
1039                                 operating-points-v2 = <&qup_opp_table>;
1040                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1041                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1042                                 interconnect-names = "qup-core", "qup-config";
1043                                 status = "disabled";
1044                         };
1045
1046                         uart5: serial@894000 {
1047                                 compatible = "qcom,geni-uart";
1048                                 reg = <0 0x00894000 0 0x4000>;
1049                                 clock-names = "se";
1050                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1051                                 pinctrl-names = "default";
1052                                 pinctrl-0 = <&qup_uart5_default>;
1053                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1054                                 power-domains = <&rpmhpd SC7180_CX>;
1055                                 operating-points-v2 = <&qup_opp_table>;
1056                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1057                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1058                                 interconnect-names = "qup-core", "qup-config";
1059                                 status = "disabled";
1060                         };
1061                 };
1062
1063                 qupv3_id_1: geniqup@ac0000 {
1064                         compatible = "qcom,geni-se-qup";
1065                         reg = <0 0x00ac0000 0 0x6000>;
1066                         clock-names = "m-ahb", "s-ahb";
1067                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1068                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1069                         #address-cells = <2>;
1070                         #size-cells = <2>;
1071                         ranges;
1072                         iommus = <&apps_smmu 0x4c3 0x0>;
1073                         status = "disabled";
1074
1075                         i2c6: i2c@a80000 {
1076                                 compatible = "qcom,geni-i2c";
1077                                 reg = <0 0x00a80000 0 0x4000>;
1078                                 clock-names = "se";
1079                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1080                                 pinctrl-names = "default";
1081                                 pinctrl-0 = <&qup_i2c6_default>;
1082                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1083                                 #address-cells = <1>;
1084                                 #size-cells = <0>;
1085                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1086                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1087                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1088                                 interconnect-names = "qup-core", "qup-config",
1089                                                         "qup-memory";
1090                                 power-domains = <&rpmhpd SC7180_CX>;
1091                                 required-opps = <&rpmhpd_opp_low_svs>;
1092                                 status = "disabled";
1093                         };
1094
1095                         spi6: spi@a80000 {
1096                                 compatible = "qcom,geni-spi";
1097                                 reg = <0 0x00a80000 0 0x4000>;
1098                                 clock-names = "se";
1099                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1100                                 pinctrl-names = "default";
1101                                 pinctrl-0 = <&qup_spi6_default>;
1102                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105                                 power-domains = <&rpmhpd SC7180_CX>;
1106                                 operating-points-v2 = <&qup_opp_table>;
1107                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1108                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1109                                 interconnect-names = "qup-core", "qup-config";
1110                                 status = "disabled";
1111                         };
1112
1113                         uart6: serial@a80000 {
1114                                 compatible = "qcom,geni-uart";
1115                                 reg = <0 0x00a80000 0 0x4000>;
1116                                 clock-names = "se";
1117                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1118                                 pinctrl-names = "default";
1119                                 pinctrl-0 = <&qup_uart6_default>;
1120                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1121                                 power-domains = <&rpmhpd SC7180_CX>;
1122                                 operating-points-v2 = <&qup_opp_table>;
1123                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1124                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1125                                 interconnect-names = "qup-core", "qup-config";
1126                                 status = "disabled";
1127                         };
1128
1129                         i2c7: i2c@a84000 {
1130                                 compatible = "qcom,geni-i2c";
1131                                 reg = <0 0x00a84000 0 0x4000>;
1132                                 clock-names = "se";
1133                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1134                                 pinctrl-names = "default";
1135                                 pinctrl-0 = <&qup_i2c7_default>;
1136                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1137                                 #address-cells = <1>;
1138                                 #size-cells = <0>;
1139                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1140                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1141                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1142                                 interconnect-names = "qup-core", "qup-config",
1143                                                         "qup-memory";
1144                                 power-domains = <&rpmhpd SC7180_CX>;
1145                                 required-opps = <&rpmhpd_opp_low_svs>;
1146                                 status = "disabled";
1147                         };
1148
1149                         uart7: serial@a84000 {
1150                                 compatible = "qcom,geni-uart";
1151                                 reg = <0 0x00a84000 0 0x4000>;
1152                                 clock-names = "se";
1153                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1154                                 pinctrl-names = "default";
1155                                 pinctrl-0 = <&qup_uart7_default>;
1156                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1157                                 power-domains = <&rpmhpd SC7180_CX>;
1158                                 operating-points-v2 = <&qup_opp_table>;
1159                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1160                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1161                                 interconnect-names = "qup-core", "qup-config";
1162                                 status = "disabled";
1163                         };
1164
1165                         i2c8: i2c@a88000 {
1166                                 compatible = "qcom,geni-i2c";
1167                                 reg = <0 0x00a88000 0 0x4000>;
1168                                 clock-names = "se";
1169                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1170                                 pinctrl-names = "default";
1171                                 pinctrl-0 = <&qup_i2c8_default>;
1172                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1173                                 #address-cells = <1>;
1174                                 #size-cells = <0>;
1175                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1176                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1177                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1178                                 interconnect-names = "qup-core", "qup-config",
1179                                                         "qup-memory";
1180                                 power-domains = <&rpmhpd SC7180_CX>;
1181                                 required-opps = <&rpmhpd_opp_low_svs>;
1182                                 status = "disabled";
1183                         };
1184
1185                         spi8: spi@a88000 {
1186                                 compatible = "qcom,geni-spi";
1187                                 reg = <0 0x00a88000 0 0x4000>;
1188                                 clock-names = "se";
1189                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1190                                 pinctrl-names = "default";
1191                                 pinctrl-0 = <&qup_spi8_default>;
1192                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1193                                 #address-cells = <1>;
1194                                 #size-cells = <0>;
1195                                 power-domains = <&rpmhpd SC7180_CX>;
1196                                 operating-points-v2 = <&qup_opp_table>;
1197                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1199                                 interconnect-names = "qup-core", "qup-config";
1200                                 status = "disabled";
1201                         };
1202
1203                         uart8: serial@a88000 {
1204                                 compatible = "qcom,geni-debug-uart";
1205                                 reg = <0 0x00a88000 0 0x4000>;
1206                                 clock-names = "se";
1207                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1208                                 pinctrl-names = "default";
1209                                 pinctrl-0 = <&qup_uart8_default>;
1210                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1211                                 power-domains = <&rpmhpd SC7180_CX>;
1212                                 operating-points-v2 = <&qup_opp_table>;
1213                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1214                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1215                                 interconnect-names = "qup-core", "qup-config";
1216                                 status = "disabled";
1217                         };
1218
1219                         i2c9: i2c@a8c000 {
1220                                 compatible = "qcom,geni-i2c";
1221                                 reg = <0 0x00a8c000 0 0x4000>;
1222                                 clock-names = "se";
1223                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1224                                 pinctrl-names = "default";
1225                                 pinctrl-0 = <&qup_i2c9_default>;
1226                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1227                                 #address-cells = <1>;
1228                                 #size-cells = <0>;
1229                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1230                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1231                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1232                                 interconnect-names = "qup-core", "qup-config",
1233                                                         "qup-memory";
1234                                 power-domains = <&rpmhpd SC7180_CX>;
1235                                 required-opps = <&rpmhpd_opp_low_svs>;
1236                                 status = "disabled";
1237                         };
1238
1239                         uart9: serial@a8c000 {
1240                                 compatible = "qcom,geni-uart";
1241                                 reg = <0 0x00a8c000 0 0x4000>;
1242                                 clock-names = "se";
1243                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1244                                 pinctrl-names = "default";
1245                                 pinctrl-0 = <&qup_uart9_default>;
1246                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1247                                 power-domains = <&rpmhpd SC7180_CX>;
1248                                 operating-points-v2 = <&qup_opp_table>;
1249                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1250                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1251                                 interconnect-names = "qup-core", "qup-config";
1252                                 status = "disabled";
1253                         };
1254
1255                         i2c10: i2c@a90000 {
1256                                 compatible = "qcom,geni-i2c";
1257                                 reg = <0 0x00a90000 0 0x4000>;
1258                                 clock-names = "se";
1259                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1260                                 pinctrl-names = "default";
1261                                 pinctrl-0 = <&qup_i2c10_default>;
1262                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1263                                 #address-cells = <1>;
1264                                 #size-cells = <0>;
1265                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1266                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1267                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1268                                 interconnect-names = "qup-core", "qup-config",
1269                                                         "qup-memory";
1270                                 power-domains = <&rpmhpd SC7180_CX>;
1271                                 required-opps = <&rpmhpd_opp_low_svs>;
1272                                 status = "disabled";
1273                         };
1274
1275                         spi10: spi@a90000 {
1276                                 compatible = "qcom,geni-spi";
1277                                 reg = <0 0x00a90000 0 0x4000>;
1278                                 clock-names = "se";
1279                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1280                                 pinctrl-names = "default";
1281                                 pinctrl-0 = <&qup_spi10_default>;
1282                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 power-domains = <&rpmhpd SC7180_CX>;
1286                                 operating-points-v2 = <&qup_opp_table>;
1287                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1288                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1289                                 interconnect-names = "qup-core", "qup-config";
1290                                 status = "disabled";
1291                         };
1292
1293                         uart10: serial@a90000 {
1294                                 compatible = "qcom,geni-uart";
1295                                 reg = <0 0x00a90000 0 0x4000>;
1296                                 clock-names = "se";
1297                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1298                                 pinctrl-names = "default";
1299                                 pinctrl-0 = <&qup_uart10_default>;
1300                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1301                                 power-domains = <&rpmhpd SC7180_CX>;
1302                                 operating-points-v2 = <&qup_opp_table>;
1303                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1304                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1305                                 interconnect-names = "qup-core", "qup-config";
1306                                 status = "disabled";
1307                         };
1308
1309                         i2c11: i2c@a94000 {
1310                                 compatible = "qcom,geni-i2c";
1311                                 reg = <0 0x00a94000 0 0x4000>;
1312                                 clock-names = "se";
1313                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1314                                 pinctrl-names = "default";
1315                                 pinctrl-0 = <&qup_i2c11_default>;
1316                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1317                                 #address-cells = <1>;
1318                                 #size-cells = <0>;
1319                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1320                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1321                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1322                                 interconnect-names = "qup-core", "qup-config",
1323                                                         "qup-memory";
1324                                 power-domains = <&rpmhpd SC7180_CX>;
1325                                 required-opps = <&rpmhpd_opp_low_svs>;
1326                                 status = "disabled";
1327                         };
1328
1329                         spi11: spi@a94000 {
1330                                 compatible = "qcom,geni-spi";
1331                                 reg = <0 0x00a94000 0 0x4000>;
1332                                 clock-names = "se";
1333                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1334                                 pinctrl-names = "default";
1335                                 pinctrl-0 = <&qup_spi11_default>;
1336                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1337                                 #address-cells = <1>;
1338                                 #size-cells = <0>;
1339                                 power-domains = <&rpmhpd SC7180_CX>;
1340                                 operating-points-v2 = <&qup_opp_table>;
1341                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1342                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1343                                 interconnect-names = "qup-core", "qup-config";
1344                                 status = "disabled";
1345                         };
1346
1347                         uart11: serial@a94000 {
1348                                 compatible = "qcom,geni-uart";
1349                                 reg = <0 0x00a94000 0 0x4000>;
1350                                 clock-names = "se";
1351                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1352                                 pinctrl-names = "default";
1353                                 pinctrl-0 = <&qup_uart11_default>;
1354                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1355                                 power-domains = <&rpmhpd SC7180_CX>;
1356                                 operating-points-v2 = <&qup_opp_table>;
1357                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1358                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1359                                 interconnect-names = "qup-core", "qup-config";
1360                                 status = "disabled";
1361                         };
1362                 };
1363
1364                 config_noc: interconnect@1500000 {
1365                         compatible = "qcom,sc7180-config-noc";
1366                         reg = <0 0x01500000 0 0x28000>;
1367                         #interconnect-cells = <2>;
1368                         qcom,bcm-voters = <&apps_bcm_voter>;
1369                 };
1370
1371                 system_noc: interconnect@1620000 {
1372                         compatible = "qcom,sc7180-system-noc";
1373                         reg = <0 0x01620000 0 0x17080>;
1374                         #interconnect-cells = <2>;
1375                         qcom,bcm-voters = <&apps_bcm_voter>;
1376                 };
1377
1378                 mc_virt: interconnect@1638000 {
1379                         compatible = "qcom,sc7180-mc-virt";
1380                         reg = <0 0x01638000 0 0x1000>;
1381                         #interconnect-cells = <2>;
1382                         qcom,bcm-voters = <&apps_bcm_voter>;
1383                 };
1384
1385                 qup_virt: interconnect@1650000 {
1386                         compatible = "qcom,sc7180-qup-virt";
1387                         reg = <0 0x01650000 0 0x1000>;
1388                         #interconnect-cells = <2>;
1389                         qcom,bcm-voters = <&apps_bcm_voter>;
1390                 };
1391
1392                 aggre1_noc: interconnect@16e0000 {
1393                         compatible = "qcom,sc7180-aggre1-noc";
1394                         reg = <0 0x016e0000 0 0x15080>;
1395                         #interconnect-cells = <2>;
1396                         qcom,bcm-voters = <&apps_bcm_voter>;
1397                 };
1398
1399                 aggre2_noc: interconnect@1705000 {
1400                         compatible = "qcom,sc7180-aggre2-noc";
1401                         reg = <0 0x01705000 0 0x9000>;
1402                         #interconnect-cells = <2>;
1403                         qcom,bcm-voters = <&apps_bcm_voter>;
1404                 };
1405
1406                 compute_noc: interconnect@170e000 {
1407                         compatible = "qcom,sc7180-compute-noc";
1408                         reg = <0 0x0170e000 0 0x6000>;
1409                         #interconnect-cells = <2>;
1410                         qcom,bcm-voters = <&apps_bcm_voter>;
1411                 };
1412
1413                 mmss_noc: interconnect@1740000 {
1414                         compatible = "qcom,sc7180-mmss-noc";
1415                         reg = <0 0x01740000 0 0x1c100>;
1416                         #interconnect-cells = <2>;
1417                         qcom,bcm-voters = <&apps_bcm_voter>;
1418                 };
1419
1420                 ipa_virt: interconnect@1e00000 {
1421                         compatible = "qcom,sc7180-ipa-virt";
1422                         reg = <0 0x01e00000 0 0x1000>;
1423                         #interconnect-cells = <2>;
1424                         qcom,bcm-voters = <&apps_bcm_voter>;
1425                 };
1426
1427                 ipa: ipa@1e40000 {
1428                         compatible = "qcom,sc7180-ipa";
1429
1430                         iommus = <&apps_smmu 0x440 0x0>,
1431                                  <&apps_smmu 0x442 0x0>;
1432                         reg = <0 0x1e40000 0 0x7000>,
1433                               <0 0x1e47000 0 0x2000>,
1434                               <0 0x1e04000 0 0x2c000>;
1435                         reg-names = "ipa-reg",
1436                                     "ipa-shared",
1437                                     "gsi";
1438
1439                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1440                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1441                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1442                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1443                         interrupt-names = "ipa",
1444                                           "gsi",
1445                                           "ipa-clock-query",
1446                                           "ipa-setup-ready";
1447
1448                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1449                         clock-names = "core";
1450
1451                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1452                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1453                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1454                         interconnect-names = "memory",
1455                                              "imem",
1456                                              "config";
1457
1458                         qcom,smem-states = <&ipa_smp2p_out 0>,
1459                                            <&ipa_smp2p_out 1>;
1460                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1461                                                 "ipa-clock-enabled";
1462
1463                         status = "disabled";
1464                 };
1465
1466                 tcsr_mutex_regs: syscon@1f40000 {
1467                         compatible = "syscon";
1468                         reg = <0 0x01f40000 0 0x40000>;
1469                 };
1470
1471                 tcsr_regs: syscon@1fc0000 {
1472                         compatible = "syscon";
1473                         reg = <0 0x01fc0000 0 0x40000>;
1474                 };
1475
1476                 tlmm: pinctrl@3500000 {
1477                         compatible = "qcom,sc7180-pinctrl";
1478                         reg = <0 0x03500000 0 0x300000>,
1479                               <0 0x03900000 0 0x300000>,
1480                               <0 0x03d00000 0 0x300000>;
1481                         reg-names = "west", "north", "south";
1482                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1483                         gpio-controller;
1484                         #gpio-cells = <2>;
1485                         interrupt-controller;
1486                         #interrupt-cells = <2>;
1487                         gpio-ranges = <&tlmm 0 0 120>;
1488                         wakeup-parent = <&pdc>;
1489
1490                         dp_hot_plug_det: dp-hot-plug-det {
1491                                 pinmux {
1492                                         pins = "gpio117";
1493                                         function = "dp_hot";
1494                                 };
1495                         };
1496
1497                         qspi_clk: qspi-clk {
1498                                 pinmux {
1499                                         pins = "gpio63";
1500                                         function = "qspi_clk";
1501                                 };
1502                         };
1503
1504                         qspi_cs0: qspi-cs0 {
1505                                 pinmux {
1506                                         pins = "gpio68";
1507                                         function = "qspi_cs";
1508                                 };
1509                         };
1510
1511                         qspi_cs1: qspi-cs1 {
1512                                 pinmux {
1513                                         pins = "gpio72";
1514                                         function = "qspi_cs";
1515                                 };
1516                         };
1517
1518                         qspi_data01: qspi-data01 {
1519                                 pinmux-data {
1520                                         pins = "gpio64", "gpio65";
1521                                         function = "qspi_data";
1522                                 };
1523                         };
1524
1525                         qspi_data12: qspi-data12 {
1526                                 pinmux-data {
1527                                         pins = "gpio66", "gpio67";
1528                                         function = "qspi_data";
1529                                 };
1530                         };
1531
1532                         qup_i2c0_default: qup-i2c0-default {
1533                                 pinmux {
1534                                         pins = "gpio34", "gpio35";
1535                                         function = "qup00";
1536                                 };
1537                         };
1538
1539                         qup_i2c1_default: qup-i2c1-default {
1540                                 pinmux {
1541                                         pins = "gpio0", "gpio1";
1542                                         function = "qup01";
1543                                 };
1544                         };
1545
1546                         qup_i2c2_default: qup-i2c2-default {
1547                                 pinmux {
1548                                         pins = "gpio15", "gpio16";
1549                                         function = "qup02_i2c";
1550                                 };
1551                         };
1552
1553                         qup_i2c3_default: qup-i2c3-default {
1554                                 pinmux {
1555                                         pins = "gpio38", "gpio39";
1556                                         function = "qup03";
1557                                 };
1558                         };
1559
1560                         qup_i2c4_default: qup-i2c4-default {
1561                                 pinmux {
1562                                         pins = "gpio115", "gpio116";
1563                                         function = "qup04_i2c";
1564                                 };
1565                         };
1566
1567                         qup_i2c5_default: qup-i2c5-default {
1568                                 pinmux {
1569                                         pins = "gpio25", "gpio26";
1570                                         function = "qup05";
1571                                 };
1572                         };
1573
1574                         qup_i2c6_default: qup-i2c6-default {
1575                                 pinmux {
1576                                         pins = "gpio59", "gpio60";
1577                                         function = "qup10";
1578                                 };
1579                         };
1580
1581                         qup_i2c7_default: qup-i2c7-default {
1582                                 pinmux {
1583                                         pins = "gpio6", "gpio7";
1584                                         function = "qup11_i2c";
1585                                 };
1586                         };
1587
1588                         qup_i2c8_default: qup-i2c8-default {
1589                                 pinmux {
1590                                         pins = "gpio42", "gpio43";
1591                                         function = "qup12";
1592                                 };
1593                         };
1594
1595                         qup_i2c9_default: qup-i2c9-default {
1596                                 pinmux {
1597                                         pins = "gpio46", "gpio47";
1598                                         function = "qup13_i2c";
1599                                 };
1600                         };
1601
1602                         qup_i2c10_default: qup-i2c10-default {
1603                                 pinmux {
1604                                         pins = "gpio86", "gpio87";
1605                                         function = "qup14";
1606                                 };
1607                         };
1608
1609                         qup_i2c11_default: qup-i2c11-default {
1610                                 pinmux {
1611                                         pins = "gpio53", "gpio54";
1612                                         function = "qup15";
1613                                 };
1614                         };
1615
1616                         qup_spi0_default: qup-spi0-default {
1617                                 pinmux {
1618                                         pins = "gpio34", "gpio35",
1619                                                "gpio36", "gpio37";
1620                                         function = "qup00";
1621                                 };
1622                         };
1623
1624                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1625                                 pinmux {
1626                                         pins = "gpio34", "gpio35",
1627                                                "gpio36";
1628                                         function = "qup00";
1629                                 };
1630
1631                                 pinmux-cs {
1632                                         pins = "gpio37";
1633                                         function = "gpio";
1634                                 };
1635                         };
1636
1637                         qup_spi1_default: qup-spi1-default {
1638                                 pinmux {
1639                                         pins = "gpio0", "gpio1",
1640                                                "gpio2", "gpio3";
1641                                         function = "qup01";
1642                                 };
1643                         };
1644
1645                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1646                                 pinmux {
1647                                         pins = "gpio0", "gpio1",
1648                                                "gpio2";
1649                                         function = "qup01";
1650                                 };
1651
1652                                 pinmux-cs {
1653                                         pins = "gpio3";
1654                                         function = "gpio";
1655                                 };
1656                         };
1657
1658                         qup_spi3_default: qup-spi3-default {
1659                                 pinmux {
1660                                         pins = "gpio38", "gpio39",
1661                                                "gpio40", "gpio41";
1662                                         function = "qup03";
1663                                 };
1664                         };
1665
1666                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1667                                 pinmux {
1668                                         pins = "gpio38", "gpio39",
1669                                                "gpio40";
1670                                         function = "qup03";
1671                                 };
1672
1673                                 pinmux-cs {
1674                                         pins = "gpio41";
1675                                         function = "gpio";
1676                                 };
1677                         };
1678
1679                         qup_spi5_default: qup-spi5-default {
1680                                 pinmux {
1681                                         pins = "gpio25", "gpio26",
1682                                                "gpio27", "gpio28";
1683                                         function = "qup05";
1684                                 };
1685                         };
1686
1687                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1688                                 pinmux {
1689                                         pins = "gpio25", "gpio26",
1690                                                "gpio27";
1691                                         function = "qup05";
1692                                 };
1693
1694                                 pinmux-cs {
1695                                         pins = "gpio28";
1696                                         function = "gpio";
1697                                 };
1698                         };
1699
1700                         qup_spi6_default: qup-spi6-default {
1701                                 pinmux {
1702                                         pins = "gpio59", "gpio60",
1703                                                "gpio61", "gpio62";
1704                                         function = "qup10";
1705                                 };
1706                         };
1707
1708                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1709                                 pinmux {
1710                                         pins = "gpio59", "gpio60",
1711                                                "gpio61";
1712                                         function = "qup10";
1713                                 };
1714
1715                                 pinmux-cs {
1716                                         pins = "gpio62";
1717                                         function = "gpio";
1718                                 };
1719                         };
1720
1721                         qup_spi8_default: qup-spi8-default {
1722                                 pinmux {
1723                                         pins = "gpio42", "gpio43",
1724                                                "gpio44", "gpio45";
1725                                         function = "qup12";
1726                                 };
1727                         };
1728
1729                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1730                                 pinmux {
1731                                         pins = "gpio42", "gpio43",
1732                                                "gpio44";
1733                                         function = "qup12";
1734                                 };
1735
1736                                 pinmux-cs {
1737                                         pins = "gpio45";
1738                                         function = "gpio";
1739                                 };
1740                         };
1741
1742                         qup_spi10_default: qup-spi10-default {
1743                                 pinmux {
1744                                         pins = "gpio86", "gpio87",
1745                                                "gpio88", "gpio89";
1746                                         function = "qup14";
1747                                 };
1748                         };
1749
1750                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1751                                 pinmux {
1752                                         pins = "gpio86", "gpio87",
1753                                                "gpio88";
1754                                         function = "qup14";
1755                                 };
1756
1757                                 pinmux-cs {
1758                                         pins = "gpio89";
1759                                         function = "gpio";
1760                                 };
1761                         };
1762
1763                         qup_spi11_default: qup-spi11-default {
1764                                 pinmux {
1765                                         pins = "gpio53", "gpio54",
1766                                                "gpio55", "gpio56";
1767                                         function = "qup15";
1768                                 };
1769                         };
1770
1771                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1772                                 pinmux {
1773                                         pins = "gpio53", "gpio54",
1774                                                "gpio55";
1775                                         function = "qup15";
1776                                 };
1777
1778                                 pinmux-cs {
1779                                         pins = "gpio56";
1780                                         function = "gpio";
1781                                 };
1782                         };
1783
1784                         qup_uart0_default: qup-uart0-default {
1785                                 pinmux {
1786                                         pins = "gpio34", "gpio35",
1787                                                "gpio36", "gpio37";
1788                                         function = "qup00";
1789                                 };
1790                         };
1791
1792                         qup_uart1_default: qup-uart1-default {
1793                                 pinmux {
1794                                         pins = "gpio0", "gpio1",
1795                                                "gpio2", "gpio3";
1796                                         function = "qup01";
1797                                 };
1798                         };
1799
1800                         qup_uart2_default: qup-uart2-default {
1801                                 pinmux {
1802                                         pins = "gpio15", "gpio16";
1803                                         function = "qup02_uart";
1804                                 };
1805                         };
1806
1807                         qup_uart3_default: qup-uart3-default {
1808                                 pinmux {
1809                                         pins = "gpio38", "gpio39",
1810                                                "gpio40", "gpio41";
1811                                         function = "qup03";
1812                                 };
1813                         };
1814
1815                         qup_uart4_default: qup-uart4-default {
1816                                 pinmux {
1817                                         pins = "gpio115", "gpio116";
1818                                         function = "qup04_uart";
1819                                 };
1820                         };
1821
1822                         qup_uart5_default: qup-uart5-default {
1823                                 pinmux {
1824                                         pins = "gpio25", "gpio26",
1825                                                "gpio27", "gpio28";
1826                                         function = "qup05";
1827                                 };
1828                         };
1829
1830                         qup_uart6_default: qup-uart6-default {
1831                                 pinmux {
1832                                         pins = "gpio59", "gpio60",
1833                                                "gpio61", "gpio62";
1834                                         function = "qup10";
1835                                 };
1836                         };
1837
1838                         qup_uart7_default: qup-uart7-default {
1839                                 pinmux {
1840                                         pins = "gpio6", "gpio7";
1841                                         function = "qup11_uart";
1842                                 };
1843                         };
1844
1845                         qup_uart8_default: qup-uart8-default {
1846                                 pinmux {
1847                                         pins = "gpio44", "gpio45";
1848                                         function = "qup12";
1849                                 };
1850                         };
1851
1852                         qup_uart9_default: qup-uart9-default {
1853                                 pinmux {
1854                                         pins = "gpio46", "gpio47";
1855                                         function = "qup13_uart";
1856                                 };
1857                         };
1858
1859                         qup_uart10_default: qup-uart10-default {
1860                                 pinmux {
1861                                         pins = "gpio86", "gpio87",
1862                                                "gpio88", "gpio89";
1863                                         function = "qup14";
1864                                 };
1865                         };
1866
1867                         qup_uart11_default: qup-uart11-default {
1868                                 pinmux {
1869                                         pins = "gpio53", "gpio54",
1870                                                "gpio55", "gpio56";
1871                                         function = "qup15";
1872                                 };
1873                         };
1874
1875                         sec_mi2s_active: sec-mi2s-active {
1876                                 pinmux {
1877                                         pins = "gpio49", "gpio50", "gpio51";
1878                                         function = "mi2s_1";
1879                                 };
1880                         };
1881
1882                         pri_mi2s_active: pri-mi2s-active {
1883                                 pinmux {
1884                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1885                                         function = "mi2s_0";
1886                                 };
1887                         };
1888
1889                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1890                                 pinmux {
1891                                         pins = "gpio57";
1892                                         function = "lpass_ext";
1893                                 };
1894                         };
1895                 };
1896
1897                 remoteproc_mpss: remoteproc@4080000 {
1898                         compatible = "qcom,sc7180-mpss-pas";
1899                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1900                         reg-names = "qdsp6", "rmb";
1901
1902                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1903                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1904                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1905                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1906                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1907                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1908                         interrupt-names = "wdog", "fatal", "ready", "handover",
1909                                           "stop-ack", "shutdown-ack";
1910
1911                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1912                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1913                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
1914                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1915                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1916                                  <&rpmhcc RPMH_CXO_CLK>;
1917                         clock-names = "iface", "bus", "nav", "snoc_axi",
1918                                       "mnoc_axi", "xo";
1919
1920                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1921                                         <&rpmhpd SC7180_CX>,
1922                                         <&rpmhpd SC7180_MX>,
1923                                         <&rpmhpd SC7180_MSS>;
1924                         power-domain-names = "load_state", "cx", "mx", "mss";
1925
1926                         memory-region = <&mpss_mem>;
1927
1928                         qcom,smem-states = <&modem_smp2p_out 0>;
1929                         qcom,smem-state-names = "stop";
1930
1931                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1932                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1933                         reset-names = "mss_restart", "pdc_reset";
1934
1935                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1936                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1937
1938                         status = "disabled";
1939
1940                         glink-edge {
1941                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1942                                 label = "modem";
1943                                 qcom,remote-pid = <1>;
1944                                 mboxes = <&apss_shared 12>;
1945                         };
1946                 };
1947
1948                 gpu: gpu@5000000 {
1949                         compatible = "qcom,adreno-618.0", "qcom,adreno";
1950                         #stream-id-cells = <16>;
1951                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1952                                 <0 0x05061000 0 0x800>;
1953                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1954                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1955                         iommus = <&adreno_smmu 0>;
1956                         operating-points-v2 = <&gpu_opp_table>;
1957                         qcom,gmu = <&gmu>;
1958
1959                         #cooling-cells = <2>;
1960
1961                         nvmem-cells = <&gpu_speed_bin>;
1962                         nvmem-cell-names = "speed_bin";
1963
1964                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1965                         interconnect-names = "gfx-mem";
1966
1967                         gpu_opp_table: opp-table {
1968                                 compatible = "operating-points-v2";
1969
1970                                 opp-825000000 {
1971                                         opp-hz = /bits/ 64 <825000000>;
1972                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1973                                         opp-peak-kBps = <8532000>;
1974                                         opp-supported-hw = <0x04>;
1975                                 };
1976
1977                                 opp-800000000 {
1978                                         opp-hz = /bits/ 64 <800000000>;
1979                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1980                                         opp-peak-kBps = <8532000>;
1981                                         opp-supported-hw = <0x07>;
1982                                 };
1983
1984                                 opp-650000000 {
1985                                         opp-hz = /bits/ 64 <650000000>;
1986                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1987                                         opp-peak-kBps = <7216000>;
1988                                         opp-supported-hw = <0x07>;
1989                                 };
1990
1991                                 opp-565000000 {
1992                                         opp-hz = /bits/ 64 <565000000>;
1993                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1994                                         opp-peak-kBps = <5412000>;
1995                                         opp-supported-hw = <0x07>;
1996                                 };
1997
1998                                 opp-430000000 {
1999                                         opp-hz = /bits/ 64 <430000000>;
2000                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2001                                         opp-peak-kBps = <5412000>;
2002                                         opp-supported-hw = <0x07>;
2003                                 };
2004
2005                                 opp-355000000 {
2006                                         opp-hz = /bits/ 64 <355000000>;
2007                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2008                                         opp-peak-kBps = <3072000>;
2009                                         opp-supported-hw = <0x07>;
2010                                 };
2011
2012                                 opp-267000000 {
2013                                         opp-hz = /bits/ 64 <267000000>;
2014                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2015                                         opp-peak-kBps = <3072000>;
2016                                         opp-supported-hw = <0x07>;
2017                                 };
2018
2019                                 opp-180000000 {
2020                                         opp-hz = /bits/ 64 <180000000>;
2021                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2022                                         opp-peak-kBps = <1804000>;
2023                                         opp-supported-hw = <0x07>;
2024                                 };
2025                         };
2026                 };
2027
2028                 adreno_smmu: iommu@5040000 {
2029                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2030                         reg = <0 0x05040000 0 0x10000>;
2031                         #iommu-cells = <1>;
2032                         #global-interrupts = <2>;
2033                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2034                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2035                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2036                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2037                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2038                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2039                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2040                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2041                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2042                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2043
2044                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2045                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2046                         clock-names = "bus", "iface";
2047
2048                         power-domains = <&gpucc CX_GDSC>;
2049                 };
2050
2051                 gmu: gmu@506a000 {
2052                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2053                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2054                                 <0 0x0b490000 0 0x10000>;
2055                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2056                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2057                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2058                         interrupt-names = "hfi", "gmu";
2059                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2060                                <&gpucc GPU_CC_CXO_CLK>,
2061                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2062                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2063                         clock-names = "gmu", "cxo", "axi", "memnoc";
2064                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2065                         power-domain-names = "cx", "gx";
2066                         iommus = <&adreno_smmu 5>;
2067                         operating-points-v2 = <&gmu_opp_table>;
2068
2069                         gmu_opp_table: opp-table {
2070                                 compatible = "operating-points-v2";
2071
2072                                 opp-200000000 {
2073                                         opp-hz = /bits/ 64 <200000000>;
2074                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2075                                 };
2076                         };
2077                 };
2078
2079                 gpucc: clock-controller@5090000 {
2080                         compatible = "qcom,sc7180-gpucc";
2081                         reg = <0 0x05090000 0 0x9000>;
2082                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2083                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2084                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2085                         clock-names = "bi_tcxo",
2086                                       "gcc_gpu_gpll0_clk_src",
2087                                       "gcc_gpu_gpll0_div_clk_src";
2088                         #clock-cells = <1>;
2089                         #reset-cells = <1>;
2090                         #power-domain-cells = <1>;
2091                 };
2092
2093                 stm@6002000 {
2094                         compatible = "arm,coresight-stm", "arm,primecell";
2095                         reg = <0 0x06002000 0 0x1000>,
2096                               <0 0x16280000 0 0x180000>;
2097                         reg-names = "stm-base", "stm-stimulus-base";
2098
2099                         clocks = <&aoss_qmp>;
2100                         clock-names = "apb_pclk";
2101
2102                         out-ports {
2103                                 port {
2104                                         stm_out: endpoint {
2105                                                 remote-endpoint = <&funnel0_in7>;
2106                                         };
2107                                 };
2108                         };
2109                 };
2110
2111                 funnel@6041000 {
2112                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2113                         reg = <0 0x06041000 0 0x1000>;
2114
2115                         clocks = <&aoss_qmp>;
2116                         clock-names = "apb_pclk";
2117
2118                         out-ports {
2119                                 port {
2120                                         funnel0_out: endpoint {
2121                                                 remote-endpoint = <&merge_funnel_in0>;
2122                                         };
2123                                 };
2124                         };
2125
2126                         in-ports {
2127                                 #address-cells = <1>;
2128                                 #size-cells = <0>;
2129
2130                                 port@7 {
2131                                         reg = <7>;
2132                                         funnel0_in7: endpoint {
2133                                                 remote-endpoint = <&stm_out>;
2134                                         };
2135                                 };
2136                         };
2137                 };
2138
2139                 funnel@6042000 {
2140                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2141                         reg = <0 0x06042000 0 0x1000>;
2142
2143                         clocks = <&aoss_qmp>;
2144                         clock-names = "apb_pclk";
2145
2146                         out-ports {
2147                                 port {
2148                                         funnel1_out: endpoint {
2149                                                 remote-endpoint = <&merge_funnel_in1>;
2150                                         };
2151                                 };
2152                         };
2153
2154                         in-ports {
2155                                 #address-cells = <1>;
2156                                 #size-cells = <0>;
2157
2158                                 port@4 {
2159                                         reg = <4>;
2160                                         funnel1_in4: endpoint {
2161                                                 remote-endpoint = <&apss_merge_funnel_out>;
2162                                         };
2163                                 };
2164                         };
2165                 };
2166
2167                 funnel@6045000 {
2168                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2169                         reg = <0 0x06045000 0 0x1000>;
2170
2171                         clocks = <&aoss_qmp>;
2172                         clock-names = "apb_pclk";
2173
2174                         out-ports {
2175                                 port {
2176                                         merge_funnel_out: endpoint {
2177                                                 remote-endpoint = <&swao_funnel_in>;
2178                                         };
2179                                 };
2180                         };
2181
2182                         in-ports {
2183                                 #address-cells = <1>;
2184                                 #size-cells = <0>;
2185
2186                                 port@0 {
2187                                         reg = <0>;
2188                                         merge_funnel_in0: endpoint {
2189                                                 remote-endpoint = <&funnel0_out>;
2190                                         };
2191                                 };
2192
2193                                 port@1 {
2194                                         reg = <1>;
2195                                         merge_funnel_in1: endpoint {
2196                                                 remote-endpoint = <&funnel1_out>;
2197                                         };
2198                                 };
2199                         };
2200                 };
2201
2202                 replicator@6046000 {
2203                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2204                         reg = <0 0x06046000 0 0x1000>;
2205
2206                         clocks = <&aoss_qmp>;
2207                         clock-names = "apb_pclk";
2208
2209                         out-ports {
2210                                 port {
2211                                         replicator_out: endpoint {
2212                                                 remote-endpoint = <&etr_in>;
2213                                         };
2214                                 };
2215                         };
2216
2217                         in-ports {
2218                                 port {
2219                                         replicator_in: endpoint {
2220                                                 remote-endpoint = <&swao_replicator_out>;
2221                                         };
2222                                 };
2223                         };
2224                 };
2225
2226                 etr@6048000 {
2227                         compatible = "arm,coresight-tmc", "arm,primecell";
2228                         reg = <0 0x06048000 0 0x1000>;
2229                         iommus = <&apps_smmu 0x04a0 0x20>;
2230
2231                         clocks = <&aoss_qmp>;
2232                         clock-names = "apb_pclk";
2233                         arm,scatter-gather;
2234
2235                         in-ports {
2236                                 port {
2237                                         etr_in: endpoint {
2238                                                 remote-endpoint = <&replicator_out>;
2239                                         };
2240                                 };
2241                         };
2242                 };
2243
2244                 funnel@6b04000 {
2245                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2246                         reg = <0 0x06b04000 0 0x1000>;
2247
2248                         clocks = <&aoss_qmp>;
2249                         clock-names = "apb_pclk";
2250
2251                         out-ports {
2252                                 port {
2253                                         swao_funnel_out: endpoint {
2254                                                 remote-endpoint = <&etf_in>;
2255                                         };
2256                                 };
2257                         };
2258
2259                         in-ports {
2260                                 #address-cells = <1>;
2261                                 #size-cells = <0>;
2262
2263                                 port@7 {
2264                                         reg = <7>;
2265                                         swao_funnel_in: endpoint {
2266                                                 remote-endpoint = <&merge_funnel_out>;
2267                                         };
2268                                 };
2269                         };
2270                 };
2271
2272                 etf@6b05000 {
2273                         compatible = "arm,coresight-tmc", "arm,primecell";
2274                         reg = <0 0x06b05000 0 0x1000>;
2275
2276                         clocks = <&aoss_qmp>;
2277                         clock-names = "apb_pclk";
2278
2279                         out-ports {
2280                                 port {
2281                                         etf_out: endpoint {
2282                                                 remote-endpoint = <&swao_replicator_in>;
2283                                         };
2284                                 };
2285                         };
2286
2287                         in-ports {
2288                                 port {
2289                                         etf_in: endpoint {
2290                                                 remote-endpoint = <&swao_funnel_out>;
2291                                         };
2292                                 };
2293                         };
2294                 };
2295
2296                 replicator@6b06000 {
2297                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2298                         reg = <0 0x06b06000 0 0x1000>;
2299
2300                         clocks = <&aoss_qmp>;
2301                         clock-names = "apb_pclk";
2302                         qcom,replicator-loses-context;
2303
2304                         out-ports {
2305                                 port {
2306                                         swao_replicator_out: endpoint {
2307                                                 remote-endpoint = <&replicator_in>;
2308                                         };
2309                                 };
2310                         };
2311
2312                         in-ports {
2313                                 port {
2314                                         swao_replicator_in: endpoint {
2315                                                 remote-endpoint = <&etf_out>;
2316                                         };
2317                                 };
2318                         };
2319                 };
2320
2321                 etm@7040000 {
2322                         compatible = "arm,coresight-etm4x", "arm,primecell";
2323                         reg = <0 0x07040000 0 0x1000>;
2324
2325                         cpu = <&CPU0>;
2326
2327                         clocks = <&aoss_qmp>;
2328                         clock-names = "apb_pclk";
2329                         arm,coresight-loses-context-with-cpu;
2330                         qcom,skip-power-up;
2331
2332                         out-ports {
2333                                 port {
2334                                         etm0_out: endpoint {
2335                                                 remote-endpoint = <&apss_funnel_in0>;
2336                                         };
2337                                 };
2338                         };
2339                 };
2340
2341                 etm@7140000 {
2342                         compatible = "arm,coresight-etm4x", "arm,primecell";
2343                         reg = <0 0x07140000 0 0x1000>;
2344
2345                         cpu = <&CPU1>;
2346
2347                         clocks = <&aoss_qmp>;
2348                         clock-names = "apb_pclk";
2349                         arm,coresight-loses-context-with-cpu;
2350                         qcom,skip-power-up;
2351
2352                         out-ports {
2353                                 port {
2354                                         etm1_out: endpoint {
2355                                                 remote-endpoint = <&apss_funnel_in1>;
2356                                         };
2357                                 };
2358                         };
2359                 };
2360
2361                 etm@7240000 {
2362                         compatible = "arm,coresight-etm4x", "arm,primecell";
2363                         reg = <0 0x07240000 0 0x1000>;
2364
2365                         cpu = <&CPU2>;
2366
2367                         clocks = <&aoss_qmp>;
2368                         clock-names = "apb_pclk";
2369                         arm,coresight-loses-context-with-cpu;
2370                         qcom,skip-power-up;
2371
2372                         out-ports {
2373                                 port {
2374                                         etm2_out: endpoint {
2375                                                 remote-endpoint = <&apss_funnel_in2>;
2376                                         };
2377                                 };
2378                         };
2379                 };
2380
2381                 etm@7340000 {
2382                         compatible = "arm,coresight-etm4x", "arm,primecell";
2383                         reg = <0 0x07340000 0 0x1000>;
2384
2385                         cpu = <&CPU3>;
2386
2387                         clocks = <&aoss_qmp>;
2388                         clock-names = "apb_pclk";
2389                         arm,coresight-loses-context-with-cpu;
2390                         qcom,skip-power-up;
2391
2392                         out-ports {
2393                                 port {
2394                                         etm3_out: endpoint {
2395                                                 remote-endpoint = <&apss_funnel_in3>;
2396                                         };
2397                                 };
2398                         };
2399                 };
2400
2401                 etm@7440000 {
2402                         compatible = "arm,coresight-etm4x", "arm,primecell";
2403                         reg = <0 0x07440000 0 0x1000>;
2404
2405                         cpu = <&CPU4>;
2406
2407                         clocks = <&aoss_qmp>;
2408                         clock-names = "apb_pclk";
2409                         arm,coresight-loses-context-with-cpu;
2410                         qcom,skip-power-up;
2411
2412                         out-ports {
2413                                 port {
2414                                         etm4_out: endpoint {
2415                                                 remote-endpoint = <&apss_funnel_in4>;
2416                                         };
2417                                 };
2418                         };
2419                 };
2420
2421                 etm@7540000 {
2422                         compatible = "arm,coresight-etm4x", "arm,primecell";
2423                         reg = <0 0x07540000 0 0x1000>;
2424
2425                         cpu = <&CPU5>;
2426
2427                         clocks = <&aoss_qmp>;
2428                         clock-names = "apb_pclk";
2429                         arm,coresight-loses-context-with-cpu;
2430                         qcom,skip-power-up;
2431
2432                         out-ports {
2433                                 port {
2434                                         etm5_out: endpoint {
2435                                                 remote-endpoint = <&apss_funnel_in5>;
2436                                         };
2437                                 };
2438                         };
2439                 };
2440
2441                 etm@7640000 {
2442                         compatible = "arm,coresight-etm4x", "arm,primecell";
2443                         reg = <0 0x07640000 0 0x1000>;
2444
2445                         cpu = <&CPU6>;
2446
2447                         clocks = <&aoss_qmp>;
2448                         clock-names = "apb_pclk";
2449                         arm,coresight-loses-context-with-cpu;
2450                         qcom,skip-power-up;
2451
2452                         out-ports {
2453                                 port {
2454                                         etm6_out: endpoint {
2455                                                 remote-endpoint = <&apss_funnel_in6>;
2456                                         };
2457                                 };
2458                         };
2459                 };
2460
2461                 etm@7740000 {
2462                         compatible = "arm,coresight-etm4x", "arm,primecell";
2463                         reg = <0 0x07740000 0 0x1000>;
2464
2465                         cpu = <&CPU7>;
2466
2467                         clocks = <&aoss_qmp>;
2468                         clock-names = "apb_pclk";
2469                         arm,coresight-loses-context-with-cpu;
2470                         qcom,skip-power-up;
2471
2472                         out-ports {
2473                                 port {
2474                                         etm7_out: endpoint {
2475                                                 remote-endpoint = <&apss_funnel_in7>;
2476                                         };
2477                                 };
2478                         };
2479                 };
2480
2481                 funnel@7800000 { /* APSS Funnel */
2482                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2483                         reg = <0 0x07800000 0 0x1000>;
2484
2485                         clocks = <&aoss_qmp>;
2486                         clock-names = "apb_pclk";
2487
2488                         out-ports {
2489                                 port {
2490                                         apss_funnel_out: endpoint {
2491                                                 remote-endpoint = <&apss_merge_funnel_in>;
2492                                         };
2493                                 };
2494                         };
2495
2496                         in-ports {
2497                                 #address-cells = <1>;
2498                                 #size-cells = <0>;
2499
2500                                 port@0 {
2501                                         reg = <0>;
2502                                         apss_funnel_in0: endpoint {
2503                                                 remote-endpoint = <&etm0_out>;
2504                                         };
2505                                 };
2506
2507                                 port@1 {
2508                                         reg = <1>;
2509                                         apss_funnel_in1: endpoint {
2510                                                 remote-endpoint = <&etm1_out>;
2511                                         };
2512                                 };
2513
2514                                 port@2 {
2515                                         reg = <2>;
2516                                         apss_funnel_in2: endpoint {
2517                                                 remote-endpoint = <&etm2_out>;
2518                                         };
2519                                 };
2520
2521                                 port@3 {
2522                                         reg = <3>;
2523                                         apss_funnel_in3: endpoint {
2524                                                 remote-endpoint = <&etm3_out>;
2525                                         };
2526                                 };
2527
2528                                 port@4 {
2529                                         reg = <4>;
2530                                         apss_funnel_in4: endpoint {
2531                                                 remote-endpoint = <&etm4_out>;
2532                                         };
2533                                 };
2534
2535                                 port@5 {
2536                                         reg = <5>;
2537                                         apss_funnel_in5: endpoint {
2538                                                 remote-endpoint = <&etm5_out>;
2539                                         };
2540                                 };
2541
2542                                 port@6 {
2543                                         reg = <6>;
2544                                         apss_funnel_in6: endpoint {
2545                                                 remote-endpoint = <&etm6_out>;
2546                                         };
2547                                 };
2548
2549                                 port@7 {
2550                                         reg = <7>;
2551                                         apss_funnel_in7: endpoint {
2552                                                 remote-endpoint = <&etm7_out>;
2553                                         };
2554                                 };
2555                         };
2556                 };
2557
2558                 funnel@7810000 {
2559                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2560                         reg = <0 0x07810000 0 0x1000>;
2561
2562                         clocks = <&aoss_qmp>;
2563                         clock-names = "apb_pclk";
2564
2565                         out-ports {
2566                                 port {
2567                                         apss_merge_funnel_out: endpoint {
2568                                                 remote-endpoint = <&funnel1_in4>;
2569                                         };
2570                                 };
2571                         };
2572
2573                         in-ports {
2574                                 port {
2575                                         apss_merge_funnel_in: endpoint {
2576                                                 remote-endpoint = <&apss_funnel_out>;
2577                                         };
2578                                 };
2579                         };
2580                 };
2581
2582                 sdhc_2: sdhci@8804000 {
2583                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2584                         reg = <0 0x08804000 0 0x1000>;
2585
2586                         iommus = <&apps_smmu 0x80 0>;
2587                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2588                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2589                         interrupt-names = "hc_irq", "pwr_irq";
2590
2591                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2592                                  <&gcc GCC_SDCC2_AHB_CLK>,
2593                                  <&rpmhcc RPMH_CXO_CLK>;
2594                         clock-names = "core", "iface", "xo";
2595
2596                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2597                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2598                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2599                         power-domains = <&rpmhpd SC7180_CX>;
2600                         operating-points-v2 = <&sdhc2_opp_table>;
2601
2602                         bus-width = <4>;
2603
2604                         status = "disabled";
2605
2606                         sdhc2_opp_table: sdhc2-opp-table {
2607                                 compatible = "operating-points-v2";
2608
2609                                 opp-100000000 {
2610                                         opp-hz = /bits/ 64 <100000000>;
2611                                         required-opps = <&rpmhpd_opp_low_svs>;
2612                                         opp-peak-kBps = <1800000 600000>;
2613                                         opp-avg-kBps = <100000 0>;
2614                                 };
2615
2616                                 opp-202000000 {
2617                                         opp-hz = /bits/ 64 <202000000>;
2618                                         required-opps = <&rpmhpd_opp_nom>;
2619                                         opp-peak-kBps = <5400000 1600000>;
2620                                         opp-avg-kBps = <200000 0>;
2621                                 };
2622                         };
2623                 };
2624
2625                 qspi_opp_table: qspi-opp-table {
2626                         compatible = "operating-points-v2";
2627
2628                         opp-75000000 {
2629                                 opp-hz = /bits/ 64 <75000000>;
2630                                 required-opps = <&rpmhpd_opp_low_svs>;
2631                         };
2632
2633                         opp-150000000 {
2634                                 opp-hz = /bits/ 64 <150000000>;
2635                                 required-opps = <&rpmhpd_opp_svs>;
2636                         };
2637
2638                         opp-300000000 {
2639                                 opp-hz = /bits/ 64 <300000000>;
2640                                 required-opps = <&rpmhpd_opp_nom>;
2641                         };
2642                 };
2643
2644                 qspi: spi@88dc000 {
2645                         compatible = "qcom,qspi-v1";
2646                         reg = <0 0x088dc000 0 0x600>;
2647                         #address-cells = <1>;
2648                         #size-cells = <0>;
2649                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2650                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2651                                  <&gcc GCC_QSPI_CORE_CLK>;
2652                         clock-names = "iface", "core";
2653                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2654                                         &config_noc SLAVE_QSPI_0 0>;
2655                         interconnect-names = "qspi-config";
2656                         power-domains = <&rpmhpd SC7180_CX>;
2657                         operating-points-v2 = <&qspi_opp_table>;
2658                         status = "disabled";
2659                 };
2660
2661                 usb_1_hsphy: phy@88e3000 {
2662                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2663                         reg = <0 0x088e3000 0 0x400>;
2664                         status = "disabled";
2665                         #phy-cells = <0>;
2666                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2667                                  <&rpmhcc RPMH_CXO_CLK>;
2668                         clock-names = "cfg_ahb", "ref";
2669                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2670
2671                         nvmem-cells = <&qusb2p_hstx_trim>;
2672                 };
2673
2674                 usb_1_qmpphy: phy-wrapper@88e9000 {
2675                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2676                         reg = <0 0x088e9000 0 0x18c>,
2677                               <0 0x088e8000 0 0x3c>,
2678                               <0 0x088ea000 0 0x18c>;
2679                         status = "disabled";
2680                         #address-cells = <2>;
2681                         #size-cells = <2>;
2682                         ranges;
2683
2684                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2685                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2686                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2687                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2688                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2689
2690                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2691                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2692                         reset-names = "phy", "common";
2693
2694                         usb_1_ssphy: usb3-phy@88e9200 {
2695                                 reg = <0 0x088e9200 0 0x128>,
2696                                       <0 0x088e9400 0 0x200>,
2697                                       <0 0x088e9c00 0 0x218>,
2698                                       <0 0x088e9600 0 0x128>,
2699                                       <0 0x088e9800 0 0x200>,
2700                                       <0 0x088e9a00 0 0x18>;
2701                                 #clock-cells = <0>;
2702                                 #phy-cells = <0>;
2703                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2704                                 clock-names = "pipe0";
2705                                 clock-output-names = "usb3_phy_pipe_clk_src";
2706                         };
2707
2708                         dp_phy: dp-phy@88ea200 {
2709                                 reg = <0 0x088ea200 0 0x200>,
2710                                       <0 0x088ea400 0 0x200>,
2711                                       <0 0x088eaa00 0 0x200>,
2712                                       <0 0x088ea600 0 0x200>,
2713                                       <0 0x088ea800 0 0x200>;
2714                                 #clock-cells = <1>;
2715                                 #phy-cells = <0>;
2716                         };
2717                 };
2718
2719                 dc_noc: interconnect@9160000 {
2720                         compatible = "qcom,sc7180-dc-noc";
2721                         reg = <0 0x09160000 0 0x03200>;
2722                         #interconnect-cells = <2>;
2723                         qcom,bcm-voters = <&apps_bcm_voter>;
2724                 };
2725
2726                 system-cache-controller@9200000 {
2727                         compatible = "qcom,sc7180-llcc";
2728                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2729                         reg-names = "llcc_base", "llcc_broadcast_base";
2730                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2731                 };
2732
2733                 gem_noc: interconnect@9680000 {
2734                         compatible = "qcom,sc7180-gem-noc";
2735                         reg = <0 0x09680000 0 0x3e200>;
2736                         #interconnect-cells = <2>;
2737                         qcom,bcm-voters = <&apps_bcm_voter>;
2738                 };
2739
2740                 npu_noc: interconnect@9990000 {
2741                         compatible = "qcom,sc7180-npu-noc";
2742                         reg = <0 0x09990000 0 0x1600>;
2743                         #interconnect-cells = <2>;
2744                         qcom,bcm-voters = <&apps_bcm_voter>;
2745                 };
2746
2747                 usb_1: usb@a6f8800 {
2748                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2749                         reg = <0 0x0a6f8800 0 0x400>;
2750                         status = "disabled";
2751                         #address-cells = <2>;
2752                         #size-cells = <2>;
2753                         ranges;
2754                         dma-ranges;
2755
2756                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2757                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2758                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2759                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2760                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2761                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2762                                       "sleep";
2763
2764                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2765                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2766                         assigned-clock-rates = <19200000>, <150000000>;
2767
2768                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2769                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2770                                               <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2771                                               <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2772                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2773                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2774
2775                         power-domains = <&gcc USB30_PRIM_GDSC>;
2776
2777                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2778
2779                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2780                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2781                         interconnect-names = "usb-ddr", "apps-usb";
2782
2783                         usb_1_dwc3: dwc3@a600000 {
2784                                 compatible = "snps,dwc3";
2785                                 reg = <0 0x0a600000 0 0xe000>;
2786                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2787                                 iommus = <&apps_smmu 0x540 0>;
2788                                 snps,dis_u2_susphy_quirk;
2789                                 snps,dis_enblslpm_quirk;
2790                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2791                                 phy-names = "usb2-phy", "usb3-phy";
2792                                 maximum-speed = "super-speed";
2793                         };
2794                 };
2795
2796                 venus: video-codec@aa00000 {
2797                         compatible = "qcom,sc7180-venus";
2798                         reg = <0 0x0aa00000 0 0xff000>;
2799                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2800                         power-domains = <&videocc VENUS_GDSC>,
2801                                         <&videocc VCODEC0_GDSC>,
2802                                         <&rpmhpd SC7180_CX>;
2803                         power-domain-names = "venus", "vcodec0", "cx";
2804                         operating-points-v2 = <&venus_opp_table>;
2805                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2806                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2807                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2808                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2809                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2810                         clock-names = "core", "iface", "bus",
2811                                       "vcodec0_core", "vcodec0_bus";
2812                         iommus = <&apps_smmu 0x0c00 0x60>;
2813                         memory-region = <&venus_mem>;
2814                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2815                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2816                         interconnect-names = "video-mem", "cpu-cfg";
2817
2818                         video-decoder {
2819                                 compatible = "venus-decoder";
2820                         };
2821
2822                         video-encoder {
2823                                 compatible = "venus-encoder";
2824                         };
2825
2826                         venus_opp_table: venus-opp-table {
2827                                 compatible = "operating-points-v2";
2828
2829                                 opp-150000000 {
2830                                         opp-hz = /bits/ 64 <150000000>;
2831                                         required-opps = <&rpmhpd_opp_low_svs>;
2832                                 };
2833
2834                                 opp-270000000 {
2835                                         opp-hz = /bits/ 64 <270000000>;
2836                                         required-opps = <&rpmhpd_opp_svs>;
2837                                 };
2838
2839                                 opp-340000000 {
2840                                         opp-hz = /bits/ 64 <340000000>;
2841                                         required-opps = <&rpmhpd_opp_svs_l1>;
2842                                 };
2843
2844                                 opp-434000000 {
2845                                         opp-hz = /bits/ 64 <434000000>;
2846                                         required-opps = <&rpmhpd_opp_nom>;
2847                                 };
2848
2849                                 opp-500000097 {
2850                                         opp-hz = /bits/ 64 <500000097>;
2851                                         required-opps = <&rpmhpd_opp_turbo>;
2852                                 };
2853                         };
2854                 };
2855
2856                 videocc: clock-controller@ab00000 {
2857                         compatible = "qcom,sc7180-videocc";
2858                         reg = <0 0x0ab00000 0 0x10000>;
2859                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2860                         clock-names = "bi_tcxo";
2861                         #clock-cells = <1>;
2862                         #reset-cells = <1>;
2863                         #power-domain-cells = <1>;
2864                 };
2865
2866                 camnoc_virt: interconnect@ac00000 {
2867                         compatible = "qcom,sc7180-camnoc-virt";
2868                         reg = <0 0x0ac00000 0 0x1000>;
2869                         #interconnect-cells = <2>;
2870                         qcom,bcm-voters = <&apps_bcm_voter>;
2871                 };
2872
2873                 camcc: clock-controller@ad00000 {
2874                         compatible = "qcom,sc7180-camcc";
2875                         reg = <0 0x0ad00000 0 0x10000>;
2876                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2877                                <&gcc GCC_CAMERA_AHB_CLK>,
2878                                <&gcc GCC_CAMERA_XO_CLK>;
2879                         clock-names = "bi_tcxo", "iface", "xo";
2880                         #clock-cells = <1>;
2881                         #reset-cells = <1>;
2882                         #power-domain-cells = <1>;
2883                 };
2884
2885                 mdss: mdss@ae00000 {
2886                         compatible = "qcom,sc7180-mdss";
2887                         reg = <0 0x0ae00000 0 0x1000>;
2888                         reg-names = "mdss";
2889
2890                         power-domains = <&dispcc MDSS_GDSC>;
2891
2892                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2893                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2894                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2895                         clock-names = "iface", "ahb", "core";
2896
2897                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2898                         assigned-clock-rates = <300000000>;
2899
2900                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2901                         interrupt-controller;
2902                         #interrupt-cells = <1>;
2903
2904                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2905                         interconnect-names = "mdp0-mem";
2906
2907                         iommus = <&apps_smmu 0x800 0x2>;
2908
2909                         #address-cells = <2>;
2910                         #size-cells = <2>;
2911                         ranges;
2912
2913                         status = "disabled";
2914
2915                         mdp: mdp@ae01000 {
2916                                 compatible = "qcom,sc7180-dpu";
2917                                 reg = <0 0x0ae01000 0 0x8f000>,
2918                                       <0 0x0aeb0000 0 0x2008>;
2919                                 reg-names = "mdp", "vbif";
2920
2921                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2922                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2923                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2924                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2925                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2926                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2927                                 clock-names = "bus", "iface", "rot", "lut", "core",
2928                                               "vsync";
2929                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2930                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2931                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
2932                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
2933                                 assigned-clock-rates = <300000000>,
2934                                                        <19200000>,
2935                                                        <19200000>,
2936                                                        <19200000>;
2937                                 operating-points-v2 = <&mdp_opp_table>;
2938                                 power-domains = <&rpmhpd SC7180_CX>;
2939
2940                                 interrupt-parent = <&mdss>;
2941                                 interrupts = <0>;
2942
2943                                 status = "disabled";
2944
2945                                 ports {
2946                                         #address-cells = <1>;
2947                                         #size-cells = <0>;
2948
2949                                         port@0 {
2950                                                 reg = <0>;
2951                                                 dpu_intf1_out: endpoint {
2952                                                         remote-endpoint = <&dsi0_in>;
2953                                                 };
2954                                         };
2955                                 };
2956
2957                                 mdp_opp_table: mdp-opp-table {
2958                                         compatible = "operating-points-v2";
2959
2960                                         opp-200000000 {
2961                                                 opp-hz = /bits/ 64 <200000000>;
2962                                                 required-opps = <&rpmhpd_opp_low_svs>;
2963                                         };
2964
2965                                         opp-300000000 {
2966                                                 opp-hz = /bits/ 64 <300000000>;
2967                                                 required-opps = <&rpmhpd_opp_svs>;
2968                                         };
2969
2970                                         opp-345000000 {
2971                                                 opp-hz = /bits/ 64 <345000000>;
2972                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2973                                         };
2974
2975                                         opp-460000000 {
2976                                                 opp-hz = /bits/ 64 <460000000>;
2977                                                 required-opps = <&rpmhpd_opp_nom>;
2978                                         };
2979                                 };
2980
2981                         };
2982
2983                         dsi0: dsi@ae94000 {
2984                                 compatible = "qcom,mdss-dsi-ctrl";
2985                                 reg = <0 0x0ae94000 0 0x400>;
2986                                 reg-names = "dsi_ctrl";
2987
2988                                 interrupt-parent = <&mdss>;
2989                                 interrupts = <4>;
2990
2991                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2992                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2993                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2994                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2995                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2996                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2997                                 clock-names = "byte",
2998                                               "byte_intf",
2999                                               "pixel",
3000                                               "core",
3001                                               "iface",
3002                                               "bus";
3003
3004                                 operating-points-v2 = <&dsi_opp_table>;
3005                                 power-domains = <&rpmhpd SC7180_CX>;
3006
3007                                 phys = <&dsi_phy>;
3008                                 phy-names = "dsi";
3009
3010                                 #address-cells = <1>;
3011                                 #size-cells = <0>;
3012
3013                                 status = "disabled";
3014
3015                                 ports {
3016                                         #address-cells = <1>;
3017                                         #size-cells = <0>;
3018
3019                                         port@0 {
3020                                                 reg = <0>;
3021                                                 dsi0_in: endpoint {
3022                                                         remote-endpoint = <&dpu_intf1_out>;
3023                                                 };
3024                                         };
3025
3026                                         port@1 {
3027                                                 reg = <1>;
3028                                                 dsi0_out: endpoint {
3029                                                 };
3030                                         };
3031                                 };
3032
3033                                 dsi_opp_table: dsi-opp-table {
3034                                         compatible = "operating-points-v2";
3035
3036                                         opp-187500000 {
3037                                                 opp-hz = /bits/ 64 <187500000>;
3038                                                 required-opps = <&rpmhpd_opp_low_svs>;
3039                                         };
3040
3041                                         opp-300000000 {
3042                                                 opp-hz = /bits/ 64 <300000000>;
3043                                                 required-opps = <&rpmhpd_opp_svs>;
3044                                         };
3045
3046                                         opp-358000000 {
3047                                                 opp-hz = /bits/ 64 <358000000>;
3048                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3049                                         };
3050                                 };
3051                         };
3052
3053                         dsi_phy: dsi-phy@ae94400 {
3054                                 compatible = "qcom,dsi-phy-10nm";
3055                                 reg = <0 0x0ae94400 0 0x200>,
3056                                       <0 0x0ae94600 0 0x280>,
3057                                       <0 0x0ae94a00 0 0x1e0>;
3058                                 reg-names = "dsi_phy",
3059                                             "dsi_phy_lane",
3060                                             "dsi_pll";
3061
3062                                 #clock-cells = <1>;
3063                                 #phy-cells = <0>;
3064
3065                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3066                                          <&rpmhcc RPMH_CXO_CLK>;
3067                                 clock-names = "iface", "ref";
3068
3069                                 status = "disabled";
3070                         };
3071                 };
3072
3073                 dispcc: clock-controller@af00000 {
3074                         compatible = "qcom,sc7180-dispcc";
3075                         reg = <0 0x0af00000 0 0x200000>;
3076                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3077                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3078                                  <&dsi_phy 0>,
3079                                  <&dsi_phy 1>,
3080                                  <&dp_phy 0>,
3081                                  <&dp_phy 1>;
3082                         clock-names = "bi_tcxo",
3083                                       "gcc_disp_gpll0_clk_src",
3084                                       "dsi0_phy_pll_out_byteclk",
3085                                       "dsi0_phy_pll_out_dsiclk",
3086                                       "dp_phy_pll_link_clk",
3087                                       "dp_phy_pll_vco_div_clk";
3088                         #clock-cells = <1>;
3089                         #reset-cells = <1>;
3090                         #power-domain-cells = <1>;
3091                 };
3092
3093                 pdc: interrupt-controller@b220000 {
3094                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3095                         reg = <0 0x0b220000 0 0x30000>;
3096                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3097                         #interrupt-cells = <2>;
3098                         interrupt-parent = <&intc>;
3099                         interrupt-controller;
3100                 };
3101
3102                 pdc_reset: reset-controller@b2e0000 {
3103                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3104                         reg = <0 0x0b2e0000 0 0x20000>;
3105                         #reset-cells = <1>;
3106                 };
3107
3108                 tsens0: thermal-sensor@c263000 {
3109                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3110                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3111                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3112                         #qcom,sensors = <15>;
3113                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3114                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3115                         interrupt-names = "uplow","critical";
3116                         #thermal-sensor-cells = <1>;
3117                 };
3118
3119                 tsens1: thermal-sensor@c265000 {
3120                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3121                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3122                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3123                         #qcom,sensors = <10>;
3124                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3125                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3126                         interrupt-names = "uplow","critical";
3127                         #thermal-sensor-cells = <1>;
3128                 };
3129
3130                 aoss_reset: reset-controller@c2a0000 {
3131                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3132                         reg = <0 0x0c2a0000 0 0x31000>;
3133                         #reset-cells = <1>;
3134                 };
3135
3136                 aoss_qmp: power-controller@c300000 {
3137                         compatible = "qcom,sc7180-aoss-qmp";
3138                         reg = <0 0x0c300000 0 0x100000>;
3139                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3140                         mboxes = <&apss_shared 0>;
3141
3142                         #clock-cells = <0>;
3143                         #power-domain-cells = <1>;
3144                 };
3145
3146                 spmi_bus: spmi@c440000 {
3147                         compatible = "qcom,spmi-pmic-arb";
3148                         reg = <0 0x0c440000 0 0x1100>,
3149                               <0 0x0c600000 0 0x2000000>,
3150                               <0 0x0e600000 0 0x100000>,
3151                               <0 0x0e700000 0 0xa0000>,
3152                               <0 0x0c40a000 0 0x26000>;
3153                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3154                         interrupt-names = "periph_irq";
3155                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3156                         qcom,ee = <0>;
3157                         qcom,channel = <0>;
3158                         #address-cells = <1>;
3159                         #size-cells = <1>;
3160                         interrupt-controller;
3161                         #interrupt-cells = <4>;
3162                         cell-index = <0>;
3163                 };
3164
3165                 apps_smmu: iommu@15000000 {
3166                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3167                         reg = <0 0x15000000 0 0x100000>;
3168                         #iommu-cells = <2>;
3169                         #global-interrupts = <1>;
3170                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3171                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3172                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3173                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3174                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3175                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3176                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3177                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3178                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3179                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3180                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3181                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3182                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3183                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3184                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3185                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3186                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3187                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3188                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3189                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3190                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3191                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3192                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3193                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3194                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3195                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3196                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3197                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3198                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3199                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3200                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3201                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3202                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3203                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3204                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3205                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3206                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3207                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3208                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3209                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3210                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3211                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3212                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3213                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3214                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3215                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3216                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3217                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3218                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3219                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3220                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3221                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3222                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3223                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3224                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3225                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3226                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3227                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3228                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3229                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3230                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3231                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3232                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3233                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3234                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3235                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3236                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3237                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3238                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3239                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3240                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3241                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3242                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3243                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3244                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3245                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3246                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3247                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3248                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3249                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3250                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3251                 };
3252
3253                 intc: interrupt-controller@17a00000 {
3254                         compatible = "arm,gic-v3";
3255                         #address-cells = <2>;
3256                         #size-cells = <2>;
3257                         ranges;
3258                         #interrupt-cells = <3>;
3259                         interrupt-controller;
3260                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3261                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3262                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3263
3264                         msi-controller@17a40000 {
3265                                 compatible = "arm,gic-v3-its";
3266                                 msi-controller;
3267                                 #msi-cells = <1>;
3268                                 reg = <0 0x17a40000 0 0x20000>;
3269                                 status = "disabled";
3270                         };
3271                 };
3272
3273                 apss_shared: mailbox@17c00000 {
3274                         compatible = "qcom,sc7180-apss-shared";
3275                         reg = <0 0x17c00000 0 0x10000>;
3276                         #mbox-cells = <1>;
3277                 };
3278
3279                 watchdog@17c10000 {
3280                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3281                         reg = <0 0x17c10000 0 0x1000>;
3282                         clocks = <&sleep_clk>;
3283                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3284                 };
3285
3286                 timer@17c20000{
3287                         #address-cells = <2>;
3288                         #size-cells = <2>;
3289                         ranges;
3290                         compatible = "arm,armv7-timer-mem";
3291                         reg = <0 0x17c20000 0 0x1000>;
3292
3293                         frame@17c21000 {
3294                                 frame-number = <0>;
3295                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3296                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3297                                 reg = <0 0x17c21000 0 0x1000>,
3298                                       <0 0x17c22000 0 0x1000>;
3299                         };
3300
3301                         frame@17c23000 {
3302                                 frame-number = <1>;
3303                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3304                                 reg = <0 0x17c23000 0 0x1000>;
3305                                 status = "disabled";
3306                         };
3307
3308                         frame@17c25000 {
3309                                 frame-number = <2>;
3310                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3311                                 reg = <0 0x17c25000 0 0x1000>;
3312                                 status = "disabled";
3313                         };
3314
3315                         frame@17c27000 {
3316                                 frame-number = <3>;
3317                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3318                                 reg = <0 0x17c27000 0 0x1000>;
3319                                 status = "disabled";
3320                         };
3321
3322                         frame@17c29000 {
3323                                 frame-number = <4>;
3324                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3325                                 reg = <0 0x17c29000 0 0x1000>;
3326                                 status = "disabled";
3327                         };
3328
3329                         frame@17c2b000 {
3330                                 frame-number = <5>;
3331                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3332                                 reg = <0 0x17c2b000 0 0x1000>;
3333                                 status = "disabled";
3334                         };
3335
3336                         frame@17c2d000 {
3337                                 frame-number = <6>;
3338                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3339                                 reg = <0 0x17c2d000 0 0x1000>;
3340                                 status = "disabled";
3341                         };
3342                 };
3343
3344                 apps_rsc: rsc@18200000 {
3345                         compatible = "qcom,rpmh-rsc";
3346                         reg = <0 0x18200000 0 0x10000>,
3347                               <0 0x18210000 0 0x10000>,
3348                               <0 0x18220000 0 0x10000>;
3349                         reg-names = "drv-0", "drv-1", "drv-2";
3350                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3351                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3352                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3353                         qcom,tcs-offset = <0xd00>;
3354                         qcom,drv-id = <2>;
3355                         qcom,tcs-config = <ACTIVE_TCS  2>,
3356                                           <SLEEP_TCS   3>,
3357                                           <WAKE_TCS    3>,
3358                                           <CONTROL_TCS 1>;
3359
3360                         rpmhcc: clock-controller {
3361                                 compatible = "qcom,sc7180-rpmh-clk";
3362                                 clocks = <&xo_board>;
3363                                 clock-names = "xo";
3364                                 #clock-cells = <1>;
3365                         };
3366
3367                         rpmhpd: power-controller {
3368                                 compatible = "qcom,sc7180-rpmhpd";
3369                                 #power-domain-cells = <1>;
3370                                 operating-points-v2 = <&rpmhpd_opp_table>;
3371
3372                                 rpmhpd_opp_table: opp-table {
3373                                         compatible = "operating-points-v2";
3374
3375                                         rpmhpd_opp_ret: opp1 {
3376                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3377                                         };
3378
3379                                         rpmhpd_opp_min_svs: opp2 {
3380                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3381                                         };
3382
3383                                         rpmhpd_opp_low_svs: opp3 {
3384                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3385                                         };
3386
3387                                         rpmhpd_opp_svs: opp4 {
3388                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3389                                         };
3390
3391                                         rpmhpd_opp_svs_l1: opp5 {
3392                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3393                                         };
3394
3395                                         rpmhpd_opp_svs_l2: opp6 {
3396                                                 opp-level = <224>;
3397                                         };
3398
3399                                         rpmhpd_opp_nom: opp7 {
3400                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3401                                         };
3402
3403                                         rpmhpd_opp_nom_l1: opp8 {
3404                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3405                                         };
3406
3407                                         rpmhpd_opp_nom_l2: opp9 {
3408                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3409                                         };
3410
3411                                         rpmhpd_opp_turbo: opp10 {
3412                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3413                                         };
3414
3415                                         rpmhpd_opp_turbo_l1: opp11 {
3416                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3417                                         };
3418                                 };
3419                         };
3420
3421                         apps_bcm_voter: bcm_voter {
3422                                 compatible = "qcom,bcm-voter";
3423                         };
3424                 };
3425
3426                 osm_l3: interconnect@18321000 {
3427                         compatible = "qcom,sc7180-osm-l3";
3428                         reg = <0 0x18321000 0 0x1400>;
3429
3430                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3431                         clock-names = "xo", "alternate";
3432
3433                         #interconnect-cells = <1>;
3434                 };
3435
3436                 cpufreq_hw: cpufreq@18323000 {
3437                         compatible = "qcom,cpufreq-hw";
3438                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3439                         reg-names = "freq-domain0", "freq-domain1";
3440
3441                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3442                         clock-names = "xo", "alternate";
3443
3444                         #freq-domain-cells = <1>;
3445                 };
3446
3447                 wifi: wifi@18800000 {
3448                         compatible = "qcom,wcn3990-wifi";
3449                         reg = <0 0x18800000 0 0x800000>;
3450                         reg-names = "membase";
3451                         iommus = <&apps_smmu 0xc0 0x1>;
3452                         interrupts =
3453                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3454                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3455                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3456                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3457                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3458                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3459                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3460                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3461                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3462                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3463                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3464                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3465                         memory-region = <&wlan_mem>;
3466                         qcom,msa-fixed-perm;
3467                         status = "disabled";
3468                 };
3469
3470                 lpasscc: clock-controller@62d00000 {
3471                         compatible = "qcom,sc7180-lpasscorecc";
3472                         reg = <0 0x62d00000 0 0x50000>,
3473                               <0 0x62780000 0 0x30000>;
3474                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3475                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3476                                  <&rpmhcc RPMH_CXO_CLK>;
3477                         clock-names = "iface", "bi_tcxo";
3478                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3479                         #clock-cells = <1>;
3480                         #power-domain-cells = <1>;
3481                 };
3482
3483                 lpass_cpu: lpass@62f00000 {
3484                         compatible = "qcom,sc7180-lpass-cpu";
3485
3486                         reg = <0 0x62f00000 0 0x29000>;
3487                         reg-names = "lpass-lpaif";
3488
3489                         iommus = <&apps_smmu 0x1020 0>,
3490                                 <&apps_smmu 0x1021 0>;
3491
3492                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3493
3494                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3495                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3496                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3497                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3498                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3499                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3500
3501                         clock-names = "pcnoc-sway-clk", "audio-core",
3502                                         "mclk0", "pcnoc-mport-clk",
3503                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3504
3505
3506                         #sound-dai-cells = <1>;
3507                         #address-cells = <1>;
3508                         #size-cells = <0>;
3509
3510                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3511                         interrupt-names = "lpass-irq-lpaif";
3512                 };
3513
3514                 lpass_hm: clock-controller@63000000 {
3515                         compatible = "qcom,sc7180-lpasshm";
3516                         reg = <0 0x63000000 0 0x28>;
3517                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3518                                  <&rpmhcc RPMH_CXO_CLK>;
3519                         clock-names = "iface", "bi_tcxo";
3520                         #clock-cells = <1>;
3521                         #power-domain-cells = <1>;
3522                 };
3523         };
3524
3525         thermal-zones {
3526                 cpu0_thermal: cpu0-thermal {
3527                         polling-delay-passive = <250>;
3528                         polling-delay = <0>;
3529
3530                         thermal-sensors = <&tsens0 1>;
3531                         sustainable-power = <768>;
3532
3533                         trips {
3534                                 cpu0_alert0: trip-point0 {
3535                                         temperature = <90000>;
3536                                         hysteresis = <2000>;
3537                                         type = "passive";
3538                                 };
3539
3540                                 cpu0_alert1: trip-point1 {
3541                                         temperature = <95000>;
3542                                         hysteresis = <2000>;
3543                                         type = "passive";
3544                                 };
3545
3546                                 cpu0_crit: cpu_crit {
3547                                         temperature = <110000>;
3548                                         hysteresis = <1000>;
3549                                         type = "critical";
3550                                 };
3551                         };
3552
3553                         cooling-maps {
3554                                 map0 {
3555                                         trip = <&cpu0_alert0>;
3556                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3557                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3558                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3559                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3560                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3561                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3562                                 };
3563                                 map1 {
3564                                         trip = <&cpu0_alert1>;
3565                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3566                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3567                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3568                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3569                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3570                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3571                                 };
3572                         };
3573                 };
3574
3575                 cpu1_thermal: cpu1-thermal {
3576                         polling-delay-passive = <250>;
3577                         polling-delay = <0>;
3578
3579                         thermal-sensors = <&tsens0 2>;
3580                         sustainable-power = <768>;
3581
3582                         trips {
3583                                 cpu1_alert0: trip-point0 {
3584                                         temperature = <90000>;
3585                                         hysteresis = <2000>;
3586                                         type = "passive";
3587                                 };
3588
3589                                 cpu1_alert1: trip-point1 {
3590                                         temperature = <95000>;
3591                                         hysteresis = <2000>;
3592                                         type = "passive";
3593                                 };
3594
3595                                 cpu1_crit: cpu_crit {
3596                                         temperature = <110000>;
3597                                         hysteresis = <1000>;
3598                                         type = "critical";
3599                                 };
3600                         };
3601
3602                         cooling-maps {
3603                                 map0 {
3604                                         trip = <&cpu1_alert0>;
3605                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3606                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3607                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3608                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3609                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3610                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3611                                 };
3612                                 map1 {
3613                                         trip = <&cpu1_alert1>;
3614                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3615                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3616                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3617                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3618                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3619                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3620                                 };
3621                         };
3622                 };
3623
3624                 cpu2_thermal: cpu2-thermal {
3625                         polling-delay-passive = <250>;
3626                         polling-delay = <0>;
3627
3628                         thermal-sensors = <&tsens0 3>;
3629                         sustainable-power = <768>;
3630
3631                         trips {
3632                                 cpu2_alert0: trip-point0 {
3633                                         temperature = <90000>;
3634                                         hysteresis = <2000>;
3635                                         type = "passive";
3636                                 };
3637
3638                                 cpu2_alert1: trip-point1 {
3639                                         temperature = <95000>;
3640                                         hysteresis = <2000>;
3641                                         type = "passive";
3642                                 };
3643
3644                                 cpu2_crit: cpu_crit {
3645                                         temperature = <110000>;
3646                                         hysteresis = <1000>;
3647                                         type = "critical";
3648                                 };
3649                         };
3650
3651                         cooling-maps {
3652                                 map0 {
3653                                         trip = <&cpu2_alert0>;
3654                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3655                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3660                                 };
3661                                 map1 {
3662                                         trip = <&cpu2_alert1>;
3663                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3666                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3667                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3668                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3669                                 };
3670                         };
3671                 };
3672
3673                 cpu3_thermal: cpu3-thermal {
3674                         polling-delay-passive = <250>;
3675                         polling-delay = <0>;
3676
3677                         thermal-sensors = <&tsens0 4>;
3678                         sustainable-power = <768>;
3679
3680                         trips {
3681                                 cpu3_alert0: trip-point0 {
3682                                         temperature = <90000>;
3683                                         hysteresis = <2000>;
3684                                         type = "passive";
3685                                 };
3686
3687                                 cpu3_alert1: trip-point1 {
3688                                         temperature = <95000>;
3689                                         hysteresis = <2000>;
3690                                         type = "passive";
3691                                 };
3692
3693                                 cpu3_crit: cpu_crit {
3694                                         temperature = <110000>;
3695                                         hysteresis = <1000>;
3696                                         type = "critical";
3697                                 };
3698                         };
3699
3700                         cooling-maps {
3701                                 map0 {
3702                                         trip = <&cpu3_alert0>;
3703                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3704                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3705                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3706                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3708                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3709                                 };
3710                                 map1 {
3711                                         trip = <&cpu3_alert1>;
3712                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3713                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3714                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3715                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3716                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3718                                 };
3719                         };
3720                 };
3721
3722                 cpu4_thermal: cpu4-thermal {
3723                         polling-delay-passive = <250>;
3724                         polling-delay = <0>;
3725
3726                         thermal-sensors = <&tsens0 5>;
3727                         sustainable-power = <768>;
3728
3729                         trips {
3730                                 cpu4_alert0: trip-point0 {
3731                                         temperature = <90000>;
3732                                         hysteresis = <2000>;
3733                                         type = "passive";
3734                                 };
3735
3736                                 cpu4_alert1: trip-point1 {
3737                                         temperature = <95000>;
3738                                         hysteresis = <2000>;
3739                                         type = "passive";
3740                                 };
3741
3742                                 cpu4_crit: cpu_crit {
3743                                         temperature = <110000>;
3744                                         hysteresis = <1000>;
3745                                         type = "critical";
3746                                 };
3747                         };
3748
3749                         cooling-maps {
3750                                 map0 {
3751                                         trip = <&cpu4_alert0>;
3752                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3754                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3755                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3756                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3757                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3758                                 };
3759                                 map1 {
3760                                         trip = <&cpu4_alert1>;
3761                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3762                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3763                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3764                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3765                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3766                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3767                                 };
3768                         };
3769                 };
3770
3771                 cpu5_thermal: cpu5-thermal {
3772                         polling-delay-passive = <250>;
3773                         polling-delay = <0>;
3774
3775                         thermal-sensors = <&tsens0 6>;
3776                         sustainable-power = <768>;
3777
3778                         trips {
3779                                 cpu5_alert0: trip-point0 {
3780                                         temperature = <90000>;
3781                                         hysteresis = <2000>;
3782                                         type = "passive";
3783                                 };
3784
3785                                 cpu5_alert1: trip-point1 {
3786                                         temperature = <95000>;
3787                                         hysteresis = <2000>;
3788                                         type = "passive";
3789                                 };
3790
3791                                 cpu5_crit: cpu_crit {
3792                                         temperature = <110000>;
3793                                         hysteresis = <1000>;
3794                                         type = "critical";
3795                                 };
3796                         };
3797
3798                         cooling-maps {
3799                                 map0 {
3800                                         trip = <&cpu5_alert0>;
3801                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3804                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3805                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3806                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3807                                 };
3808                                 map1 {
3809                                         trip = <&cpu5_alert1>;
3810                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3811                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3812                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3813                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3816                                 };
3817                         };
3818                 };
3819
3820                 cpu6_thermal: cpu6-thermal {
3821                         polling-delay-passive = <250>;
3822                         polling-delay = <0>;
3823
3824                         thermal-sensors = <&tsens0 9>;
3825                         sustainable-power = <1202>;
3826
3827                         trips {
3828                                 cpu6_alert0: trip-point0 {
3829                                         temperature = <90000>;
3830                                         hysteresis = <2000>;
3831                                         type = "passive";
3832                                 };
3833
3834                                 cpu6_alert1: trip-point1 {
3835                                         temperature = <95000>;
3836                                         hysteresis = <2000>;
3837                                         type = "passive";
3838                                 };
3839
3840                                 cpu6_crit: cpu_crit {
3841                                         temperature = <110000>;
3842                                         hysteresis = <1000>;
3843                                         type = "critical";
3844                                 };
3845                         };
3846
3847                         cooling-maps {
3848                                 map0 {
3849                                         trip = <&cpu6_alert0>;
3850                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3851                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3852                                 };
3853                                 map1 {
3854                                         trip = <&cpu6_alert1>;
3855                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3856                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3857                                 };
3858                         };
3859                 };
3860
3861                 cpu7_thermal: cpu7-thermal {
3862                         polling-delay-passive = <250>;
3863                         polling-delay = <0>;
3864
3865                         thermal-sensors = <&tsens0 10>;
3866                         sustainable-power = <1202>;
3867
3868                         trips {
3869                                 cpu7_alert0: trip-point0 {
3870                                         temperature = <90000>;
3871                                         hysteresis = <2000>;
3872                                         type = "passive";
3873                                 };
3874
3875                                 cpu7_alert1: trip-point1 {
3876                                         temperature = <95000>;
3877                                         hysteresis = <2000>;
3878                                         type = "passive";
3879                                 };
3880
3881                                 cpu7_crit: cpu_crit {
3882                                         temperature = <110000>;
3883                                         hysteresis = <1000>;
3884                                         type = "critical";
3885                                 };
3886                         };
3887
3888                         cooling-maps {
3889                                 map0 {
3890                                         trip = <&cpu7_alert0>;
3891                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3892                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3893                                 };
3894                                 map1 {
3895                                         trip = <&cpu7_alert1>;
3896                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3897                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3898                                 };
3899                         };
3900                 };
3901
3902                 cpu8_thermal: cpu8-thermal {
3903                         polling-delay-passive = <250>;
3904                         polling-delay = <0>;
3905
3906                         thermal-sensors = <&tsens0 11>;
3907                         sustainable-power = <1202>;
3908
3909                         trips {
3910                                 cpu8_alert0: trip-point0 {
3911                                         temperature = <90000>;
3912                                         hysteresis = <2000>;
3913                                         type = "passive";
3914                                 };
3915
3916                                 cpu8_alert1: trip-point1 {
3917                                         temperature = <95000>;
3918                                         hysteresis = <2000>;
3919                                         type = "passive";
3920                                 };
3921
3922                                 cpu8_crit: cpu_crit {
3923                                         temperature = <110000>;
3924                                         hysteresis = <1000>;
3925                                         type = "critical";
3926                                 };
3927                         };
3928
3929                         cooling-maps {
3930                                 map0 {
3931                                         trip = <&cpu8_alert0>;
3932                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3933                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3934                                 };
3935                                 map1 {
3936                                         trip = <&cpu8_alert1>;
3937                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3938                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3939                                 };
3940                         };
3941                 };
3942
3943                 cpu9_thermal: cpu9-thermal {
3944                         polling-delay-passive = <250>;
3945                         polling-delay = <0>;
3946
3947                         thermal-sensors = <&tsens0 12>;
3948                         sustainable-power = <1202>;
3949
3950                         trips {
3951                                 cpu9_alert0: trip-point0 {
3952                                         temperature = <90000>;
3953                                         hysteresis = <2000>;
3954                                         type = "passive";
3955                                 };
3956
3957                                 cpu9_alert1: trip-point1 {
3958                                         temperature = <95000>;
3959                                         hysteresis = <2000>;
3960                                         type = "passive";
3961                                 };
3962
3963                                 cpu9_crit: cpu_crit {
3964                                         temperature = <110000>;
3965                                         hysteresis = <1000>;
3966                                         type = "critical";
3967                                 };
3968                         };
3969
3970                         cooling-maps {
3971                                 map0 {
3972                                         trip = <&cpu9_alert0>;
3973                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3974                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3975                                 };
3976                                 map1 {
3977                                         trip = <&cpu9_alert1>;
3978                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3979                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3980                                 };
3981                         };
3982                 };
3983
3984                 aoss0-thermal {
3985                         polling-delay-passive = <250>;
3986                         polling-delay = <0>;
3987
3988                         thermal-sensors = <&tsens0 0>;
3989
3990                         trips {
3991                                 aoss0_alert0: trip-point0 {
3992                                         temperature = <90000>;
3993                                         hysteresis = <2000>;
3994                                         type = "hot";
3995                                 };
3996
3997                                 aoss0_crit: aoss0_crit {
3998                                         temperature = <110000>;
3999                                         hysteresis = <2000>;
4000                                         type = "critical";
4001                                 };
4002                         };
4003                 };
4004
4005                 cpuss0-thermal {
4006                         polling-delay-passive = <250>;
4007                         polling-delay = <0>;
4008
4009                         thermal-sensors = <&tsens0 7>;
4010
4011                         trips {
4012                                 cpuss0_alert0: trip-point0 {
4013                                         temperature = <90000>;
4014                                         hysteresis = <2000>;
4015                                         type = "hot";
4016                                 };
4017                                 cpuss0_crit: cluster0_crit {
4018                                         temperature = <110000>;
4019                                         hysteresis = <2000>;
4020                                         type = "critical";
4021                                 };
4022                         };
4023                 };
4024
4025                 cpuss1-thermal {
4026                         polling-delay-passive = <250>;
4027                         polling-delay = <0>;
4028
4029                         thermal-sensors = <&tsens0 8>;
4030
4031                         trips {
4032                                 cpuss1_alert0: trip-point0 {
4033                                         temperature = <90000>;
4034                                         hysteresis = <2000>;
4035                                         type = "hot";
4036                                 };
4037                                 cpuss1_crit: cluster0_crit {
4038                                         temperature = <110000>;
4039                                         hysteresis = <2000>;
4040                                         type = "critical";
4041                                 };
4042                         };
4043                 };
4044
4045                 gpuss0-thermal {
4046                         polling-delay-passive = <250>;
4047                         polling-delay = <0>;
4048
4049                         thermal-sensors = <&tsens0 13>;
4050
4051                         trips {
4052                                 gpuss0_alert0: trip-point0 {
4053                                         temperature = <95000>;
4054                                         hysteresis = <2000>;
4055                                         type = "passive";
4056                                 };
4057
4058                                 gpuss0_crit: gpuss0_crit {
4059                                         temperature = <110000>;
4060                                         hysteresis = <2000>;
4061                                         type = "critical";
4062                                 };
4063                         };
4064
4065                         cooling-maps {
4066                                 map0 {
4067                                         trip = <&gpuss0_alert0>;
4068                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4069                                 };
4070                         };
4071                 };
4072
4073                 gpuss1-thermal {
4074                         polling-delay-passive = <250>;
4075                         polling-delay = <0>;
4076
4077                         thermal-sensors = <&tsens0 14>;
4078
4079                         trips {
4080                                 gpuss1_alert0: trip-point0 {
4081                                         temperature = <95000>;
4082                                         hysteresis = <2000>;
4083                                         type = "passive";
4084                                 };
4085
4086                                 gpuss1_crit: gpuss1_crit {
4087                                         temperature = <110000>;
4088                                         hysteresis = <2000>;
4089                                         type = "critical";
4090                                 };
4091                         };
4092
4093                         cooling-maps {
4094                                 map0 {
4095                                         trip = <&gpuss1_alert0>;
4096                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4097                                 };
4098                         };
4099                 };
4100
4101                 aoss1-thermal {
4102                         polling-delay-passive = <250>;
4103                         polling-delay = <0>;
4104
4105                         thermal-sensors = <&tsens1 0>;
4106
4107                         trips {
4108                                 aoss1_alert0: trip-point0 {
4109                                         temperature = <90000>;
4110                                         hysteresis = <2000>;
4111                                         type = "hot";
4112                                 };
4113
4114                                 aoss1_crit: aoss1_crit {
4115                                         temperature = <110000>;
4116                                         hysteresis = <2000>;
4117                                         type = "critical";
4118                                 };
4119                         };
4120                 };
4121
4122                 cwlan-thermal {
4123                         polling-delay-passive = <250>;
4124                         polling-delay = <0>;
4125
4126                         thermal-sensors = <&tsens1 1>;
4127
4128                         trips {
4129                                 cwlan_alert0: trip-point0 {
4130                                         temperature = <90000>;
4131                                         hysteresis = <2000>;
4132                                         type = "hot";
4133                                 };
4134
4135                                 cwlan_crit: cwlan_crit {
4136                                         temperature = <110000>;
4137                                         hysteresis = <2000>;
4138                                         type = "critical";
4139                                 };
4140                         };
4141                 };
4142
4143                 audio-thermal {
4144                         polling-delay-passive = <250>;
4145                         polling-delay = <0>;
4146
4147                         thermal-sensors = <&tsens1 2>;
4148
4149                         trips {
4150                                 audio_alert0: trip-point0 {
4151                                         temperature = <90000>;
4152                                         hysteresis = <2000>;
4153                                         type = "hot";
4154                                 };
4155
4156                                 audio_crit: audio_crit {
4157                                         temperature = <110000>;
4158                                         hysteresis = <2000>;
4159                                         type = "critical";
4160                                 };
4161                         };
4162                 };
4163
4164                 ddr-thermal {
4165                         polling-delay-passive = <250>;
4166                         polling-delay = <0>;
4167
4168                         thermal-sensors = <&tsens1 3>;
4169
4170                         trips {
4171                                 ddr_alert0: trip-point0 {
4172                                         temperature = <90000>;
4173                                         hysteresis = <2000>;
4174                                         type = "hot";
4175                                 };
4176
4177                                 ddr_crit: ddr_crit {
4178                                         temperature = <110000>;
4179                                         hysteresis = <2000>;
4180                                         type = "critical";
4181                                 };
4182                         };
4183                 };
4184
4185                 q6-hvx-thermal {
4186                         polling-delay-passive = <250>;
4187                         polling-delay = <0>;
4188
4189                         thermal-sensors = <&tsens1 4>;
4190
4191                         trips {
4192                                 q6_hvx_alert0: trip-point0 {
4193                                         temperature = <90000>;
4194                                         hysteresis = <2000>;
4195                                         type = "hot";
4196                                 };
4197
4198                                 q6_hvx_crit: q6_hvx_crit {
4199                                         temperature = <110000>;
4200                                         hysteresis = <2000>;
4201                                         type = "critical";
4202                                 };
4203                         };
4204                 };
4205
4206                 camera-thermal {
4207                         polling-delay-passive = <250>;
4208                         polling-delay = <0>;
4209
4210                         thermal-sensors = <&tsens1 5>;
4211
4212                         trips {
4213                                 camera_alert0: trip-point0 {
4214                                         temperature = <90000>;
4215                                         hysteresis = <2000>;
4216                                         type = "hot";
4217                                 };
4218
4219                                 camera_crit: camera_crit {
4220                                         temperature = <110000>;
4221                                         hysteresis = <2000>;
4222                                         type = "critical";
4223                                 };
4224                         };
4225                 };
4226
4227                 mdm-core-thermal {
4228                         polling-delay-passive = <250>;
4229                         polling-delay = <0>;
4230
4231                         thermal-sensors = <&tsens1 6>;
4232
4233                         trips {
4234                                 mdm_alert0: trip-point0 {
4235                                         temperature = <90000>;
4236                                         hysteresis = <2000>;
4237                                         type = "hot";
4238                                 };
4239
4240                                 mdm_crit: mdm_crit {
4241                                         temperature = <110000>;
4242                                         hysteresis = <2000>;
4243                                         type = "critical";
4244                                 };
4245                         };
4246                 };
4247
4248                 mdm-dsp-thermal {
4249                         polling-delay-passive = <250>;
4250                         polling-delay = <0>;
4251
4252                         thermal-sensors = <&tsens1 7>;
4253
4254                         trips {
4255                                 mdm_dsp_alert0: trip-point0 {
4256                                         temperature = <90000>;
4257                                         hysteresis = <2000>;
4258                                         type = "hot";
4259                                 };
4260
4261                                 mdm_dsp_crit: mdm_dsp_crit {
4262                                         temperature = <110000>;
4263                                         hysteresis = <2000>;
4264                                         type = "critical";
4265                                 };
4266                         };
4267                 };
4268
4269                 npu-thermal {
4270                         polling-delay-passive = <250>;
4271                         polling-delay = <0>;
4272
4273                         thermal-sensors = <&tsens1 8>;
4274
4275                         trips {
4276                                 npu_alert0: trip-point0 {
4277                                         temperature = <90000>;
4278                                         hysteresis = <2000>;
4279                                         type = "hot";
4280                                 };
4281
4282                                 npu_crit: npu_crit {
4283                                         temperature = <110000>;
4284                                         hysteresis = <2000>;
4285                                         type = "critical";
4286                                 };
4287                         };
4288                 };
4289
4290                 video-thermal {
4291                         polling-delay-passive = <250>;
4292                         polling-delay = <0>;
4293
4294                         thermal-sensors = <&tsens1 9>;
4295
4296                         trips {
4297                                 video_alert0: trip-point0 {
4298                                         temperature = <90000>;
4299                                         hysteresis = <2000>;
4300                                         type = "hot";
4301                                 };
4302
4303                                 video_crit: video_crit {
4304                                         temperature = <110000>;
4305                                         hysteresis = <2000>;
4306                                         type = "critical";
4307                                 };
4308                         };
4309                 };
4310         };
4311
4312         timer {
4313                 compatible = "arm,armv8-timer";
4314                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4315                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4316                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4317                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4318         };
4319 };