arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/interconnect/qcom,icc.h>
  16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  17 #include <dt-bindings/interconnect/qcom,sc7180.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/phy/phy-qcom-qmp.h>
  20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/soc/qcom,apr.h>
  26 #include <dt-bindings/sound/qcom,q6afe.h>
  27 #include <dt-bindings/thermal/thermal.h>
  28
  29 / {
  30         interrupt-parent = <&intc>;
  31
  32         #address-cells = <2>;
  33         #size-cells = <2>;
  34
  35         aliases {
  36                 mmc1 = &sdhc_1;
  37                 mmc2 = &sdhc_2;
  38                 i2c0 = &i2c0;
  39                 i2c1 = &i2c1;
  40                 i2c2 = &i2c2;
  41                 i2c3 = &i2c3;
  42                 i2c4 = &i2c4;
  43                 i2c5 = &i2c5;
  44                 i2c6 = &i2c6;
  45                 i2c7 = &i2c7;
  46                 i2c8 = &i2c8;
  47                 i2c9 = &i2c9;
  48                 i2c10 = &i2c10;
  49                 i2c11 = &i2c11;
  50                 spi0 = &spi0;
  51                 spi1 = &spi1;
  52                 spi3 = &spi3;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi8 = &spi8;
  56                 spi10 = &spi10;
  57                 spi11 = &spi11;
  58         };
  59
  60         chosen { };
  61
  62         clocks {
  63                 xo_board: xo-board {
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <38400000>;
  66                         #clock-cells = <0>;
  67                 };
  68
  69                 sleep_clk: sleep-clk {
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32764>;
  72                         #clock-cells = <0>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <2>;
  78                 #size-cells = <0>;
  79
  80                 CPU0: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "qcom,kryo468";
  83                         reg = <0x0 0x0>;
  84                         clocks = <&cpufreq_hw 0>;
  85                         enable-method = "psci";
  86                         power-domains = <&CPU_PD0>;
  87                         power-domain-names = "psci";
  88                         capacity-dmips-mhz = <415>;
  89                         dynamic-power-coefficient = <137>;
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  92                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  93                         next-level-cache = <&L2_0>;
  94                         #cooling-cells = <2>;
  95                         qcom,freq-domain = <&cpufreq_hw 0>;
  96                         L2_0: l2-cache {
  97                                 compatible = "cache";
  98                                 cache-level = <2>;
  99                                 cache-unified;
 100                                 next-level-cache = <&L3_0>;
 101                                 L3_0: l3-cache {
 102                                         compatible = "cache";
 103                                         cache-level = <3>;
 104                                         cache-unified;
 105                                 };
 106                         };
 107                 };
 108
 109                 CPU1: cpu@100 {
 110                         device_type = "cpu";
 111                         compatible = "qcom,kryo468";
 112                         reg = <0x0 0x100>;
 113                         clocks = <&cpufreq_hw 0>;
 114                         enable-method = "psci";
 115                         power-domains = <&CPU_PD1>;
 116                         power-domain-names = "psci";
 117                         capacity-dmips-mhz = <415>;
 118                         dynamic-power-coefficient = <137>;
 119                         next-level-cache = <&L2_100>;
 120                         operating-points-v2 = <&cpu0_opp_table>;
 121                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 122                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 123                         #cooling-cells = <2>;
 124                         qcom,freq-domain = <&cpufreq_hw 0>;
 125                         L2_100: l2-cache {
 126                                 compatible = "cache";
 127                                 cache-level = <2>;
 128                                 cache-unified;
 129                                 next-level-cache = <&L3_0>;
 130                         };
 131                 };
 132
 133                 CPU2: cpu@200 {
 134                         device_type = "cpu";
 135                         compatible = "qcom,kryo468";
 136                         reg = <0x0 0x200>;
 137                         clocks = <&cpufreq_hw 0>;
 138                         enable-method = "psci";
 139                         power-domains = <&CPU_PD2>;
 140                         power-domain-names = "psci";
 141                         capacity-dmips-mhz = <415>;
 142                         dynamic-power-coefficient = <137>;
 143                         next-level-cache = <&L2_200>;
 144                         operating-points-v2 = <&cpu0_opp_table>;
 145                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 146                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 147                         #cooling-cells = <2>;
 148                         qcom,freq-domain = <&cpufreq_hw 0>;
 149                         L2_200: l2-cache {
 150                                 compatible = "cache";
 151                                 cache-level = <2>;
 152                                 cache-unified;
 153                                 next-level-cache = <&L3_0>;
 154                         };
 155                 };
 156
 157                 CPU3: cpu@300 {
 158                         device_type = "cpu";
 159                         compatible = "qcom,kryo468";
 160                         reg = <0x0 0x300>;
 161                         clocks = <&cpufreq_hw 0>;
 162                         enable-method = "psci";
 163                         power-domains = <&CPU_PD3>;
 164                         power-domain-names = "psci";
 165                         capacity-dmips-mhz = <415>;
 166                         dynamic-power-coefficient = <137>;
 167                         next-level-cache = <&L2_300>;
 168                         operating-points-v2 = <&cpu0_opp_table>;
 169                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 170                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 171                         #cooling-cells = <2>;
 172                         qcom,freq-domain = <&cpufreq_hw 0>;
 173                         L2_300: l2-cache {
 174                                 compatible = "cache";
 175                                 cache-level = <2>;
 176                                 cache-unified;
 177                                 next-level-cache = <&L3_0>;
 178                         };
 179                 };
 180
 181                 CPU4: cpu@400 {
 182                         device_type = "cpu";
 183                         compatible = "qcom,kryo468";
 184                         reg = <0x0 0x400>;
 185                         clocks = <&cpufreq_hw 0>;
 186                         enable-method = "psci";
 187                         power-domains = <&CPU_PD4>;
 188                         power-domain-names = "psci";
 189                         capacity-dmips-mhz = <415>;
 190                         dynamic-power-coefficient = <137>;
 191                         next-level-cache = <&L2_400>;
 192                         operating-points-v2 = <&cpu0_opp_table>;
 193                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 194                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 195                         #cooling-cells = <2>;
 196                         qcom,freq-domain = <&cpufreq_hw 0>;
 197                         L2_400: l2-cache {
 198                                 compatible = "cache";
 199                                 cache-level = <2>;
 200                                 cache-unified;
 201                                 next-level-cache = <&L3_0>;
 202                         };
 203                 };
 204
 205                 CPU5: cpu@500 {
 206                         device_type = "cpu";
 207                         compatible = "qcom,kryo468";
 208                         reg = <0x0 0x500>;
 209                         clocks = <&cpufreq_hw 0>;
 210                         enable-method = "psci";
 211                         power-domains = <&CPU_PD5>;
 212                         power-domain-names = "psci";
 213                         capacity-dmips-mhz = <415>;
 214                         dynamic-power-coefficient = <137>;
 215                         next-level-cache = <&L2_500>;
 216                         operating-points-v2 = <&cpu0_opp_table>;
 217                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 218                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 219                         #cooling-cells = <2>;
 220                         qcom,freq-domain = <&cpufreq_hw 0>;
 221                         L2_500: l2-cache {
 222                                 compatible = "cache";
 223                                 cache-level = <2>;
 224                                 cache-unified;
 225                                 next-level-cache = <&L3_0>;
 226                         };
 227                 };
 228
 229                 CPU6: cpu@600 {
 230                         device_type = "cpu";
 231                         compatible = "qcom,kryo468";
 232                         reg = <0x0 0x600>;
 233                         clocks = <&cpufreq_hw 1>;
 234                         enable-method = "psci";
 235                         power-domains = <&CPU_PD6>;
 236                         power-domain-names = "psci";
 237                         capacity-dmips-mhz = <1024>;
 238                         dynamic-power-coefficient = <480>;
 239                         next-level-cache = <&L2_600>;
 240                         operating-points-v2 = <&cpu6_opp_table>;
 241                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 242                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 243                         #cooling-cells = <2>;
 244                         qcom,freq-domain = <&cpufreq_hw 1>;
 245                         L2_600: l2-cache {
 246                                 compatible = "cache";
 247                                 cache-level = <2>;
 248                                 cache-unified;
 249                                 next-level-cache = <&L3_0>;
 250                         };
 251                 };
 252
 253                 CPU7: cpu@700 {
 254                         device_type = "cpu";
 255                         compatible = "qcom,kryo468";
 256                         reg = <0x0 0x700>;
 257                         clocks = <&cpufreq_hw 1>;
 258                         enable-method = "psci";
 259                         power-domains = <&CPU_PD7>;
 260                         power-domain-names = "psci";
 261                         capacity-dmips-mhz = <1024>;
 262                         dynamic-power-coefficient = <480>;
 263                         next-level-cache = <&L2_700>;
 264                         operating-points-v2 = <&cpu6_opp_table>;
 265                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 266                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 267                         #cooling-cells = <2>;
 268                         qcom,freq-domain = <&cpufreq_hw 1>;
 269                         L2_700: l2-cache {
 270                                 compatible = "cache";
 271                                 cache-level = <2>;
 272                                 cache-unified;
 273                                 next-level-cache = <&L3_0>;
 274                         };
 275                 };
 276
 277                 cpu-map {
 278                         cluster0 {
 279                                 core0 {
 280                                         cpu = <&CPU0>;
 281                                 };
 282
 283                                 core1 {
 284                                         cpu = <&CPU1>;
 285                                 };
 286
 287                                 core2 {
 288                                         cpu = <&CPU2>;
 289                                 };
 290
 291                                 core3 {
 292                                         cpu = <&CPU3>;
 293                                 };
 294
 295                                 core4 {
 296                                         cpu = <&CPU4>;
 297                                 };
 298
 299                                 core5 {
 300                                         cpu = <&CPU5>;
 301                                 };
 302
 303                                 core6 {
 304                                         cpu = <&CPU6>;
 305                                 };
 306
 307                                 core7 {
 308                                         cpu = <&CPU7>;
 309                                 };
 310                         };
 311                 };
 312
 313                 idle_states: idle-states {
 314                         entry-method = "psci";
 315
 316                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 317                                 compatible = "arm,idle-state";
 318                                 idle-state-name = "little-power-down";
 319                                 arm,psci-suspend-param = <0x40000003>;
 320                                 entry-latency-us = <549>;
 321                                 exit-latency-us = <901>;
 322                                 min-residency-us = <1774>;
 323                                 local-timer-stop;
 324                         };
 325
 326                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 327                                 compatible = "arm,idle-state";
 328                                 idle-state-name = "little-rail-power-down";
 329                                 arm,psci-suspend-param = <0x40000004>;
 330                                 entry-latency-us = <702>;
 331                                 exit-latency-us = <915>;
 332                                 min-residency-us = <4001>;
 333                                 local-timer-stop;
 334                         };
 335
 336                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 337                                 compatible = "arm,idle-state";
 338                                 idle-state-name = "big-power-down";
 339                                 arm,psci-suspend-param = <0x40000003>;
 340                                 entry-latency-us = <523>;
 341                                 exit-latency-us = <1244>;
 342                                 min-residency-us = <2207>;
 343                                 local-timer-stop;
 344                         };
 345
 346                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 347                                 compatible = "arm,idle-state";
 348                                 idle-state-name = "big-rail-power-down";
 349                                 arm,psci-suspend-param = <0x40000004>;
 350                                 entry-latency-us = <526>;
 351                                 exit-latency-us = <1854>;
 352                                 min-residency-us = <5555>;
 353                                 local-timer-stop;
 354                         };
 355                 };
 356
 357                 domain_idle_states: domain-idle-states {
 358                         CLUSTER_SLEEP_PC: cluster-sleep-0 {
 359                                 compatible = "domain-idle-state";
 360                                 idle-state-name = "cluster-l3-power-collapse";
 361                                 arm,psci-suspend-param = <0x41000044>;
 362                                 entry-latency-us = <2752>;
 363                                 exit-latency-us = <3048>;
 364                                 min-residency-us = <6118>;
 365                         };
 366
 367                         CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
 368                                 compatible = "domain-idle-state";
 369                                 idle-state-name = "cluster-cx-retention";
 370                                 arm,psci-suspend-param = <0x41001244>;
 371                                 entry-latency-us = <3638>;
 372                                 exit-latency-us = <4562>;
 373                                 min-residency-us = <8467>;
 374                         };
 375
 376                         CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
 377                                 compatible = "domain-idle-state";
 378                                 idle-state-name = "cluster-power-down";
 379                                 arm,psci-suspend-param = <0x4100b244>;
 380                                 entry-latency-us = <3263>;
 381                                 exit-latency-us = <6562>;
 382                                 min-residency-us = <9826>;
 383                         };
 384                 };
 385         };
 386
 387         firmware {
 388                 scm: scm {
 389                         compatible = "qcom,scm-sc7180", "qcom,scm";
 390                 };
 391         };
 392
 393         memory@80000000 {
 394                 device_type = "memory";
 395                 /* We expect the bootloader to fill in the size */
 396                 reg = <0 0x80000000 0 0>;
 397         };
 398
 399         cpu0_opp_table: opp-table-cpu0 {
 400                 compatible = "operating-points-v2";
 401                 opp-shared;
 402
 403                 cpu0_opp1: opp-300000000 {
 404                         opp-hz = /bits/ 64 <300000000>;
 405                         opp-peak-kBps = <1200000 4800000>;
 406                 };
 407
 408                 cpu0_opp2: opp-576000000 {
 409                         opp-hz = /bits/ 64 <576000000>;
 410                         opp-peak-kBps = <1200000 4800000>;
 411                 };
 412
 413                 cpu0_opp3: opp-768000000 {
 414                         opp-hz = /bits/ 64 <768000000>;
 415                         opp-peak-kBps = <1200000 4800000>;
 416                 };
 417
 418                 cpu0_opp4: opp-1017600000 {
 419                         opp-hz = /bits/ 64 <1017600000>;
 420                         opp-peak-kBps = <1804000 8908800>;
 421                 };
 422
 423                 cpu0_opp5: opp-1248000000 {
 424                         opp-hz = /bits/ 64 <1248000000>;
 425                         opp-peak-kBps = <2188000 12902400>;
 426                 };
 427
 428                 cpu0_opp6: opp-1324800000 {
 429                         opp-hz = /bits/ 64 <1324800000>;
 430                         opp-peak-kBps = <2188000 12902400>;
 431                 };
 432
 433                 cpu0_opp7: opp-1516800000 {
 434                         opp-hz = /bits/ 64 <1516800000>;
 435                         opp-peak-kBps = <3072000 15052800>;
 436                 };
 437
 438                 cpu0_opp8: opp-1612800000 {
 439                         opp-hz = /bits/ 64 <1612800000>;
 440                         opp-peak-kBps = <3072000 15052800>;
 441                 };
 442
 443                 cpu0_opp9: opp-1708800000 {
 444                         opp-hz = /bits/ 64 <1708800000>;
 445                         opp-peak-kBps = <3072000 15052800>;
 446                 };
 447
 448                 cpu0_opp10: opp-1804800000 {
 449                         opp-hz = /bits/ 64 <1804800000>;
 450                         opp-peak-kBps = <4068000 22425600>;
 451                 };
 452         };
 453
 454         cpu6_opp_table: opp-table-cpu6 {
 455                 compatible = "operating-points-v2";
 456                 opp-shared;
 457
 458                 cpu6_opp1: opp-300000000 {
 459                         opp-hz = /bits/ 64 <300000000>;
 460                         opp-peak-kBps = <2188000 8908800>;
 461                 };
 462
 463                 cpu6_opp2: opp-652800000 {
 464                         opp-hz = /bits/ 64 <652800000>;
 465                         opp-peak-kBps = <2188000 8908800>;
 466                 };
 467
 468                 cpu6_opp3: opp-825600000 {
 469                         opp-hz = /bits/ 64 <825600000>;
 470                         opp-peak-kBps = <2188000 8908800>;
 471                 };
 472
 473                 cpu6_opp4: opp-979200000 {
 474                         opp-hz = /bits/ 64 <979200000>;
 475                         opp-peak-kBps = <2188000 8908800>;
 476                 };
 477
 478                 cpu6_opp5: opp-1113600000 {
 479                         opp-hz = /bits/ 64 <1113600000>;
 480                         opp-peak-kBps = <2188000 8908800>;
 481                 };
 482
 483                 cpu6_opp6: opp-1267200000 {
 484                         opp-hz = /bits/ 64 <1267200000>;
 485                         opp-peak-kBps = <4068000 12902400>;
 486                 };
 487
 488                 cpu6_opp7: opp-1555200000 {
 489                         opp-hz = /bits/ 64 <1555200000>;
 490                         opp-peak-kBps = <4068000 15052800>;
 491                 };
 492
 493                 cpu6_opp8: opp-1708800000 {
 494                         opp-hz = /bits/ 64 <1708800000>;
 495                         opp-peak-kBps = <6220000 19353600>;
 496                 };
 497
 498                 cpu6_opp9: opp-1843200000 {
 499                         opp-hz = /bits/ 64 <1843200000>;
 500                         opp-peak-kBps = <6220000 19353600>;
 501                 };
 502
 503                 cpu6_opp10: opp-1900800000 {
 504                         opp-hz = /bits/ 64 <1900800000>;
 505                         opp-peak-kBps = <6220000 22425600>;
 506                 };
 507
 508                 cpu6_opp11: opp-1996800000 {
 509                         opp-hz = /bits/ 64 <1996800000>;
 510                         opp-peak-kBps = <6220000 22425600>;
 511                 };
 512
 513                 cpu6_opp12: opp-2112000000 {
 514                         opp-hz = /bits/ 64 <2112000000>;
 515                         opp-peak-kBps = <6220000 22425600>;
 516                 };
 517
 518                 cpu6_opp13: opp-2208000000 {
 519                         opp-hz = /bits/ 64 <2208000000>;
 520                         opp-peak-kBps = <7216000 22425600>;
 521                 };
 522
 523                 cpu6_opp14: opp-2323200000 {
 524                         opp-hz = /bits/ 64 <2323200000>;
 525                         opp-peak-kBps = <7216000 22425600>;
 526                 };
 527
 528                 cpu6_opp15: opp-2400000000 {
 529                         opp-hz = /bits/ 64 <2400000000>;
 530                         opp-peak-kBps = <8532000 23347200>;
 531                 };
 532
 533                 cpu6_opp16: opp-2553600000 {
 534                         opp-hz = /bits/ 64 <2553600000>;
 535                         opp-peak-kBps = <8532000 23347200>;
 536                 };
 537         };
 538
 539         qspi_opp_table: opp-table-qspi {
 540                 compatible = "operating-points-v2";
 541
 542                 opp-75000000 {
 543                         opp-hz = /bits/ 64 <75000000>;
 544                         required-opps = <&rpmhpd_opp_low_svs>;
 545                 };
 546
 547                 opp-150000000 {
 548                         opp-hz = /bits/ 64 <150000000>;
 549                         required-opps = <&rpmhpd_opp_svs>;
 550                 };
 551
 552                 opp-300000000 {
 553                         opp-hz = /bits/ 64 <300000000>;
 554                         required-opps = <&rpmhpd_opp_nom>;
 555                 };
 556         };
 557
 558         qup_opp_table: opp-table-qup {
 559                 compatible = "operating-points-v2";
 560
 561                 opp-75000000 {
 562                         opp-hz = /bits/ 64 <75000000>;
 563                         required-opps = <&rpmhpd_opp_low_svs>;
 564                 };
 565
 566                 opp-100000000 {
 567                         opp-hz = /bits/ 64 <100000000>;
 568                         required-opps = <&rpmhpd_opp_svs>;
 569                 };
 570
 571                 opp-128000000 {
 572                         opp-hz = /bits/ 64 <128000000>;
 573                         required-opps = <&rpmhpd_opp_nom>;
 574                 };
 575         };
 576
 577         pmu {
 578                 compatible = "arm,armv8-pmuv3";
 579                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 580         };
 581
 582         psci {
 583                 compatible = "arm,psci-1.0";
 584                 method = "smc";
 585
 586                 CPU_PD0: cpu0 {
 587                         #power-domain-cells = <0>;
 588                         power-domains = <&CLUSTER_PD>;
 589                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 590                 };
 591
 592                 CPU_PD1: cpu1 {
 593                         #power-domain-cells = <0>;
 594                         power-domains = <&CLUSTER_PD>;
 595                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 596                 };
 597
 598                 CPU_PD2: cpu2 {
 599                         #power-domain-cells = <0>;
 600                         power-domains = <&CLUSTER_PD>;
 601                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 602                 };
 603
 604                 CPU_PD3: cpu3 {
 605                         #power-domain-cells = <0>;
 606                         power-domains = <&CLUSTER_PD>;
 607                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 608                 };
 609
 610                 CPU_PD4: cpu4 {
 611                         #power-domain-cells = <0>;
 612                         power-domains = <&CLUSTER_PD>;
 613                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 614                 };
 615
 616                 CPU_PD5: cpu5 {
 617                         #power-domain-cells = <0>;
 618                         power-domains = <&CLUSTER_PD>;
 619                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 620                 };
 621
 622                 CPU_PD6: cpu6 {
 623                         #power-domain-cells = <0>;
 624                         power-domains = <&CLUSTER_PD>;
 625                         domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 626                 };
 627
 628                 CPU_PD7: cpu7 {
 629                         #power-domain-cells = <0>;
 630                         power-domains = <&CLUSTER_PD>;
 631                         domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 632                 };
 633
 634                 CLUSTER_PD: cpu-cluster0 {
 635                         #power-domain-cells = <0>;
 636                         domain-idle-states = <&CLUSTER_SLEEP_PC
 637                                               &CLUSTER_SLEEP_CX_RET
 638                                               &CLUSTER_AOSS_SLEEP>;
 639                 };
 640         };
 641
 642         reserved_memory: reserved-memory {
 643                 #address-cells = <2>;
 644                 #size-cells = <2>;
 645                 ranges;
 646
 647                 hyp_mem: memory@80000000 {
 648                         reg = <0x0 0x80000000 0x0 0x600000>;
 649                         no-map;
 650                 };
 651
 652                 xbl_mem: memory@80600000 {
 653                         reg = <0x0 0x80600000 0x0 0x200000>;
 654                         no-map;
 655                 };
 656
 657                 aop_mem: memory@80800000 {
 658                         reg = <0x0 0x80800000 0x0 0x20000>;
 659                         no-map;
 660                 };
 661
 662                 aop_cmd_db_mem: memory@80820000 {
 663                         reg = <0x0 0x80820000 0x0 0x20000>;
 664                         compatible = "qcom,cmd-db";
 665                         no-map;
 666                 };
 667
 668                 sec_apps_mem: memory@808ff000 {
 669                         reg = <0x0 0x808ff000 0x0 0x1000>;
 670                         no-map;
 671                 };
 672
 673                 smem_mem: memory@80900000 {
 674                         reg = <0x0 0x80900000 0x0 0x200000>;
 675                         no-map;
 676                 };
 677
 678                 tz_mem: memory@80b00000 {
 679                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 680                         no-map;
 681                 };
 682
 683                 ipa_fw_mem: memory@8b700000 {
 684                         reg = <0 0x8b700000 0 0x10000>;
 685                         no-map;
 686                 };
 687
 688                 rmtfs_mem: memory@94600000 {
 689                         compatible = "qcom,rmtfs-mem";
 690                         reg = <0x0 0x94600000 0x0 0x200000>;
 691                         no-map;
 692
 693                         qcom,client-id = <1>;
 694                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 695                 };
 696         };
 697
 698         smem {
 699                 compatible = "qcom,smem";
 700                 memory-region = <&smem_mem>;
 701                 hwlocks = <&tcsr_mutex 3>;
 702         };
 703
 704         smp2p-cdsp {
 705                 compatible = "qcom,smp2p";
 706                 qcom,smem = <94>, <432>;
 707
 708                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 709
 710                 mboxes = <&apss_shared 6>;
 711
 712                 qcom,local-pid = <0>;
 713                 qcom,remote-pid = <5>;
 714
 715                 cdsp_smp2p_out: master-kernel {
 716                         qcom,entry-name = "master-kernel";
 717                         #qcom,smem-state-cells = <1>;
 718                 };
 719
 720                 cdsp_smp2p_in: slave-kernel {
 721                         qcom,entry-name = "slave-kernel";
 722
 723                         interrupt-controller;
 724                         #interrupt-cells = <2>;
 725                 };
 726         };
 727
 728         smp2p-lpass {
 729                 compatible = "qcom,smp2p";
 730                 qcom,smem = <443>, <429>;
 731
 732                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 733
 734                 mboxes = <&apss_shared 10>;
 735
 736                 qcom,local-pid = <0>;
 737                 qcom,remote-pid = <2>;
 738
 739                 adsp_smp2p_out: master-kernel {
 740                         qcom,entry-name = "master-kernel";
 741                         #qcom,smem-state-cells = <1>;
 742                 };
 743
 744                 adsp_smp2p_in: slave-kernel {
 745                         qcom,entry-name = "slave-kernel";
 746
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750         };
 751
 752         smp2p-mpss {
 753                 compatible = "qcom,smp2p";
 754                 qcom,smem = <435>, <428>;
 755                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 756                 mboxes = <&apss_shared 14>;
 757                 qcom,local-pid = <0>;
 758                 qcom,remote-pid = <1>;
 759
 760                 modem_smp2p_out: master-kernel {
 761                         qcom,entry-name = "master-kernel";
 762                         #qcom,smem-state-cells = <1>;
 763                 };
 764
 765                 modem_smp2p_in: slave-kernel {
 766                         qcom,entry-name = "slave-kernel";
 767                         interrupt-controller;
 768                         #interrupt-cells = <2>;
 769                 };
 770
 771                 ipa_smp2p_out: ipa-ap-to-modem {
 772                         qcom,entry-name = "ipa";
 773                         #qcom,smem-state-cells = <1>;
 774                 };
 775
 776                 ipa_smp2p_in: ipa-modem-to-ap {
 777                         qcom,entry-name = "ipa";
 778                         interrupt-controller;
 779                         #interrupt-cells = <2>;
 780                 };
 781         };
 782
 783         soc: soc@0 {
 784                 #address-cells = <2>;
 785                 #size-cells = <2>;
 786                 ranges = <0 0 0 0 0x10 0>;
 787                 dma-ranges = <0 0 0 0 0x10 0>;
 788                 compatible = "simple-bus";
 789
 790                 gcc: clock-controller@100000 {
 791                         compatible = "qcom,gcc-sc7180";
 792                         reg = <0 0x00100000 0 0x1f0000>;
 793                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 794                                  <&rpmhcc RPMH_CXO_CLK_A>,
 795                                  <&sleep_clk>;
 796                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 797                         #clock-cells = <1>;
 798                         #reset-cells = <1>;
 799                         #power-domain-cells = <1>;
 800                         power-domains = <&rpmhpd SC7180_CX>;
 801                 };
 802
 803                 qfprom: efuse@784000 {
 804                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 805                         reg = <0 0x00784000 0 0x7a0>,
 806                               <0 0x00780000 0 0x7a0>,
 807                               <0 0x00782000 0 0x100>,
 808                               <0 0x00786000 0 0x1fff>;
 809
 810                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 811                         clock-names = "core";
 812                         #address-cells = <1>;
 813                         #size-cells = <1>;
 814
 815                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 816                                 reg = <0x25b 0x1>;
 817                                 bits = <1 3>;
 818                         };
 819
 820                         gpu_speed_bin: gpu-speed-bin@1d2 {
 821                                 reg = <0x1d2 0x2>;
 822                                 bits = <5 8>;
 823                         };
 824                 };
 825
 826                 sdhc_1: mmc@7c4000 {
 827                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 828                         reg = <0 0x007c4000 0 0x1000>,
 829                                 <0 0x007c5000 0 0x1000>;
 830                         reg-names = "hc", "cqhci";
 831
 832                         iommus = <&apps_smmu 0x60 0x0>;
 833                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 834                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 835                         interrupt-names = "hc_irq", "pwr_irq";
 836
 837                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 838                                  <&gcc GCC_SDCC1_APPS_CLK>,
 839                                  <&rpmhcc RPMH_CXO_CLK>;
 840                         clock-names = "iface", "core", "xo";
 841                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 842                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 843                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 844                         power-domains = <&rpmhpd SC7180_CX>;
 845                         operating-points-v2 = <&sdhc1_opp_table>;
 846
 847                         bus-width = <8>;
 848                         non-removable;
 849                         supports-cqe;
 850
 851                         mmc-ddr-1_8v;
 852                         mmc-hs200-1_8v;
 853                         mmc-hs400-1_8v;
 854                         mmc-hs400-enhanced-strobe;
 855
 856                         status = "disabled";
 857
 858                         sdhc1_opp_table: opp-table {
 859                                 compatible = "operating-points-v2";
 860
 861                                 opp-100000000 {
 862                                         opp-hz = /bits/ 64 <100000000>;
 863                                         required-opps = <&rpmhpd_opp_low_svs>;
 864                                         opp-peak-kBps = <1800000 600000>;
 865                                         opp-avg-kBps = <100000 0>;
 866                                 };
 867
 868                                 opp-384000000 {
 869                                         opp-hz = /bits/ 64 <384000000>;
 870                                         required-opps = <&rpmhpd_opp_nom>;
 871                                         opp-peak-kBps = <5400000 1600000>;
 872                                         opp-avg-kBps = <390000 0>;
 873                                 };
 874                         };
 875                 };
 876
 877                 qupv3_id_0: geniqup@8c0000 {
 878                         compatible = "qcom,geni-se-qup";
 879                         reg = <0 0x008c0000 0 0x6000>;
 880                         clock-names = "m-ahb", "s-ahb";
 881                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 882                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 883                         #address-cells = <2>;
 884                         #size-cells = <2>;
 885                         ranges;
 886                         iommus = <&apps_smmu 0x43 0x0>;
 887                         status = "disabled";
 888
 889                         i2c0: i2c@880000 {
 890                                 compatible = "qcom,geni-i2c";
 891                                 reg = <0 0x00880000 0 0x4000>;
 892                                 clock-names = "se";
 893                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 894                                 pinctrl-names = "default";
 895                                 pinctrl-0 = <&qup_i2c0_default>;
 896                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 897                                 #address-cells = <1>;
 898                                 #size-cells = <0>;
 899                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 900                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 901                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 902                                 interconnect-names = "qup-core", "qup-config",
 903                                                         "qup-memory";
 904                                 power-domains = <&rpmhpd SC7180_CX>;
 905                                 required-opps = <&rpmhpd_opp_low_svs>;
 906                                 status = "disabled";
 907                         };
 908
 909                         spi0: spi@880000 {
 910                                 compatible = "qcom,geni-spi";
 911                                 reg = <0 0x00880000 0 0x4000>;
 912                                 clock-names = "se";
 913                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 914                                 pinctrl-names = "default";
 915                                 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
 916                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919                                 power-domains = <&rpmhpd SC7180_CX>;
 920                                 operating-points-v2 = <&qup_opp_table>;
 921                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 922                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 923                                 interconnect-names = "qup-core", "qup-config";
 924                                 status = "disabled";
 925                         };
 926
 927                         uart0: serial@880000 {
 928                                 compatible = "qcom,geni-uart";
 929                                 reg = <0 0x00880000 0 0x4000>;
 930                                 clock-names = "se";
 931                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 932                                 pinctrl-names = "default";
 933                                 pinctrl-0 = <&qup_uart0_default>;
 934                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 935                                 power-domains = <&rpmhpd SC7180_CX>;
 936                                 operating-points-v2 = <&qup_opp_table>;
 937                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 938                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 939                                 interconnect-names = "qup-core", "qup-config";
 940                                 status = "disabled";
 941                         };
 942
 943                         i2c1: i2c@884000 {
 944                                 compatible = "qcom,geni-i2c";
 945                                 reg = <0 0x00884000 0 0x4000>;
 946                                 clock-names = "se";
 947                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 948                                 pinctrl-names = "default";
 949                                 pinctrl-0 = <&qup_i2c1_default>;
 950                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 954                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 955                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 956                                 interconnect-names = "qup-core", "qup-config",
 957                                                         "qup-memory";
 958                                 power-domains = <&rpmhpd SC7180_CX>;
 959                                 required-opps = <&rpmhpd_opp_low_svs>;
 960                                 status = "disabled";
 961                         };
 962
 963                         spi1: spi@884000 {
 964                                 compatible = "qcom,geni-spi";
 965                                 reg = <0 0x00884000 0 0x4000>;
 966                                 clock-names = "se";
 967                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 968                                 pinctrl-names = "default";
 969                                 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
 970                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 power-domains = <&rpmhpd SC7180_CX>;
 974                                 operating-points-v2 = <&qup_opp_table>;
 975                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 976                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 977                                 interconnect-names = "qup-core", "qup-config";
 978                                 status = "disabled";
 979                         };
 980
 981                         uart1: serial@884000 {
 982                                 compatible = "qcom,geni-uart";
 983                                 reg = <0 0x00884000 0 0x4000>;
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 986                                 pinctrl-names = "default";
 987                                 pinctrl-0 = <&qup_uart1_default>;
 988                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 989                                 power-domains = <&rpmhpd SC7180_CX>;
 990                                 operating-points-v2 = <&qup_opp_table>;
 991                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 992                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 993                                 interconnect-names = "qup-core", "qup-config";
 994                                 status = "disabled";
 995                         };
 996
 997                         i2c2: i2c@888000 {
 998                                 compatible = "qcom,geni-i2c";
 999                                 reg = <0 0x00888000 0 0x4000>;
1000                                 clock-names = "se";
1001                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002                                 pinctrl-names = "default";
1003                                 pinctrl-0 = <&qup_i2c2_default>;
1004                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005                                 #address-cells = <1>;
1006                                 #size-cells = <0>;
1007                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010                                 interconnect-names = "qup-core", "qup-config",
1011                                                         "qup-memory";
1012                                 power-domains = <&rpmhpd SC7180_CX>;
1013                                 required-opps = <&rpmhpd_opp_low_svs>;
1014                                 status = "disabled";
1015                         };
1016
1017                         uart2: serial@888000 {
1018                                 compatible = "qcom,geni-uart";
1019                                 reg = <0 0x00888000 0 0x4000>;
1020                                 clock-names = "se";
1021                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022                                 pinctrl-names = "default";
1023                                 pinctrl-0 = <&qup_uart2_default>;
1024                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025                                 power-domains = <&rpmhpd SC7180_CX>;
1026                                 operating-points-v2 = <&qup_opp_table>;
1027                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029                                 interconnect-names = "qup-core", "qup-config";
1030                                 status = "disabled";
1031                         };
1032
1033                         i2c3: i2c@88c000 {
1034                                 compatible = "qcom,geni-i2c";
1035                                 reg = <0 0x0088c000 0 0x4000>;
1036                                 clock-names = "se";
1037                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038                                 pinctrl-names = "default";
1039                                 pinctrl-0 = <&qup_i2c3_default>;
1040                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041                                 #address-cells = <1>;
1042                                 #size-cells = <0>;
1043                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046                                 interconnect-names = "qup-core", "qup-config",
1047                                                         "qup-memory";
1048                                 power-domains = <&rpmhpd SC7180_CX>;
1049                                 required-opps = <&rpmhpd_opp_low_svs>;
1050                                 status = "disabled";
1051                         };
1052
1053                         spi3: spi@88c000 {
1054                                 compatible = "qcom,geni-spi";
1055                                 reg = <0 0x0088c000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058                                 pinctrl-names = "default";
1059                                 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063                                 power-domains = <&rpmhpd SC7180_CX>;
1064                                 operating-points-v2 = <&qup_opp_table>;
1065                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067                                 interconnect-names = "qup-core", "qup-config";
1068                                 status = "disabled";
1069                         };
1070
1071                         uart3: serial@88c000 {
1072                                 compatible = "qcom,geni-uart";
1073                                 reg = <0 0x0088c000 0 0x4000>;
1074                                 clock-names = "se";
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076                                 pinctrl-names = "default";
1077                                 pinctrl-0 = <&qup_uart3_default>;
1078                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079                                 power-domains = <&rpmhpd SC7180_CX>;
1080                                 operating-points-v2 = <&qup_opp_table>;
1081                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083                                 interconnect-names = "qup-core", "qup-config";
1084                                 status = "disabled";
1085                         };
1086
1087                         i2c4: i2c@890000 {
1088                                 compatible = "qcom,geni-i2c";
1089                                 reg = <0 0x00890000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092                                 pinctrl-names = "default";
1093                                 pinctrl-0 = <&qup_i2c4_default>;
1094                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100                                 interconnect-names = "qup-core", "qup-config",
1101                                                         "qup-memory";
1102                                 power-domains = <&rpmhpd SC7180_CX>;
1103                                 required-opps = <&rpmhpd_opp_low_svs>;
1104                                 status = "disabled";
1105                         };
1106
1107                         uart4: serial@890000 {
1108                                 compatible = "qcom,geni-uart";
1109                                 reg = <0 0x00890000 0 0x4000>;
1110                                 clock-names = "se";
1111                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112                                 pinctrl-names = "default";
1113                                 pinctrl-0 = <&qup_uart4_default>;
1114                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115                                 power-domains = <&rpmhpd SC7180_CX>;
1116                                 operating-points-v2 = <&qup_opp_table>;
1117                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119                                 interconnect-names = "qup-core", "qup-config";
1120                                 status = "disabled";
1121                         };
1122
1123                         i2c5: i2c@894000 {
1124                                 compatible = "qcom,geni-i2c";
1125                                 reg = <0 0x00894000 0 0x4000>;
1126                                 clock-names = "se";
1127                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128                                 pinctrl-names = "default";
1129                                 pinctrl-0 = <&qup_i2c5_default>;
1130                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131                                 #address-cells = <1>;
1132                                 #size-cells = <0>;
1133                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136                                 interconnect-names = "qup-core", "qup-config",
1137                                                         "qup-memory";
1138                                 power-domains = <&rpmhpd SC7180_CX>;
1139                                 required-opps = <&rpmhpd_opp_low_svs>;
1140                                 status = "disabled";
1141                         };
1142
1143                         spi5: spi@894000 {
1144                                 compatible = "qcom,geni-spi";
1145                                 reg = <0 0x00894000 0 0x4000>;
1146                                 clock-names = "se";
1147                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148                                 pinctrl-names = "default";
1149                                 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151                                 #address-cells = <1>;
1152                                 #size-cells = <0>;
1153                                 power-domains = <&rpmhpd SC7180_CX>;
1154                                 operating-points-v2 = <&qup_opp_table>;
1155                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157                                 interconnect-names = "qup-core", "qup-config";
1158                                 status = "disabled";
1159                         };
1160
1161                         uart5: serial@894000 {
1162                                 compatible = "qcom,geni-uart";
1163                                 reg = <0 0x00894000 0 0x4000>;
1164                                 clock-names = "se";
1165                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166                                 pinctrl-names = "default";
1167                                 pinctrl-0 = <&qup_uart5_default>;
1168                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169                                 power-domains = <&rpmhpd SC7180_CX>;
1170                                 operating-points-v2 = <&qup_opp_table>;
1171                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173                                 interconnect-names = "qup-core", "qup-config";
1174                                 status = "disabled";
1175                         };
1176                 };
1177
1178                 qupv3_id_1: geniqup@ac0000 {
1179                         compatible = "qcom,geni-se-qup";
1180                         reg = <0 0x00ac0000 0 0x6000>;
1181                         clock-names = "m-ahb", "s-ahb";
1182                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184                         #address-cells = <2>;
1185                         #size-cells = <2>;
1186                         ranges;
1187                         iommus = <&apps_smmu 0x4c3 0x0>;
1188                         status = "disabled";
1189
1190                         i2c6: i2c@a80000 {
1191                                 compatible = "qcom,geni-i2c";
1192                                 reg = <0 0x00a80000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&qup_i2c6_default>;
1197                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203                                 interconnect-names = "qup-core", "qup-config",
1204                                                         "qup-memory";
1205                                 power-domains = <&rpmhpd SC7180_CX>;
1206                                 required-opps = <&rpmhpd_opp_low_svs>;
1207                                 status = "disabled";
1208                         };
1209
1210                         spi6: spi@a80000 {
1211                                 compatible = "qcom,geni-spi";
1212                                 reg = <0 0x00a80000 0 0x4000>;
1213                                 clock-names = "se";
1214                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215                                 pinctrl-names = "default";
1216                                 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 power-domains = <&rpmhpd SC7180_CX>;
1221                                 operating-points-v2 = <&qup_opp_table>;
1222                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224                                 interconnect-names = "qup-core", "qup-config";
1225                                 status = "disabled";
1226                         };
1227
1228                         uart6: serial@a80000 {
1229                                 compatible = "qcom,geni-uart";
1230                                 reg = <0 0x00a80000 0 0x4000>;
1231                                 clock-names = "se";
1232                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233                                 pinctrl-names = "default";
1234                                 pinctrl-0 = <&qup_uart6_default>;
1235                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236                                 power-domains = <&rpmhpd SC7180_CX>;
1237                                 operating-points-v2 = <&qup_opp_table>;
1238                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240                                 interconnect-names = "qup-core", "qup-config";
1241                                 status = "disabled";
1242                         };
1243
1244                         i2c7: i2c@a84000 {
1245                                 compatible = "qcom,geni-i2c";
1246                                 reg = <0 0x00a84000 0 0x4000>;
1247                                 clock-names = "se";
1248                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&qup_i2c7_default>;
1251                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257                                 interconnect-names = "qup-core", "qup-config",
1258                                                         "qup-memory";
1259                                 power-domains = <&rpmhpd SC7180_CX>;
1260                                 required-opps = <&rpmhpd_opp_low_svs>;
1261                                 status = "disabled";
1262                         };
1263
1264                         uart7: serial@a84000 {
1265                                 compatible = "qcom,geni-uart";
1266                                 reg = <0 0x00a84000 0 0x4000>;
1267                                 clock-names = "se";
1268                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269                                 pinctrl-names = "default";
1270                                 pinctrl-0 = <&qup_uart7_default>;
1271                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272                                 power-domains = <&rpmhpd SC7180_CX>;
1273                                 operating-points-v2 = <&qup_opp_table>;
1274                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276                                 interconnect-names = "qup-core", "qup-config";
1277                                 status = "disabled";
1278                         };
1279
1280                         i2c8: i2c@a88000 {
1281                                 compatible = "qcom,geni-i2c";
1282                                 reg = <0 0x00a88000 0 0x4000>;
1283                                 clock-names = "se";
1284                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285                                 pinctrl-names = "default";
1286                                 pinctrl-0 = <&qup_i2c8_default>;
1287                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288                                 #address-cells = <1>;
1289                                 #size-cells = <0>;
1290                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293                                 interconnect-names = "qup-core", "qup-config",
1294                                                         "qup-memory";
1295                                 power-domains = <&rpmhpd SC7180_CX>;
1296                                 required-opps = <&rpmhpd_opp_low_svs>;
1297                                 status = "disabled";
1298                         };
1299
1300                         spi8: spi@a88000 {
1301                                 compatible = "qcom,geni-spi";
1302                                 reg = <0 0x00a88000 0 0x4000>;
1303                                 clock-names = "se";
1304                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305                                 pinctrl-names = "default";
1306                                 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308                                 #address-cells = <1>;
1309                                 #size-cells = <0>;
1310                                 power-domains = <&rpmhpd SC7180_CX>;
1311                                 operating-points-v2 = <&qup_opp_table>;
1312                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314                                 interconnect-names = "qup-core", "qup-config";
1315                                 status = "disabled";
1316                         };
1317
1318                         uart8: serial@a88000 {
1319                                 compatible = "qcom,geni-debug-uart";
1320                                 reg = <0 0x00a88000 0 0x4000>;
1321                                 clock-names = "se";
1322                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323                                 pinctrl-names = "default";
1324                                 pinctrl-0 = <&qup_uart8_default>;
1325                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326                                 power-domains = <&rpmhpd SC7180_CX>;
1327                                 operating-points-v2 = <&qup_opp_table>;
1328                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330                                 interconnect-names = "qup-core", "qup-config";
1331                                 status = "disabled";
1332                         };
1333
1334                         i2c9: i2c@a8c000 {
1335                                 compatible = "qcom,geni-i2c";
1336                                 reg = <0 0x00a8c000 0 0x4000>;
1337                                 clock-names = "se";
1338                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339                                 pinctrl-names = "default";
1340                                 pinctrl-0 = <&qup_i2c9_default>;
1341                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347                                 interconnect-names = "qup-core", "qup-config",
1348                                                         "qup-memory";
1349                                 power-domains = <&rpmhpd SC7180_CX>;
1350                                 required-opps = <&rpmhpd_opp_low_svs>;
1351                                 status = "disabled";
1352                         };
1353
1354                         uart9: serial@a8c000 {
1355                                 compatible = "qcom,geni-uart";
1356                                 reg = <0 0x00a8c000 0 0x4000>;
1357                                 clock-names = "se";
1358                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359                                 pinctrl-names = "default";
1360                                 pinctrl-0 = <&qup_uart9_default>;
1361                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362                                 power-domains = <&rpmhpd SC7180_CX>;
1363                                 operating-points-v2 = <&qup_opp_table>;
1364                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366                                 interconnect-names = "qup-core", "qup-config";
1367                                 status = "disabled";
1368                         };
1369
1370                         i2c10: i2c@a90000 {
1371                                 compatible = "qcom,geni-i2c";
1372                                 reg = <0 0x00a90000 0 0x4000>;
1373                                 clock-names = "se";
1374                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375                                 pinctrl-names = "default";
1376                                 pinctrl-0 = <&qup_i2c10_default>;
1377                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378                                 #address-cells = <1>;
1379                                 #size-cells = <0>;
1380                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383                                 interconnect-names = "qup-core", "qup-config",
1384                                                         "qup-memory";
1385                                 power-domains = <&rpmhpd SC7180_CX>;
1386                                 required-opps = <&rpmhpd_opp_low_svs>;
1387                                 status = "disabled";
1388                         };
1389
1390                         spi10: spi@a90000 {
1391                                 compatible = "qcom,geni-spi";
1392                                 reg = <0 0x00a90000 0 0x4000>;
1393                                 clock-names = "se";
1394                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395                                 pinctrl-names = "default";
1396                                 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398                                 #address-cells = <1>;
1399                                 #size-cells = <0>;
1400                                 power-domains = <&rpmhpd SC7180_CX>;
1401                                 operating-points-v2 = <&qup_opp_table>;
1402                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404                                 interconnect-names = "qup-core", "qup-config";
1405                                 status = "disabled";
1406                         };
1407
1408                         uart10: serial@a90000 {
1409                                 compatible = "qcom,geni-uart";
1410                                 reg = <0 0x00a90000 0 0x4000>;
1411                                 clock-names = "se";
1412                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413                                 pinctrl-names = "default";
1414                                 pinctrl-0 = <&qup_uart10_default>;
1415                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416                                 power-domains = <&rpmhpd SC7180_CX>;
1417                                 operating-points-v2 = <&qup_opp_table>;
1418                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420                                 interconnect-names = "qup-core", "qup-config";
1421                                 status = "disabled";
1422                         };
1423
1424                         i2c11: i2c@a94000 {
1425                                 compatible = "qcom,geni-i2c";
1426                                 reg = <0 0x00a94000 0 0x4000>;
1427                                 clock-names = "se";
1428                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429                                 pinctrl-names = "default";
1430                                 pinctrl-0 = <&qup_i2c11_default>;
1431                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432                                 #address-cells = <1>;
1433                                 #size-cells = <0>;
1434                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437                                 interconnect-names = "qup-core", "qup-config",
1438                                                         "qup-memory";
1439                                 power-domains = <&rpmhpd SC7180_CX>;
1440                                 required-opps = <&rpmhpd_opp_low_svs>;
1441                                 status = "disabled";
1442                         };
1443
1444                         spi11: spi@a94000 {
1445                                 compatible = "qcom,geni-spi";
1446                                 reg = <0 0x00a94000 0 0x4000>;
1447                                 clock-names = "se";
1448                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449                                 pinctrl-names = "default";
1450                                 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452                                 #address-cells = <1>;
1453                                 #size-cells = <0>;
1454                                 power-domains = <&rpmhpd SC7180_CX>;
1455                                 operating-points-v2 = <&qup_opp_table>;
1456                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458                                 interconnect-names = "qup-core", "qup-config";
1459                                 status = "disabled";
1460                         };
1461
1462                         uart11: serial@a94000 {
1463                                 compatible = "qcom,geni-uart";
1464                                 reg = <0 0x00a94000 0 0x4000>;
1465                                 clock-names = "se";
1466                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467                                 pinctrl-names = "default";
1468                                 pinctrl-0 = <&qup_uart11_default>;
1469                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470                                 power-domains = <&rpmhpd SC7180_CX>;
1471                                 operating-points-v2 = <&qup_opp_table>;
1472                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474                                 interconnect-names = "qup-core", "qup-config";
1475                                 status = "disabled";
1476                         };
1477                 };
1478
1479                 config_noc: interconnect@1500000 {
1480                         compatible = "qcom,sc7180-config-noc";
1481                         reg = <0 0x01500000 0 0x28000>;
1482                         #interconnect-cells = <2>;
1483                         qcom,bcm-voters = <&apps_bcm_voter>;
1484                 };
1485
1486                 system_noc: interconnect@1620000 {
1487                         compatible = "qcom,sc7180-system-noc";
1488                         reg = <0 0x01620000 0 0x17080>;
1489                         #interconnect-cells = <2>;
1490                         qcom,bcm-voters = <&apps_bcm_voter>;
1491                 };
1492
1493                 mc_virt: interconnect@1638000 {
1494                         compatible = "qcom,sc7180-mc-virt";
1495                         reg = <0 0x01638000 0 0x1000>;
1496                         #interconnect-cells = <2>;
1497                         qcom,bcm-voters = <&apps_bcm_voter>;
1498                 };
1499
1500                 qup_virt: interconnect@1650000 {
1501                         compatible = "qcom,sc7180-qup-virt";
1502                         reg = <0 0x01650000 0 0x1000>;
1503                         #interconnect-cells = <2>;
1504                         qcom,bcm-voters = <&apps_bcm_voter>;
1505                 };
1506
1507                 aggre1_noc: interconnect@16e0000 {
1508                         compatible = "qcom,sc7180-aggre1-noc";
1509                         reg = <0 0x016e0000 0 0x15080>;
1510                         #interconnect-cells = <2>;
1511                         qcom,bcm-voters = <&apps_bcm_voter>;
1512                 };
1513
1514                 aggre2_noc: interconnect@1705000 {
1515                         compatible = "qcom,sc7180-aggre2-noc";
1516                         reg = <0 0x01705000 0 0x9000>;
1517                         #interconnect-cells = <2>;
1518                         qcom,bcm-voters = <&apps_bcm_voter>;
1519                 };
1520
1521                 compute_noc: interconnect@170e000 {
1522                         compatible = "qcom,sc7180-compute-noc";
1523                         reg = <0 0x0170e000 0 0x6000>;
1524                         #interconnect-cells = <2>;
1525                         qcom,bcm-voters = <&apps_bcm_voter>;
1526                 };
1527
1528                 mmss_noc: interconnect@1740000 {
1529                         compatible = "qcom,sc7180-mmss-noc";
1530                         reg = <0 0x01740000 0 0x1c100>;
1531                         #interconnect-cells = <2>;
1532                         qcom,bcm-voters = <&apps_bcm_voter>;
1533                 };
1534
1535                 ufs_mem_hc: ufshc@1d84000 {
1536                         compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1537                                      "jedec,ufs-2.0";
1538                         reg = <0 0x01d84000 0 0x3000>;
1539                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1540                         phys = <&ufs_mem_phy>;
1541                         phy-names = "ufsphy";
1542                         lanes-per-direction = <1>;
1543                         #reset-cells = <1>;
1544                         resets = <&gcc GCC_UFS_PHY_BCR>;
1545                         reset-names = "rst";
1546
1547                         power-domains = <&gcc UFS_PHY_GDSC>;
1548
1549                         iommus = <&apps_smmu 0xa0 0x0>;
1550
1551                         clock-names = "core_clk",
1552                                       "bus_aggr_clk",
1553                                       "iface_clk",
1554                                       "core_clk_unipro",
1555                                       "ref_clk",
1556                                       "tx_lane0_sync_clk",
1557                                       "rx_lane0_sync_clk";
1558                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1559                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1560                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1561                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1562                                  <&rpmhcc RPMH_CXO_CLK>,
1563                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1564                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1565                         freq-table-hz = <50000000 200000000>,
1566                                         <0 0>,
1567                                         <0 0>,
1568                                         <37500000 150000000>,
1569                                         <0 0>,
1570                                         <0 0>,
1571                                         <0 0>;
1572
1573                         interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
1574                                          &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1575                                         <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1576                                          &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
1577                         interconnect-names = "ufs-ddr", "cpu-ufs";
1578
1579                         qcom,ice = <&ice>;
1580
1581                         status = "disabled";
1582                 };
1583
1584                 ufs_mem_phy: phy@1d87000 {
1585                         compatible = "qcom,sc7180-qmp-ufs-phy",
1586                                      "qcom,sm7150-qmp-ufs-phy";
1587                         reg = <0 0x01d87000 0 0x1000>;
1588                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1589                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1590                         clock-names = "ref", "ref_aux";
1591                         power-domains = <&gcc UFS_PHY_GDSC>;
1592                         resets = <&ufs_mem_hc 0>;
1593                         reset-names = "ufsphy";
1594                         #phy-cells = <0>;
1595                         status = "disabled";
1596                 };
1597
1598                 ice: crypto@1d90000 {
1599                         compatible = "qcom,sc7180-inline-crypto-engine",
1600                                      "qcom,inline-crypto-engine";
1601                         reg = <0 0x01d90000 0 0x8000>;
1602                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1603                 };
1604
1605                 ipa: ipa@1e40000 {
1606                         compatible = "qcom,sc7180-ipa";
1607
1608                         iommus = <&apps_smmu 0x440 0x0>,
1609                                  <&apps_smmu 0x442 0x0>;
1610                         reg = <0 0x01e40000 0 0x7000>,
1611                               <0 0x01e47000 0 0x2000>,
1612                               <0 0x01e04000 0 0x2c000>;
1613                         reg-names = "ipa-reg",
1614                                     "ipa-shared",
1615                                     "gsi";
1616
1617                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1618                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1619                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1620                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1621                         interrupt-names = "ipa",
1622                                           "gsi",
1623                                           "ipa-clock-query",
1624                                           "ipa-setup-ready";
1625
1626                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1627                         clock-names = "core";
1628
1629                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1630                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1631                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1632                         interconnect-names = "memory",
1633                                              "imem",
1634                                              "config";
1635
1636                         qcom,qmp = <&aoss_qmp>;
1637
1638                         qcom,smem-states = <&ipa_smp2p_out 0>,
1639                                            <&ipa_smp2p_out 1>;
1640                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1641                                                 "ipa-clock-enabled";
1642
1643                         status = "disabled";
1644                 };
1645
1646                 tcsr_mutex: hwlock@1f40000 {
1647                         compatible = "qcom,tcsr-mutex";
1648                         reg = <0 0x01f40000 0 0x20000>;
1649                         #hwlock-cells = <1>;
1650                 };
1651
1652                 tcsr_regs_1: syscon@1f60000 {
1653                         compatible = "qcom,sc7180-tcsr", "syscon";
1654                         reg = <0 0x01f60000 0 0x20000>;
1655                 };
1656
1657                 tcsr_regs_2: syscon@1fc0000 {
1658                         compatible = "qcom,sc7180-tcsr", "syscon";
1659                         reg = <0 0x01fc0000 0 0x40000>;
1660                 };
1661
1662                 tlmm: pinctrl@3500000 {
1663                         compatible = "qcom,sc7180-pinctrl";
1664                         reg = <0 0x03500000 0 0x300000>,
1665                               <0 0x03900000 0 0x300000>,
1666                               <0 0x03d00000 0 0x300000>;
1667                         reg-names = "west", "north", "south";
1668                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1669                         gpio-controller;
1670                         #gpio-cells = <2>;
1671                         interrupt-controller;
1672                         #interrupt-cells = <2>;
1673                         gpio-ranges = <&tlmm 0 0 120>;
1674                         wakeup-parent = <&pdc>;
1675
1676                         dp_hot_plug_det: dp-hot-plug-det-state {
1677                                 pins = "gpio117";
1678                                 function = "dp_hot";
1679                         };
1680
1681                         qspi_clk: qspi-clk-state {
1682                                 pins = "gpio63";
1683                                 function = "qspi_clk";
1684                         };
1685
1686                         qspi_cs0: qspi-cs0-state {
1687                                 pins = "gpio68";
1688                                 function = "qspi_cs";
1689                         };
1690
1691                         qspi_cs1: qspi-cs1-state {
1692                                 pins = "gpio72";
1693                                 function = "qspi_cs";
1694                         };
1695
1696                         qspi_data0: qspi-data0-state {
1697                                 pins = "gpio64";
1698                                 function = "qspi_data";
1699                         };
1700
1701                         qspi_data1: qspi-data1-state {
1702                                 pins = "gpio65";
1703                                 function = "qspi_data";
1704                         };
1705
1706                         qspi_data23: qspi-data23-state {
1707                                 pins = "gpio66", "gpio67";
1708                                 function = "qspi_data";
1709                         };
1710
1711                         qup_i2c0_default: qup-i2c0-default-state {
1712                                 pins = "gpio34", "gpio35";
1713                                 function = "qup00";
1714                         };
1715
1716                         qup_i2c1_default: qup-i2c1-default-state {
1717                                 pins = "gpio0", "gpio1";
1718                                 function = "qup01";
1719                         };
1720
1721                         qup_i2c2_default: qup-i2c2-default-state {
1722                                 pins = "gpio15", "gpio16";
1723                                 function = "qup02_i2c";
1724                         };
1725
1726                         qup_i2c3_default: qup-i2c3-default-state {
1727                                 pins = "gpio38", "gpio39";
1728                                 function = "qup03";
1729                         };
1730
1731                         qup_i2c4_default: qup-i2c4-default-state {
1732                                 pins = "gpio115", "gpio116";
1733                                 function = "qup04_i2c";
1734                         };
1735
1736                         qup_i2c5_default: qup-i2c5-default-state {
1737                                 pins = "gpio25", "gpio26";
1738                                 function = "qup05";
1739                         };
1740
1741                         qup_i2c6_default: qup-i2c6-default-state {
1742                                 pins = "gpio59", "gpio60";
1743                                 function = "qup10";
1744                         };
1745
1746                         qup_i2c7_default: qup-i2c7-default-state {
1747                                 pins = "gpio6", "gpio7";
1748                                 function = "qup11_i2c";
1749                         };
1750
1751                         qup_i2c8_default: qup-i2c8-default-state {
1752                                 pins = "gpio42", "gpio43";
1753                                 function = "qup12";
1754                         };
1755
1756                         qup_i2c9_default: qup-i2c9-default-state {
1757                                 pins = "gpio46", "gpio47";
1758                                 function = "qup13_i2c";
1759                         };
1760
1761                         qup_i2c10_default: qup-i2c10-default-state {
1762                                 pins = "gpio86", "gpio87";
1763                                 function = "qup14";
1764                         };
1765
1766                         qup_i2c11_default: qup-i2c11-default-state {
1767                                 pins = "gpio53", "gpio54";
1768                                 function = "qup15";
1769                         };
1770
1771                         qup_spi0_spi: qup-spi0-spi-state {
1772                                 pins = "gpio34", "gpio35", "gpio36";
1773                                 function = "qup00";
1774                         };
1775
1776                         qup_spi0_cs: qup-spi0-cs-state {
1777                                 pins = "gpio37";
1778                                 function = "qup00";
1779                         };
1780
1781                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1782                                 pins = "gpio37";
1783                                 function = "gpio";
1784                         };
1785
1786                         qup_spi1_spi: qup-spi1-spi-state {
1787                                 pins = "gpio0", "gpio1", "gpio2";
1788                                 function = "qup01";
1789                         };
1790
1791                         qup_spi1_cs: qup-spi1-cs-state {
1792                                 pins = "gpio3";
1793                                 function = "qup01";
1794                         };
1795
1796                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1797                                 pins = "gpio3";
1798                                 function = "gpio";
1799                         };
1800
1801                         qup_spi3_spi: qup-spi3-spi-state {
1802                                 pins = "gpio38", "gpio39", "gpio40";
1803                                 function = "qup03";
1804                         };
1805
1806                         qup_spi3_cs: qup-spi3-cs-state {
1807                                 pins = "gpio41";
1808                                 function = "qup03";
1809                         };
1810
1811                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1812                                 pins = "gpio41";
1813                                 function = "gpio";
1814                         };
1815
1816                         qup_spi5_spi: qup-spi5-spi-state {
1817                                 pins = "gpio25", "gpio26", "gpio27";
1818                                 function = "qup05";
1819                         };
1820
1821                         qup_spi5_cs: qup-spi5-cs-state {
1822                                 pins = "gpio28";
1823                                 function = "qup05";
1824                         };
1825
1826                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1827                                 pins = "gpio28";
1828                                 function = "gpio";
1829                         };
1830
1831                         qup_spi6_spi: qup-spi6-spi-state {
1832                                 pins = "gpio59", "gpio60", "gpio61";
1833                                 function = "qup10";
1834                         };
1835
1836                         qup_spi6_cs: qup-spi6-cs-state {
1837                                 pins = "gpio62";
1838                                 function = "qup10";
1839                         };
1840
1841                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1842                                 pins = "gpio62";
1843                                 function = "gpio";
1844                         };
1845
1846                         qup_spi8_spi: qup-spi8-spi-state {
1847                                 pins = "gpio42", "gpio43", "gpio44";
1848                                 function = "qup12";
1849                         };
1850
1851                         qup_spi8_cs: qup-spi8-cs-state {
1852                                 pins = "gpio45";
1853                                 function = "qup12";
1854                         };
1855
1856                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1857                                 pins = "gpio45";
1858                                 function = "gpio";
1859                         };
1860
1861                         qup_spi10_spi: qup-spi10-spi-state {
1862                                 pins = "gpio86", "gpio87", "gpio88";
1863                                 function = "qup14";
1864                         };
1865
1866                         qup_spi10_cs: qup-spi10-cs-state {
1867                                 pins = "gpio89";
1868                                 function = "qup14";
1869                         };
1870
1871                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1872                                 pins = "gpio89";
1873                                 function = "gpio";
1874                         };
1875
1876                         qup_spi11_spi: qup-spi11-spi-state {
1877                                 pins = "gpio53", "gpio54", "gpio55";
1878                                 function = "qup15";
1879                         };
1880
1881                         qup_spi11_cs: qup-spi11-cs-state {
1882                                 pins = "gpio56";
1883                                 function = "qup15";
1884                         };
1885
1886                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1887                                 pins = "gpio56";
1888                                 function = "gpio";
1889                         };
1890
1891                         qup_uart0_default: qup-uart0-default-state {
1892                                 qup_uart0_cts: cts-pins {
1893                                         pins = "gpio34";
1894                                         function = "qup00";
1895                                 };
1896
1897                                 qup_uart0_rts: rts-pins {
1898                                         pins = "gpio35";
1899                                         function = "qup00";
1900                                 };
1901
1902                                 qup_uart0_tx: tx-pins {
1903                                         pins = "gpio36";
1904                                         function = "qup00";
1905                                 };
1906
1907                                 qup_uart0_rx: rx-pins {
1908                                         pins = "gpio37";
1909                                         function = "qup00";
1910                                 };
1911                         };
1912
1913                         qup_uart1_default: qup-uart1-default-state {
1914                                 qup_uart1_cts: cts-pins {
1915                                         pins = "gpio0";
1916                                         function = "qup01";
1917                                 };
1918
1919                                 qup_uart1_rts: rts-pins {
1920                                         pins = "gpio1";
1921                                         function = "qup01";
1922                                 };
1923
1924                                 qup_uart1_tx: tx-pins {
1925                                         pins = "gpio2";
1926                                         function = "qup01";
1927                                 };
1928
1929                                 qup_uart1_rx: rx-pins {
1930                                         pins = "gpio3";
1931                                         function = "qup01";
1932                                 };
1933                         };
1934
1935                         qup_uart2_default: qup-uart2-default-state {
1936                                 qup_uart2_tx: tx-pins {
1937                                         pins = "gpio15";
1938                                         function = "qup02_uart";
1939                                 };
1940
1941                                 qup_uart2_rx: rx-pins {
1942                                         pins = "gpio16";
1943                                         function = "qup02_uart";
1944                                 };
1945                         };
1946
1947                         qup_uart3_default: qup-uart3-default-state {
1948                                 qup_uart3_cts: cts-pins {
1949                                         pins = "gpio38";
1950                                         function = "qup03";
1951                                 };
1952
1953                                 qup_uart3_rts: rts-pins {
1954                                         pins = "gpio39";
1955                                         function = "qup03";
1956                                 };
1957
1958                                 qup_uart3_tx: tx-pins {
1959                                         pins = "gpio40";
1960                                         function = "qup03";
1961                                 };
1962
1963                                 qup_uart3_rx: rx-pins {
1964                                         pins = "gpio41";
1965                                         function = "qup03";
1966                                 };
1967                         };
1968
1969                         qup_uart4_default: qup-uart4-default-state {
1970                                 qup_uart4_tx: tx-pins {
1971                                         pins = "gpio115";
1972                                         function = "qup04_uart";
1973                                 };
1974
1975                                 qup_uart4_rx: rx-pins {
1976                                         pins = "gpio116";
1977                                         function = "qup04_uart";
1978                                 };
1979                         };
1980
1981                         qup_uart5_default: qup-uart5-default-state {
1982                                 qup_uart5_cts: cts-pins {
1983                                         pins = "gpio25";
1984                                         function = "qup05";
1985                                 };
1986
1987                                 qup_uart5_rts: rts-pins {
1988                                         pins = "gpio26";
1989                                         function = "qup05";
1990                                 };
1991
1992                                 qup_uart5_tx: tx-pins {
1993                                         pins = "gpio27";
1994                                         function = "qup05";
1995                                 };
1996
1997                                 qup_uart5_rx: rx-pins {
1998                                         pins = "gpio28";
1999                                         function = "qup05";
2000                                 };
2001                         };
2002
2003                         qup_uart6_default: qup-uart6-default-state {
2004                                 qup_uart6_cts: cts-pins {
2005                                         pins = "gpio59";
2006                                         function = "qup10";
2007                                 };
2008
2009                                 qup_uart6_rts: rts-pins {
2010                                         pins = "gpio60";
2011                                         function = "qup10";
2012                                 };
2013
2014                                 qup_uart6_tx: tx-pins {
2015                                         pins = "gpio61";
2016                                         function = "qup10";
2017                                 };
2018
2019                                 qup_uart6_rx: rx-pins {
2020                                         pins = "gpio62";
2021                                         function = "qup10";
2022                                 };
2023                         };
2024
2025                         qup_uart7_default: qup-uart7-default-state {
2026                                 qup_uart7_tx: tx-pins {
2027                                         pins = "gpio6";
2028                                         function = "qup11_uart";
2029                                 };
2030
2031                                 qup_uart7_rx: rx-pins {
2032                                         pins = "gpio7";
2033                                         function = "qup11_uart";
2034                                 };
2035                         };
2036
2037                         qup_uart8_default: qup-uart8-default-state {
2038                                 qup_uart8_tx: tx-pins {
2039                                         pins = "gpio44";
2040                                         function = "qup12";
2041                                 };
2042
2043                                 qup_uart8_rx: rx-pins {
2044                                         pins = "gpio45";
2045                                         function = "qup12";
2046                                 };
2047                         };
2048
2049                         qup_uart9_default: qup-uart9-default-state {
2050                                 qup_uart9_tx: tx-pins {
2051                                         pins = "gpio46";
2052                                         function = "qup13_uart";
2053                                 };
2054
2055                                 qup_uart9_rx: rx-pins {
2056                                         pins = "gpio47";
2057                                         function = "qup13_uart";
2058                                 };
2059                         };
2060
2061                         qup_uart10_default: qup-uart10-default-state {
2062                                 qup_uart10_cts: cts-pins {
2063                                         pins = "gpio86";
2064                                         function = "qup14";
2065                                 };
2066
2067                                 qup_uart10_rts: rts-pins {
2068                                         pins = "gpio87";
2069                                         function = "qup14";
2070                                 };
2071
2072                                 qup_uart10_tx: tx-pins {
2073                                         pins = "gpio88";
2074                                         function = "qup14";
2075                                 };
2076
2077                                 qup_uart10_rx: rx-pins {
2078                                         pins = "gpio89";
2079                                         function = "qup14";
2080                                 };
2081                         };
2082
2083                         qup_uart11_default: qup-uart11-default-state {
2084                                 qup_uart11_cts: cts-pins {
2085                                         pins = "gpio53";
2086                                         function = "qup15";
2087                                 };
2088
2089                                 qup_uart11_rts: rts-pins {
2090                                         pins = "gpio54";
2091                                         function = "qup15";
2092                                 };
2093
2094                                 qup_uart11_tx: tx-pins {
2095                                         pins = "gpio55";
2096                                         function = "qup15";
2097                                 };
2098
2099                                 qup_uart11_rx: rx-pins {
2100                                         pins = "gpio56";
2101                                         function = "qup15";
2102                                 };
2103                         };
2104
2105                         sec_mi2s_active: sec-mi2s-active-state {
2106                                 pins = "gpio49", "gpio50", "gpio51";
2107                                 function = "mi2s_1";
2108                         };
2109
2110                         pri_mi2s_active: pri-mi2s-active-state {
2111                                 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2112                                 function = "mi2s_0";
2113                         };
2114
2115                         pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2116                                 pins = "gpio57";
2117                                 function = "lpass_ext";
2118                         };
2119
2120                         ter_mi2s_active: ter-mi2s-active-state {
2121                                 pins = "gpio63", "gpio64", "gpio65", "gpio66";
2122                                 function = "mi2s_2";
2123                         };
2124                 };
2125
2126                 remoteproc_mpss: remoteproc@4080000 {
2127                         compatible = "qcom,sc7180-mpss-pas";
2128                         reg = <0 0x04080000 0 0x4040>;
2129
2130                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2131                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2132                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2133                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2134                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2135                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2136                         interrupt-names = "wdog", "fatal", "ready", "handover",
2137                                           "stop-ack", "shutdown-ack";
2138
2139                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2140                         clock-names = "xo";
2141
2142                         power-domains = <&rpmhpd SC7180_CX>,
2143                                         <&rpmhpd SC7180_MX>,
2144                                         <&rpmhpd SC7180_MSS>;
2145                         power-domain-names = "cx", "mx", "mss";
2146
2147                         memory-region = <&mpss_mem>;
2148
2149                         qcom,qmp = <&aoss_qmp>;
2150
2151                         qcom,smem-states = <&modem_smp2p_out 0>;
2152                         qcom,smem-state-names = "stop";
2153
2154                         status = "disabled";
2155
2156                         glink-edge {
2157                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2158                                 label = "modem";
2159                                 qcom,remote-pid = <1>;
2160                                 mboxes = <&apss_shared 12>;
2161                         };
2162                 };
2163
2164                 gpu: gpu@5000000 {
2165                         compatible = "qcom,adreno-618.0", "qcom,adreno";
2166                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2167                                 <0 0x05061000 0 0x800>;
2168                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2169                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2170                         iommus = <&adreno_smmu 0>;
2171                         operating-points-v2 = <&gpu_opp_table>;
2172                         qcom,gmu = <&gmu>;
2173
2174                         #cooling-cells = <2>;
2175
2176                         nvmem-cells = <&gpu_speed_bin>;
2177                         nvmem-cell-names = "speed_bin";
2178
2179                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2180                         interconnect-names = "gfx-mem";
2181
2182                         gpu_opp_table: opp-table {
2183                                 compatible = "operating-points-v2";
2184
2185                                 opp-825000000 {
2186                                         opp-hz = /bits/ 64 <825000000>;
2187                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2188                                         opp-peak-kBps = <8532000>;
2189                                         opp-supported-hw = <0x04>;
2190                                 };
2191
2192                                 opp-800000000 {
2193                                         opp-hz = /bits/ 64 <800000000>;
2194                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2195                                         opp-peak-kBps = <8532000>;
2196                                         opp-supported-hw = <0x07>;
2197                                 };
2198
2199                                 opp-650000000 {
2200                                         opp-hz = /bits/ 64 <650000000>;
2201                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2202                                         opp-peak-kBps = <7216000>;
2203                                         opp-supported-hw = <0x07>;
2204                                 };
2205
2206                                 opp-565000000 {
2207                                         opp-hz = /bits/ 64 <565000000>;
2208                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2209                                         opp-peak-kBps = <5412000>;
2210                                         opp-supported-hw = <0x07>;
2211                                 };
2212
2213                                 opp-430000000 {
2214                                         opp-hz = /bits/ 64 <430000000>;
2215                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2216                                         opp-peak-kBps = <5412000>;
2217                                         opp-supported-hw = <0x07>;
2218                                 };
2219
2220                                 opp-355000000 {
2221                                         opp-hz = /bits/ 64 <355000000>;
2222                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2223                                         opp-peak-kBps = <3072000>;
2224                                         opp-supported-hw = <0x07>;
2225                                 };
2226
2227                                 opp-267000000 {
2228                                         opp-hz = /bits/ 64 <267000000>;
2229                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2230                                         opp-peak-kBps = <3072000>;
2231                                         opp-supported-hw = <0x07>;
2232                                 };
2233
2234                                 opp-180000000 {
2235                                         opp-hz = /bits/ 64 <180000000>;
2236                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2237                                         opp-peak-kBps = <1804000>;
2238                                         opp-supported-hw = <0x07>;
2239                                 };
2240                         };
2241                 };
2242
2243                 adreno_smmu: iommu@5040000 {
2244                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2245                         reg = <0 0x05040000 0 0x10000>;
2246                         #iommu-cells = <1>;
2247                         #global-interrupts = <2>;
2248                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2249                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2250                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2251                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2252                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2253                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2254                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2255                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2256                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2257                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2258
2259                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2260                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2261                         clock-names = "bus", "iface";
2262
2263                         power-domains = <&gpucc CX_GDSC>;
2264                 };
2265
2266                 gmu: gmu@506a000 {
2267                         compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2268                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2269                                 <0 0x0b490000 0 0x10000>;
2270                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2271                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2272                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2273                         interrupt-names = "hfi", "gmu";
2274                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2275                                <&gpucc GPU_CC_CXO_CLK>,
2276                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2277                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2278                         clock-names = "gmu", "cxo", "axi", "memnoc";
2279                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2280                         power-domain-names = "cx", "gx";
2281                         iommus = <&adreno_smmu 5>;
2282                         operating-points-v2 = <&gmu_opp_table>;
2283
2284                         gmu_opp_table: opp-table {
2285                                 compatible = "operating-points-v2";
2286
2287                                 opp-200000000 {
2288                                         opp-hz = /bits/ 64 <200000000>;
2289                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2290                                 };
2291                         };
2292                 };
2293
2294                 gpucc: clock-controller@5090000 {
2295                         compatible = "qcom,sc7180-gpucc";
2296                         reg = <0 0x05090000 0 0x9000>;
2297                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2298                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2299                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2300                         clock-names = "bi_tcxo",
2301                                       "gcc_gpu_gpll0_clk_src",
2302                                       "gcc_gpu_gpll0_div_clk_src";
2303                         #clock-cells = <1>;
2304                         #reset-cells = <1>;
2305                         #power-domain-cells = <1>;
2306                 };
2307
2308                 dma@10a2000 {
2309                         compatible = "qcom,sc7180-dcc", "qcom,dcc";
2310                         reg = <0x0 0x010a2000 0x0 0x1000>,
2311                               <0x0 0x010ae000 0x0 0x2000>;
2312                 };
2313
2314                 stm@6002000 {
2315                         compatible = "arm,coresight-stm", "arm,primecell";
2316                         reg = <0 0x06002000 0 0x1000>,
2317                               <0 0x16280000 0 0x180000>;
2318                         reg-names = "stm-base", "stm-stimulus-base";
2319
2320                         clocks = <&aoss_qmp>;
2321                         clock-names = "apb_pclk";
2322
2323                         out-ports {
2324                                 port {
2325                                         stm_out: endpoint {
2326                                                 remote-endpoint = <&funnel0_in7>;
2327                                         };
2328                                 };
2329                         };
2330                 };
2331
2332                 funnel@6041000 {
2333                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2334                         reg = <0 0x06041000 0 0x1000>;
2335
2336                         clocks = <&aoss_qmp>;
2337                         clock-names = "apb_pclk";
2338
2339                         out-ports {
2340                                 port {
2341                                         funnel0_out: endpoint {
2342                                                 remote-endpoint = <&merge_funnel_in0>;
2343                                         };
2344                                 };
2345                         };
2346
2347                         in-ports {
2348                                 #address-cells = <1>;
2349                                 #size-cells = <0>;
2350
2351                                 port@7 {
2352                                         reg = <7>;
2353                                         funnel0_in7: endpoint {
2354                                                 remote-endpoint = <&stm_out>;
2355                                         };
2356                                 };
2357                         };
2358                 };
2359
2360                 funnel@6042000 {
2361                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2362                         reg = <0 0x06042000 0 0x1000>;
2363
2364                         clocks = <&aoss_qmp>;
2365                         clock-names = "apb_pclk";
2366
2367                         out-ports {
2368                                 port {
2369                                         funnel1_out: endpoint {
2370                                                 remote-endpoint = <&merge_funnel_in1>;
2371                                         };
2372                                 };
2373                         };
2374
2375                         in-ports {
2376                                 #address-cells = <1>;
2377                                 #size-cells = <0>;
2378
2379                                 port@4 {
2380                                         reg = <4>;
2381                                         funnel1_in4: endpoint {
2382                                                 remote-endpoint = <&apss_merge_funnel_out>;
2383                                         };
2384                                 };
2385                         };
2386                 };
2387
2388                 funnel@6045000 {
2389                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2390                         reg = <0 0x06045000 0 0x1000>;
2391
2392                         clocks = <&aoss_qmp>;
2393                         clock-names = "apb_pclk";
2394
2395                         out-ports {
2396                                 port {
2397                                         merge_funnel_out: endpoint {
2398                                                 remote-endpoint = <&swao_funnel_in>;
2399                                         };
2400                                 };
2401                         };
2402
2403                         in-ports {
2404                                 #address-cells = <1>;
2405                                 #size-cells = <0>;
2406
2407                                 port@0 {
2408                                         reg = <0>;
2409                                         merge_funnel_in0: endpoint {
2410                                                 remote-endpoint = <&funnel0_out>;
2411                                         };
2412                                 };
2413
2414                                 port@1 {
2415                                         reg = <1>;
2416                                         merge_funnel_in1: endpoint {
2417                                                 remote-endpoint = <&funnel1_out>;
2418                                         };
2419                                 };
2420                         };
2421                 };
2422
2423                 replicator@6046000 {
2424                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2425                         reg = <0 0x06046000 0 0x1000>;
2426
2427                         clocks = <&aoss_qmp>;
2428                         clock-names = "apb_pclk";
2429
2430                         out-ports {
2431                                 port {
2432                                         replicator_out: endpoint {
2433                                                 remote-endpoint = <&etr_in>;
2434                                         };
2435                                 };
2436                         };
2437
2438                         in-ports {
2439                                 port {
2440                                         replicator_in: endpoint {
2441                                                 remote-endpoint = <&swao_replicator_out>;
2442                                         };
2443                                 };
2444                         };
2445                 };
2446
2447                 etr@6048000 {
2448                         compatible = "arm,coresight-tmc", "arm,primecell";
2449                         reg = <0 0x06048000 0 0x1000>;
2450                         iommus = <&apps_smmu 0x04a0 0x20>;
2451
2452                         clocks = <&aoss_qmp>;
2453                         clock-names = "apb_pclk";
2454                         arm,scatter-gather;
2455
2456                         in-ports {
2457                                 port {
2458                                         etr_in: endpoint {
2459                                                 remote-endpoint = <&replicator_out>;
2460                                         };
2461                                 };
2462                         };
2463                 };
2464
2465                 funnel@6b04000 {
2466                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2467                         reg = <0 0x06b04000 0 0x1000>;
2468
2469                         clocks = <&aoss_qmp>;
2470                         clock-names = "apb_pclk";
2471
2472                         out-ports {
2473                                 port {
2474                                         swao_funnel_out: endpoint {
2475                                                 remote-endpoint = <&etf_in>;
2476                                         };
2477                                 };
2478                         };
2479
2480                         in-ports {
2481                                 #address-cells = <1>;
2482                                 #size-cells = <0>;
2483
2484                                 port@7 {
2485                                         reg = <7>;
2486                                         swao_funnel_in: endpoint {
2487                                                 remote-endpoint = <&merge_funnel_out>;
2488                                         };
2489                                 };
2490                         };
2491                 };
2492
2493                 etf@6b05000 {
2494                         compatible = "arm,coresight-tmc", "arm,primecell";
2495                         reg = <0 0x06b05000 0 0x1000>;
2496
2497                         clocks = <&aoss_qmp>;
2498                         clock-names = "apb_pclk";
2499
2500                         out-ports {
2501                                 port {
2502                                         etf_out: endpoint {
2503                                                 remote-endpoint = <&swao_replicator_in>;
2504                                         };
2505                                 };
2506                         };
2507
2508                         in-ports {
2509                                 port {
2510                                         etf_in: endpoint {
2511                                                 remote-endpoint = <&swao_funnel_out>;
2512                                         };
2513                                 };
2514                         };
2515                 };
2516
2517                 replicator@6b06000 {
2518                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2519                         reg = <0 0x06b06000 0 0x1000>;
2520
2521                         clocks = <&aoss_qmp>;
2522                         clock-names = "apb_pclk";
2523                         qcom,replicator-loses-context;
2524
2525                         out-ports {
2526                                 port {
2527                                         swao_replicator_out: endpoint {
2528                                                 remote-endpoint = <&replicator_in>;
2529                                         };
2530                                 };
2531                         };
2532
2533                         in-ports {
2534                                 port {
2535                                         swao_replicator_in: endpoint {
2536                                                 remote-endpoint = <&etf_out>;
2537                                         };
2538                                 };
2539                         };
2540                 };
2541
2542                 etm@7040000 {
2543                         compatible = "arm,coresight-etm4x", "arm,primecell";
2544                         reg = <0 0x07040000 0 0x1000>;
2545
2546                         cpu = <&CPU0>;
2547
2548                         clocks = <&aoss_qmp>;
2549                         clock-names = "apb_pclk";
2550                         arm,coresight-loses-context-with-cpu;
2551                         qcom,skip-power-up;
2552
2553                         out-ports {
2554                                 port {
2555                                         etm0_out: endpoint {
2556                                                 remote-endpoint = <&apss_funnel_in0>;
2557                                         };
2558                                 };
2559                         };
2560                 };
2561
2562                 etm@7140000 {
2563                         compatible = "arm,coresight-etm4x", "arm,primecell";
2564                         reg = <0 0x07140000 0 0x1000>;
2565
2566                         cpu = <&CPU1>;
2567
2568                         clocks = <&aoss_qmp>;
2569                         clock-names = "apb_pclk";
2570                         arm,coresight-loses-context-with-cpu;
2571                         qcom,skip-power-up;
2572
2573                         out-ports {
2574                                 port {
2575                                         etm1_out: endpoint {
2576                                                 remote-endpoint = <&apss_funnel_in1>;
2577                                         };
2578                                 };
2579                         };
2580                 };
2581
2582                 etm@7240000 {
2583                         compatible = "arm,coresight-etm4x", "arm,primecell";
2584                         reg = <0 0x07240000 0 0x1000>;
2585
2586                         cpu = <&CPU2>;
2587
2588                         clocks = <&aoss_qmp>;
2589                         clock-names = "apb_pclk";
2590                         arm,coresight-loses-context-with-cpu;
2591                         qcom,skip-power-up;
2592
2593                         out-ports {
2594                                 port {
2595                                         etm2_out: endpoint {
2596                                                 remote-endpoint = <&apss_funnel_in2>;
2597                                         };
2598                                 };
2599                         };
2600                 };
2601
2602                 etm@7340000 {
2603                         compatible = "arm,coresight-etm4x", "arm,primecell";
2604                         reg = <0 0x07340000 0 0x1000>;
2605
2606                         cpu = <&CPU3>;
2607
2608                         clocks = <&aoss_qmp>;
2609                         clock-names = "apb_pclk";
2610                         arm,coresight-loses-context-with-cpu;
2611                         qcom,skip-power-up;
2612
2613                         out-ports {
2614                                 port {
2615                                         etm3_out: endpoint {
2616                                                 remote-endpoint = <&apss_funnel_in3>;
2617                                         };
2618                                 };
2619                         };
2620                 };
2621
2622                 etm@7440000 {
2623                         compatible = "arm,coresight-etm4x", "arm,primecell";
2624                         reg = <0 0x07440000 0 0x1000>;
2625
2626                         cpu = <&CPU4>;
2627
2628                         clocks = <&aoss_qmp>;
2629                         clock-names = "apb_pclk";
2630                         arm,coresight-loses-context-with-cpu;
2631                         qcom,skip-power-up;
2632
2633                         out-ports {
2634                                 port {
2635                                         etm4_out: endpoint {
2636                                                 remote-endpoint = <&apss_funnel_in4>;
2637                                         };
2638                                 };
2639                         };
2640                 };
2641
2642                 etm@7540000 {
2643                         compatible = "arm,coresight-etm4x", "arm,primecell";
2644                         reg = <0 0x07540000 0 0x1000>;
2645
2646                         cpu = <&CPU5>;
2647
2648                         clocks = <&aoss_qmp>;
2649                         clock-names = "apb_pclk";
2650                         arm,coresight-loses-context-with-cpu;
2651                         qcom,skip-power-up;
2652
2653                         out-ports {
2654                                 port {
2655                                         etm5_out: endpoint {
2656                                                 remote-endpoint = <&apss_funnel_in5>;
2657                                         };
2658                                 };
2659                         };
2660                 };
2661
2662                 etm@7640000 {
2663                         compatible = "arm,coresight-etm4x", "arm,primecell";
2664                         reg = <0 0x07640000 0 0x1000>;
2665
2666                         cpu = <&CPU6>;
2667
2668                         clocks = <&aoss_qmp>;
2669                         clock-names = "apb_pclk";
2670                         arm,coresight-loses-context-with-cpu;
2671                         qcom,skip-power-up;
2672
2673                         out-ports {
2674                                 port {
2675                                         etm6_out: endpoint {
2676                                                 remote-endpoint = <&apss_funnel_in6>;
2677                                         };
2678                                 };
2679                         };
2680                 };
2681
2682                 etm@7740000 {
2683                         compatible = "arm,coresight-etm4x", "arm,primecell";
2684                         reg = <0 0x07740000 0 0x1000>;
2685
2686                         cpu = <&CPU7>;
2687
2688                         clocks = <&aoss_qmp>;
2689                         clock-names = "apb_pclk";
2690                         arm,coresight-loses-context-with-cpu;
2691                         qcom,skip-power-up;
2692
2693                         out-ports {
2694                                 port {
2695                                         etm7_out: endpoint {
2696                                                 remote-endpoint = <&apss_funnel_in7>;
2697                                         };
2698                                 };
2699                         };
2700                 };
2701
2702                 funnel@7800000 { /* APSS Funnel */
2703                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2704                         reg = <0 0x07800000 0 0x1000>;
2705
2706                         clocks = <&aoss_qmp>;
2707                         clock-names = "apb_pclk";
2708
2709                         out-ports {
2710                                 port {
2711                                         apss_funnel_out: endpoint {
2712                                                 remote-endpoint = <&apss_merge_funnel_in>;
2713                                         };
2714                                 };
2715                         };
2716
2717                         in-ports {
2718                                 #address-cells = <1>;
2719                                 #size-cells = <0>;
2720
2721                                 port@0 {
2722                                         reg = <0>;
2723                                         apss_funnel_in0: endpoint {
2724                                                 remote-endpoint = <&etm0_out>;
2725                                         };
2726                                 };
2727
2728                                 port@1 {
2729                                         reg = <1>;
2730                                         apss_funnel_in1: endpoint {
2731                                                 remote-endpoint = <&etm1_out>;
2732                                         };
2733                                 };
2734
2735                                 port@2 {
2736                                         reg = <2>;
2737                                         apss_funnel_in2: endpoint {
2738                                                 remote-endpoint = <&etm2_out>;
2739                                         };
2740                                 };
2741
2742                                 port@3 {
2743                                         reg = <3>;
2744                                         apss_funnel_in3: endpoint {
2745                                                 remote-endpoint = <&etm3_out>;
2746                                         };
2747                                 };
2748
2749                                 port@4 {
2750                                         reg = <4>;
2751                                         apss_funnel_in4: endpoint {
2752                                                 remote-endpoint = <&etm4_out>;
2753                                         };
2754                                 };
2755
2756                                 port@5 {
2757                                         reg = <5>;
2758                                         apss_funnel_in5: endpoint {
2759                                                 remote-endpoint = <&etm5_out>;
2760                                         };
2761                                 };
2762
2763                                 port@6 {
2764                                         reg = <6>;
2765                                         apss_funnel_in6: endpoint {
2766                                                 remote-endpoint = <&etm6_out>;
2767                                         };
2768                                 };
2769
2770                                 port@7 {
2771                                         reg = <7>;
2772                                         apss_funnel_in7: endpoint {
2773                                                 remote-endpoint = <&etm7_out>;
2774                                         };
2775                                 };
2776                         };
2777                 };
2778
2779                 funnel@7810000 {
2780                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2781                         reg = <0 0x07810000 0 0x1000>;
2782
2783                         clocks = <&aoss_qmp>;
2784                         clock-names = "apb_pclk";
2785
2786                         out-ports {
2787                                 port {
2788                                         apss_merge_funnel_out: endpoint {
2789                                                 remote-endpoint = <&funnel1_in4>;
2790                                         };
2791                                 };
2792                         };
2793
2794                         in-ports {
2795                                 port {
2796                                         apss_merge_funnel_in: endpoint {
2797                                                 remote-endpoint = <&apss_funnel_out>;
2798                                         };
2799                                 };
2800                         };
2801                 };
2802
2803                 sdhc_2: mmc@8804000 {
2804                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2805                         reg = <0 0x08804000 0 0x1000>;
2806
2807                         iommus = <&apps_smmu 0x80 0>;
2808                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2809                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2810                         interrupt-names = "hc_irq", "pwr_irq";
2811
2812                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2813                                  <&gcc GCC_SDCC2_APPS_CLK>,
2814                                  <&rpmhcc RPMH_CXO_CLK>;
2815                         clock-names = "iface", "core", "xo";
2816
2817                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2818                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2819                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2820                         power-domains = <&rpmhpd SC7180_CX>;
2821                         operating-points-v2 = <&sdhc2_opp_table>;
2822
2823                         bus-width = <4>;
2824
2825                         status = "disabled";
2826
2827                         sdhc2_opp_table: opp-table {
2828                                 compatible = "operating-points-v2";
2829
2830                                 opp-100000000 {
2831                                         opp-hz = /bits/ 64 <100000000>;
2832                                         required-opps = <&rpmhpd_opp_low_svs>;
2833                                         opp-peak-kBps = <1800000 600000>;
2834                                         opp-avg-kBps = <100000 0>;
2835                                 };
2836
2837                                 opp-202000000 {
2838                                         opp-hz = /bits/ 64 <202000000>;
2839                                         required-opps = <&rpmhpd_opp_nom>;
2840                                         opp-peak-kBps = <5400000 1600000>;
2841                                         opp-avg-kBps = <200000 0>;
2842                                 };
2843                         };
2844                 };
2845
2846                 qspi: spi@88dc000 {
2847                         compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2848                         reg = <0 0x088dc000 0 0x600>;
2849                         iommus = <&apps_smmu 0x20 0x0>;
2850                         #address-cells = <1>;
2851                         #size-cells = <0>;
2852                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2853                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2854                                  <&gcc GCC_QSPI_CORE_CLK>;
2855                         clock-names = "iface", "core";
2856                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2857                                         &config_noc SLAVE_QSPI_0 0>;
2858                         interconnect-names = "qspi-config";
2859                         power-domains = <&rpmhpd SC7180_CX>;
2860                         operating-points-v2 = <&qspi_opp_table>;
2861                         status = "disabled";
2862                 };
2863
2864                 usb_1_hsphy: phy@88e3000 {
2865                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2866                         reg = <0 0x088e3000 0 0x400>;
2867                         status = "disabled";
2868                         #phy-cells = <0>;
2869                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2870                                  <&rpmhcc RPMH_CXO_CLK>;
2871                         clock-names = "cfg_ahb", "ref";
2872                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2873
2874                         nvmem-cells = <&qusb2p_hstx_trim>;
2875                 };
2876
2877                 usb_1_qmpphy: phy@88e8000 {
2878                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2879                         reg = <0 0x088e8000 0 0x3000>;
2880                         status = "disabled";
2881
2882                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2883                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2884                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2885                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
2886                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2887                         clock-names = "aux",
2888                                       "ref",
2889                                       "com_aux",
2890                                       "usb3_pipe",
2891                                       "cfg_ahb";
2892
2893                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2894                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2895                         reset-names = "phy", "common";
2896
2897                         #clock-cells = <1>;
2898                         #phy-cells = <1>;
2899                 };
2900
2901                 pmu@90b6300 {
2902                         compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2903                         reg = <0 0x090b6300 0 0x600>;
2904                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2905
2906                         interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2907                                          &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
2908                         operating-points-v2 = <&cpu_bwmon_opp_table>;
2909
2910                         cpu_bwmon_opp_table: opp-table {
2911                                 compatible = "operating-points-v2";
2912
2913                                 opp-0 {
2914                                         opp-peak-kBps = <2288000>;
2915                                 };
2916
2917                                 opp-1 {
2918                                         opp-peak-kBps = <4577000>;
2919                                 };
2920
2921                                 opp-2 {
2922                                         opp-peak-kBps = <7110000>;
2923                                 };
2924
2925                                 opp-3 {
2926                                         opp-peak-kBps = <9155000>;
2927                                 };
2928
2929                                 opp-4 {
2930                                         opp-peak-kBps = <12298000>;
2931                                 };
2932
2933                                 opp-5 {
2934                                         opp-peak-kBps = <14236000>;
2935                                 };
2936                         };
2937                 };
2938
2939                 pmu@90cd000 {
2940                         compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2941                         reg = <0 0x090cd000 0 0x1000>;
2942                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2943
2944                         interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
2945                                          &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2946                         operating-points-v2 = <&llcc_bwmon_opp_table>;
2947
2948                         llcc_bwmon_opp_table: opp-table {
2949                                 compatible = "operating-points-v2";
2950
2951                                 opp-0 {
2952                                         opp-peak-kBps = <1144000>;
2953                                 };
2954
2955                                 opp-1 {
2956                                         opp-peak-kBps = <1720000>;
2957                                 };
2958
2959                                 opp-2 {
2960                                         opp-peak-kBps = <2086000>;
2961                                 };
2962
2963                                 opp-3 {
2964                                         opp-peak-kBps = <2929000>;
2965                                 };
2966
2967                                 opp-4 {
2968                                         opp-peak-kBps = <3879000>;
2969                                 };
2970
2971                                 opp-5 {
2972                                         opp-peak-kBps = <5931000>;
2973                                 };
2974
2975                                 opp-6 {
2976                                         opp-peak-kBps = <6881000>;
2977                                 };
2978
2979                                 opp-7 {
2980                                         opp-peak-kBps = <8137000>;
2981                                 };
2982                         };
2983                 };
2984
2985                 dc_noc: interconnect@9160000 {
2986                         compatible = "qcom,sc7180-dc-noc";
2987                         reg = <0 0x09160000 0 0x03200>;
2988                         #interconnect-cells = <2>;
2989                         qcom,bcm-voters = <&apps_bcm_voter>;
2990                 };
2991
2992                 system-cache-controller@9200000 {
2993                         compatible = "qcom,sc7180-llcc";
2994                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2995                         reg-names = "llcc0_base", "llcc_broadcast_base";
2996                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2997                 };
2998
2999                 gem_noc: interconnect@9680000 {
3000                         compatible = "qcom,sc7180-gem-noc";
3001                         reg = <0 0x09680000 0 0x3e200>;
3002                         #interconnect-cells = <2>;
3003                         qcom,bcm-voters = <&apps_bcm_voter>;
3004                 };
3005
3006                 npu_noc: interconnect@9990000 {
3007                         compatible = "qcom,sc7180-npu-noc";
3008                         reg = <0 0x09990000 0 0x1600>;
3009                         #interconnect-cells = <2>;
3010                         qcom,bcm-voters = <&apps_bcm_voter>;
3011                 };
3012
3013                 usb_1: usb@a6f8800 {
3014                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3015                         reg = <0 0x0a6f8800 0 0x400>;
3016                         status = "disabled";
3017                         #address-cells = <2>;
3018                         #size-cells = <2>;
3019                         ranges;
3020                         dma-ranges;
3021
3022                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3023                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3024                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3025                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3026                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3027                         clock-names = "cfg_noc",
3028                                       "core",
3029                                       "iface",
3030                                       "sleep",
3031                                       "mock_utmi";
3032
3033                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3034                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3035                         assigned-clock-rates = <19200000>, <150000000>;
3036
3037                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3038                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3039                                               <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3040                                               <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3041                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3042                         interrupt-names = "pwr_event",
3043                                           "hs_phy_irq",
3044                                           "dp_hs_phy_irq",
3045                                           "dm_hs_phy_irq",
3046                                           "ss_phy_irq";
3047
3048                         power-domains = <&gcc USB30_PRIM_GDSC>;
3049                         required-opps = <&rpmhpd_opp_nom>;
3050
3051                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3052
3053                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3054                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3055                         interconnect-names = "usb-ddr", "apps-usb";
3056
3057                         wakeup-source;
3058
3059                         usb_1_dwc3: usb@a600000 {
3060                                 compatible = "snps,dwc3";
3061                                 reg = <0 0x0a600000 0 0xe000>;
3062                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3063                                 iommus = <&apps_smmu 0x540 0>;
3064                                 snps,dis_u2_susphy_quirk;
3065                                 snps,dis_enblslpm_quirk;
3066                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3067                                 phy-names = "usb2-phy", "usb3-phy";
3068                                 maximum-speed = "super-speed";
3069                         };
3070                 };
3071
3072                 venus: video-codec@aa00000 {
3073                         compatible = "qcom,sc7180-venus";
3074                         reg = <0 0x0aa00000 0 0xff000>;
3075                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3076                         power-domains = <&videocc VENUS_GDSC>,
3077                                         <&videocc VCODEC0_GDSC>,
3078                                         <&rpmhpd SC7180_CX>;
3079                         power-domain-names = "venus", "vcodec0", "cx";
3080                         operating-points-v2 = <&venus_opp_table>;
3081                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3082                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3083                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3084                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3085                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3086                         clock-names = "core", "iface", "bus",
3087                                       "vcodec0_core", "vcodec0_bus";
3088                         iommus = <&apps_smmu 0x0c00 0x60>;
3089                         memory-region = <&venus_mem>;
3090                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3091                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3092                         interconnect-names = "video-mem", "cpu-cfg";
3093
3094                         video-decoder {
3095                                 compatible = "venus-decoder";
3096                         };
3097
3098                         video-encoder {
3099                                 compatible = "venus-encoder";
3100                         };
3101
3102                         venus_opp_table: opp-table {
3103                                 compatible = "operating-points-v2";
3104
3105                                 opp-150000000 {
3106                                         opp-hz = /bits/ 64 <150000000>;
3107                                         required-opps = <&rpmhpd_opp_low_svs>;
3108                                 };
3109
3110                                 opp-270000000 {
3111                                         opp-hz = /bits/ 64 <270000000>;
3112                                         required-opps = <&rpmhpd_opp_svs>;
3113                                 };
3114
3115                                 opp-340000000 {
3116                                         opp-hz = /bits/ 64 <340000000>;
3117                                         required-opps = <&rpmhpd_opp_svs_l1>;
3118                                 };
3119
3120                                 opp-434000000 {
3121                                         opp-hz = /bits/ 64 <434000000>;
3122                                         required-opps = <&rpmhpd_opp_nom>;
3123                                 };
3124
3125                                 opp-500000097 {
3126                                         opp-hz = /bits/ 64 <500000097>;
3127                                         required-opps = <&rpmhpd_opp_turbo>;
3128                                 };
3129                         };
3130                 };
3131
3132                 videocc: clock-controller@ab00000 {
3133                         compatible = "qcom,sc7180-videocc";
3134                         reg = <0 0x0ab00000 0 0x10000>;
3135                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3136                         clock-names = "bi_tcxo";
3137                         #clock-cells = <1>;
3138                         #reset-cells = <1>;
3139                         #power-domain-cells = <1>;
3140                 };
3141
3142                 camnoc_virt: interconnect@ac00000 {
3143                         compatible = "qcom,sc7180-camnoc-virt";
3144                         reg = <0 0x0ac00000 0 0x1000>;
3145                         #interconnect-cells = <2>;
3146                         qcom,bcm-voters = <&apps_bcm_voter>;
3147                 };
3148
3149                 camcc: clock-controller@ad00000 {
3150                         compatible = "qcom,sc7180-camcc";
3151                         reg = <0 0x0ad00000 0 0x10000>;
3152                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3153                                <&gcc GCC_CAMERA_AHB_CLK>,
3154                                <&gcc GCC_CAMERA_XO_CLK>;
3155                         clock-names = "bi_tcxo", "iface", "xo";
3156                         #clock-cells = <1>;
3157                         #reset-cells = <1>;
3158                         #power-domain-cells = <1>;
3159                 };
3160
3161                 mdss: display-subsystem@ae00000 {
3162                         compatible = "qcom,sc7180-mdss";
3163                         reg = <0 0x0ae00000 0 0x1000>;
3164                         reg-names = "mdss";
3165
3166                         power-domains = <&dispcc MDSS_GDSC>;
3167
3168                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3169                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3170                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3171                         clock-names = "iface", "ahb", "core";
3172
3173                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3174                         interrupt-controller;
3175                         #interrupt-cells = <1>;
3176
3177                         interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
3178                                          &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3179                                         <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3180                                          &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
3181                         interconnect-names = "mdp0-mem",
3182                                              "cpu-cfg";
3183
3184                         iommus = <&apps_smmu 0x800 0x2>;
3185
3186                         #address-cells = <2>;
3187                         #size-cells = <2>;
3188                         ranges;
3189
3190                         status = "disabled";
3191
3192                         mdp: display-controller@ae01000 {
3193                                 compatible = "qcom,sc7180-dpu";
3194                                 reg = <0 0x0ae01000 0 0x8f000>,
3195                                       <0 0x0aeb0000 0 0x2008>;
3196                                 reg-names = "mdp", "vbif";
3197
3198                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3199                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3200                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
3201                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3202                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3203                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3204                                 clock-names = "bus", "iface", "rot", "lut", "core",
3205                                               "vsync";
3206                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3207                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
3208                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
3209                                 assigned-clock-rates = <19200000>,
3210                                                        <19200000>,
3211                                                        <19200000>;
3212                                 operating-points-v2 = <&mdp_opp_table>;
3213                                 power-domains = <&rpmhpd SC7180_CX>;
3214
3215                                 interrupt-parent = <&mdss>;
3216                                 interrupts = <0>;
3217
3218                                 ports {
3219                                         #address-cells = <1>;
3220                                         #size-cells = <0>;
3221
3222                                         port@0 {
3223                                                 reg = <0>;
3224                                                 dpu_intf1_out: endpoint {
3225                                                         remote-endpoint = <&mdss_dsi0_in>;
3226                                                 };
3227                                         };
3228
3229                                         port@2 {
3230                                                 reg = <2>;
3231                                                 dpu_intf0_out: endpoint {
3232                                                         remote-endpoint = <&dp_in>;
3233                                                 };
3234                                         };
3235                                 };
3236
3237                                 mdp_opp_table: opp-table {
3238                                         compatible = "operating-points-v2";
3239
3240                                         opp-200000000 {
3241                                                 opp-hz = /bits/ 64 <200000000>;
3242                                                 required-opps = <&rpmhpd_opp_low_svs>;
3243                                         };
3244
3245                                         opp-300000000 {
3246                                                 opp-hz = /bits/ 64 <300000000>;
3247                                                 required-opps = <&rpmhpd_opp_svs>;
3248                                         };
3249
3250                                         opp-345000000 {
3251                                                 opp-hz = /bits/ 64 <345000000>;
3252                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3253                                         };
3254
3255                                         opp-460000000 {
3256                                                 opp-hz = /bits/ 64 <460000000>;
3257                                                 required-opps = <&rpmhpd_opp_nom>;
3258                                         };
3259                                 };
3260                         };
3261
3262                         mdss_dsi0: dsi@ae94000 {
3263                                 compatible = "qcom,sc7180-dsi-ctrl",
3264                                              "qcom,mdss-dsi-ctrl";
3265                                 reg = <0 0x0ae94000 0 0x400>;
3266                                 reg-names = "dsi_ctrl";
3267
3268                                 interrupt-parent = <&mdss>;
3269                                 interrupts = <4>;
3270
3271                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3272                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3273                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3274                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3275                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3276                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3277                                 clock-names = "byte",
3278                                               "byte_intf",
3279                                               "pixel",
3280                                               "core",
3281                                               "iface",
3282                                               "bus";
3283
3284                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3285                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3286
3287                                 operating-points-v2 = <&dsi_opp_table>;
3288                                 power-domains = <&rpmhpd SC7180_CX>;
3289
3290                                 phys = <&mdss_dsi0_phy>;
3291
3292                                 #address-cells = <1>;
3293                                 #size-cells = <0>;
3294
3295                                 status = "disabled";
3296
3297                                 ports {
3298                                         #address-cells = <1>;
3299                                         #size-cells = <0>;
3300
3301                                         port@0 {
3302                                                 reg = <0>;
3303                                                 mdss_dsi0_in: endpoint {
3304                                                         remote-endpoint = <&dpu_intf1_out>;
3305                                                 };
3306                                         };
3307
3308                                         port@1 {
3309                                                 reg = <1>;
3310                                                 mdss_dsi0_out: endpoint {
3311                                                 };
3312                                         };
3313                                 };
3314
3315                                 dsi_opp_table: opp-table {
3316                                         compatible = "operating-points-v2";
3317
3318                                         opp-187500000 {
3319                                                 opp-hz = /bits/ 64 <187500000>;
3320                                                 required-opps = <&rpmhpd_opp_low_svs>;
3321                                         };
3322
3323                                         opp-300000000 {
3324                                                 opp-hz = /bits/ 64 <300000000>;
3325                                                 required-opps = <&rpmhpd_opp_svs>;
3326                                         };
3327
3328                                         opp-358000000 {
3329                                                 opp-hz = /bits/ 64 <358000000>;
3330                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3331                                         };
3332                                 };
3333                         };
3334
3335                         mdss_dsi0_phy: phy@ae94400 {
3336                                 compatible = "qcom,dsi-phy-10nm";
3337                                 reg = <0 0x0ae94400 0 0x200>,
3338                                       <0 0x0ae94600 0 0x280>,
3339                                       <0 0x0ae94a00 0 0x1e0>;
3340                                 reg-names = "dsi_phy",
3341                                             "dsi_phy_lane",
3342                                             "dsi_pll";
3343
3344                                 #clock-cells = <1>;
3345                                 #phy-cells = <0>;
3346
3347                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3348                                          <&rpmhcc RPMH_CXO_CLK>;
3349                                 clock-names = "iface", "ref";
3350
3351                                 status = "disabled";
3352                         };
3353
3354                         mdss_dp: displayport-controller@ae90000 {
3355                                 compatible = "qcom,sc7180-dp";
3356                                 status = "disabled";
3357
3358                                 reg = <0 0x0ae90000 0 0x200>,
3359                                       <0 0x0ae90200 0 0x200>,
3360                                       <0 0x0ae90400 0 0xc00>,
3361                                       <0 0x0ae91000 0 0x400>,
3362                                       <0 0x0ae91400 0 0x400>;
3363
3364                                 interrupt-parent = <&mdss>;
3365                                 interrupts = <12>;
3366
3367                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3368                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3369                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3370                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3371                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3372                                 clock-names = "core_iface", "core_aux", "ctrl_link",
3373                                               "ctrl_link_iface", "stream_pixel";
3374                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3375                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3376                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3377                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3378                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3379                                 phy-names = "dp";
3380
3381                                 operating-points-v2 = <&dp_opp_table>;
3382                                 power-domains = <&rpmhpd SC7180_CX>;
3383
3384                                 #sound-dai-cells = <0>;
3385
3386                                 ports {
3387                                         #address-cells = <1>;
3388                                         #size-cells = <0>;
3389                                         port@0 {
3390                                                 reg = <0>;
3391                                                 dp_in: endpoint {
3392                                                         remote-endpoint = <&dpu_intf0_out>;
3393                                                 };
3394                                         };
3395
3396                                         port@1 {
3397                                                 reg = <1>;
3398                                                 mdss_dp_out: endpoint { };
3399                                         };
3400                                 };
3401
3402                                 dp_opp_table: opp-table {
3403                                         compatible = "operating-points-v2";
3404
3405                                         opp-160000000 {
3406                                                 opp-hz = /bits/ 64 <160000000>;
3407                                                 required-opps = <&rpmhpd_opp_low_svs>;
3408                                         };
3409
3410                                         opp-270000000 {
3411                                                 opp-hz = /bits/ 64 <270000000>;
3412                                                 required-opps = <&rpmhpd_opp_svs>;
3413                                         };
3414
3415                                         opp-540000000 {
3416                                                 opp-hz = /bits/ 64 <540000000>;
3417                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3418                                         };
3419
3420                                         opp-810000000 {
3421                                                 opp-hz = /bits/ 64 <810000000>;
3422                                                 required-opps = <&rpmhpd_opp_nom>;
3423                                         };
3424                                 };
3425                         };
3426                 };
3427
3428                 dispcc: clock-controller@af00000 {
3429                         compatible = "qcom,sc7180-dispcc";
3430                         reg = <0 0x0af00000 0 0x200000>;
3431                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3432                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3433                                  <&mdss_dsi0_phy 0>,
3434                                  <&mdss_dsi0_phy 1>,
3435                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3436                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3437                         clock-names = "bi_tcxo",
3438                                       "gcc_disp_gpll0_clk_src",
3439                                       "dsi0_phy_pll_out_byteclk",
3440                                       "dsi0_phy_pll_out_dsiclk",
3441                                       "dp_phy_pll_link_clk",
3442                                       "dp_phy_pll_vco_div_clk";
3443                         #clock-cells = <1>;
3444                         #reset-cells = <1>;
3445                         #power-domain-cells = <1>;
3446                 };
3447
3448                 pdc: interrupt-controller@b220000 {
3449                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3450                         reg = <0 0x0b220000 0 0x30000>;
3451                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3452                         #interrupt-cells = <2>;
3453                         interrupt-parent = <&intc>;
3454                         interrupt-controller;
3455                 };
3456
3457                 pdc_reset: reset-controller@b2e0000 {
3458                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3459                         reg = <0 0x0b2e0000 0 0x20000>;
3460                         #reset-cells = <1>;
3461                 };
3462
3463                 tsens0: thermal-sensor@c263000 {
3464                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3465                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3466                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3467                         #qcom,sensors = <15>;
3468                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3469                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3470                         interrupt-names = "uplow","critical";
3471                         #thermal-sensor-cells = <1>;
3472                 };
3473
3474                 tsens1: thermal-sensor@c265000 {
3475                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3476                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3477                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3478                         #qcom,sensors = <10>;
3479                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3480                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3481                         interrupt-names = "uplow","critical";
3482                         #thermal-sensor-cells = <1>;
3483                 };
3484
3485                 aoss_reset: reset-controller@c2a0000 {
3486                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3487                         reg = <0 0x0c2a0000 0 0x31000>;
3488                         #reset-cells = <1>;
3489                 };
3490
3491                 aoss_qmp: power-management@c300000 {
3492                         compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3493                         reg = <0 0x0c300000 0 0x400>;
3494                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3495                         mboxes = <&apss_shared 0>;
3496
3497                         #clock-cells = <0>;
3498                 };
3499
3500                 sram@c3f0000 {
3501                         compatible = "qcom,rpmh-stats";
3502                         reg = <0 0x0c3f0000 0 0x400>;
3503                 };
3504
3505                 spmi_bus: spmi@c440000 {
3506                         compatible = "qcom,spmi-pmic-arb";
3507                         reg = <0 0x0c440000 0 0x1100>,
3508                               <0 0x0c600000 0 0x2000000>,
3509                               <0 0x0e600000 0 0x100000>,
3510                               <0 0x0e700000 0 0xa0000>,
3511                               <0 0x0c40a000 0 0x26000>;
3512                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3513                         interrupt-names = "periph_irq";
3514                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3515                         qcom,ee = <0>;
3516                         qcom,channel = <0>;
3517                         #address-cells = <2>;
3518                         #size-cells = <0>;
3519                         interrupt-controller;
3520                         #interrupt-cells = <4>;
3521                 };
3522
3523                 sram@146aa000 {
3524                         compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3525                         reg = <0 0x146aa000 0 0x2000>;
3526
3527                         #address-cells = <1>;
3528                         #size-cells = <1>;
3529
3530                         ranges = <0 0 0x146aa000 0x2000>;
3531
3532                         pil-reloc@94c {
3533                                 compatible = "qcom,pil-reloc-info";
3534                                 reg = <0x94c 0xc8>;
3535                         };
3536                 };
3537
3538                 apps_smmu: iommu@15000000 {
3539                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3540                         reg = <0 0x15000000 0 0x100000>;
3541                         #iommu-cells = <2>;
3542                         #global-interrupts = <1>;
3543                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3544                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3545                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3546                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3547                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3548                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3549                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3550                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3551                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3552                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3553                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3554                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3555                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3556                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3557                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3558                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3559                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3560                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3561                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3562                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3563                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3564                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3565                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3566                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3567                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3568                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3569                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3570                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3571                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3572                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3573                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3574                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3575                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3576                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3577                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3578                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3579                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3580                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3581                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3582                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3583                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3584                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3585                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3586                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3587                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3588                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3589                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3590                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3591                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3592                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3593                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3594                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3595                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3596                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3597                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3598                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3599                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3600                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3601                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3602                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3603                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3604                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3605                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3606                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3607                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3608                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3609                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3610                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3611                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3612                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3613                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3614                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3615                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3616                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3617                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3621                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3624                 };
3625
3626                 intc: interrupt-controller@17a00000 {
3627                         compatible = "arm,gic-v3";
3628                         #address-cells = <2>;
3629                         #size-cells = <2>;
3630                         ranges;
3631                         #interrupt-cells = <3>;
3632                         interrupt-controller;
3633                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3634                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3635                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3636
3637                         msi-controller@17a40000 {
3638                                 compatible = "arm,gic-v3-its";
3639                                 msi-controller;
3640                                 #msi-cells = <1>;
3641                                 reg = <0 0x17a40000 0 0x20000>;
3642                                 status = "disabled";
3643                         };
3644                 };
3645
3646                 apss_shared: mailbox@17c00000 {
3647                         compatible = "qcom,sc7180-apss-shared",
3648                                      "qcom,sdm845-apss-shared";
3649                         reg = <0 0x17c00000 0 0x10000>;
3650                         #mbox-cells = <1>;
3651                 };
3652
3653                 watchdog@17c10000 {
3654                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3655                         reg = <0 0x17c10000 0 0x1000>;
3656                         clocks = <&sleep_clk>;
3657                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3658                 };
3659
3660                 timer@17c20000 {
3661                         #address-cells = <1>;
3662                         #size-cells = <1>;
3663                         ranges = <0 0 0 0x20000000>;
3664                         compatible = "arm,armv7-timer-mem";
3665                         reg = <0 0x17c20000 0 0x1000>;
3666
3667                         frame@17c21000 {
3668                                 frame-number = <0>;
3669                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3670                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3671                                 reg = <0x17c21000 0x1000>,
3672                                       <0x17c22000 0x1000>;
3673                         };
3674
3675                         frame@17c23000 {
3676                                 frame-number = <1>;
3677                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3678                                 reg = <0x17c23000 0x1000>;
3679                                 status = "disabled";
3680                         };
3681
3682                         frame@17c25000 {
3683                                 frame-number = <2>;
3684                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3685                                 reg = <0x17c25000 0x1000>;
3686                                 status = "disabled";
3687                         };
3688
3689                         frame@17c27000 {
3690                                 frame-number = <3>;
3691                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3692                                 reg = <0x17c27000 0x1000>;
3693                                 status = "disabled";
3694                         };
3695
3696                         frame@17c29000 {
3697                                 frame-number = <4>;
3698                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3699                                 reg = <0x17c29000 0x1000>;
3700                                 status = "disabled";
3701                         };
3702
3703                         frame@17c2b000 {
3704                                 frame-number = <5>;
3705                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3706                                 reg = <0x17c2b000 0x1000>;
3707                                 status = "disabled";
3708                         };
3709
3710                         frame@17c2d000 {
3711                                 frame-number = <6>;
3712                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3713                                 reg = <0x17c2d000 0x1000>;
3714                                 status = "disabled";
3715                         };
3716                 };
3717
3718                 apps_rsc: rsc@18200000 {
3719                         compatible = "qcom,rpmh-rsc";
3720                         reg = <0 0x18200000 0 0x10000>,
3721                               <0 0x18210000 0 0x10000>,
3722                               <0 0x18220000 0 0x10000>;
3723                         reg-names = "drv-0", "drv-1", "drv-2";
3724                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3725                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3726                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3727                         qcom,tcs-offset = <0xd00>;
3728                         qcom,drv-id = <2>;
3729                         qcom,tcs-config = <ACTIVE_TCS  2>,
3730                                           <SLEEP_TCS   3>,
3731                                           <WAKE_TCS    3>,
3732                                           <CONTROL_TCS 1>;
3733                         power-domains = <&CLUSTER_PD>;
3734
3735                         rpmhcc: clock-controller {
3736                                 compatible = "qcom,sc7180-rpmh-clk";
3737                                 clocks = <&xo_board>;
3738                                 clock-names = "xo";
3739                                 #clock-cells = <1>;
3740                         };
3741
3742                         rpmhpd: power-controller {
3743                                 compatible = "qcom,sc7180-rpmhpd";
3744                                 #power-domain-cells = <1>;
3745                                 operating-points-v2 = <&rpmhpd_opp_table>;
3746
3747                                 rpmhpd_opp_table: opp-table {
3748                                         compatible = "operating-points-v2";
3749
3750                                         rpmhpd_opp_ret: opp1 {
3751                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3752                                         };
3753
3754                                         rpmhpd_opp_min_svs: opp2 {
3755                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3756                                         };
3757
3758                                         rpmhpd_opp_low_svs: opp3 {
3759                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3760                                         };
3761
3762                                         rpmhpd_opp_svs: opp4 {
3763                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3764                                         };
3765
3766                                         rpmhpd_opp_svs_l1: opp5 {
3767                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3768                                         };
3769
3770                                         rpmhpd_opp_svs_l2: opp6 {
3771                                                 opp-level = <224>;
3772                                         };
3773
3774                                         rpmhpd_opp_nom: opp7 {
3775                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3776                                         };
3777
3778                                         rpmhpd_opp_nom_l1: opp8 {
3779                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3780                                         };
3781
3782                                         rpmhpd_opp_nom_l2: opp9 {
3783                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3784                                         };
3785
3786                                         rpmhpd_opp_turbo: opp10 {
3787                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3788                                         };
3789
3790                                         rpmhpd_opp_turbo_l1: opp11 {
3791                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3792                                         };
3793                                 };
3794                         };
3795
3796                         apps_bcm_voter: bcm-voter {
3797                                 compatible = "qcom,bcm-voter";
3798                         };
3799                 };
3800
3801                 osm_l3: interconnect@18321000 {
3802                         compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3803                         reg = <0 0x18321000 0 0x1400>;
3804
3805                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3806                         clock-names = "xo", "alternate";
3807
3808                         #interconnect-cells = <1>;
3809                 };
3810
3811                 cpufreq_hw: cpufreq@18323000 {
3812                         compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3813                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3814                         reg-names = "freq-domain0", "freq-domain1";
3815
3816                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3817                         clock-names = "xo", "alternate";
3818
3819                         #freq-domain-cells = <1>;
3820                         #clock-cells = <1>;
3821                 };
3822
3823                 wifi: wifi@18800000 {
3824                         compatible = "qcom,wcn3990-wifi";
3825                         reg = <0 0x18800000 0 0x800000>;
3826                         reg-names = "membase";
3827                         iommus = <&apps_smmu 0xc0 0x1>;
3828                         interrupts =
3829                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3830                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3831                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3832                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3833                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3834                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3835                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3836                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3837                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3838                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3839                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3840                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3841                         memory-region = <&wlan_mem>;
3842                         qcom,msa-fixed-perm;
3843                         status = "disabled";
3844                 };
3845
3846                 remoteproc_adsp: remoteproc@62400000 {
3847                         compatible = "qcom,sc7180-adsp-pas";
3848                         reg = <0 0x62400000 0 0x100>;
3849
3850                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3851                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3852                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3853                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3854                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3855                         interrupt-names = "wdog",
3856                                           "fatal",
3857                                           "ready",
3858                                           "handover",
3859                                           "stop-ack";
3860
3861                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3862                         clock-names = "xo";
3863
3864                         power-domains = <&rpmhpd SC7180_LCX>,
3865                                         <&rpmhpd SC7180_LMX>;
3866                         power-domain-names = "lcx", "lmx";
3867
3868                         qcom,qmp = <&aoss_qmp>;
3869                         qcom,smem-states = <&adsp_smp2p_out 0>;
3870                         qcom,smem-state-names = "stop";
3871
3872                         status = "disabled";
3873
3874                         glink-edge {
3875                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3876                                 label = "lpass";
3877                                 qcom,remote-pid = <2>;
3878                                 mboxes = <&apss_shared 8>;
3879
3880                                 apr {
3881                                         compatible = "qcom,apr-v2";
3882                                         qcom,glink-channels = "apr_audio_svc";
3883                                         qcom,domain = <APR_DOMAIN_ADSP>;
3884                                         #address-cells = <1>;
3885                                         #size-cells = <0>;
3886
3887                                         service@3 {
3888                                                 compatible = "qcom,q6core";
3889                                                 reg = <APR_SVC_ADSP_CORE>;
3890                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3891                                         };
3892
3893                                         q6afe: service@4 {
3894                                                 compatible = "qcom,q6afe";
3895                                                 reg = <APR_SVC_AFE>;
3896                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3897
3898                                                 q6afedai: dais {
3899                                                         compatible = "qcom,q6afe-dais";
3900                                                         #address-cells = <1>;
3901                                                         #size-cells = <0>;
3902                                                         #sound-dai-cells = <1>;
3903                                                 };
3904
3905                                                 q6afecc: clock-controller {
3906                                                         compatible = "qcom,q6afe-clocks";
3907                                                         #clock-cells = <2>;
3908                                                 };
3909                                         };
3910
3911                                         q6asm: service@7 {
3912                                                 compatible = "qcom,q6asm";
3913                                                 reg = <APR_SVC_ASM>;
3914                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3915
3916                                                 q6asmdai: dais {
3917                                                         compatible = "qcom,q6asm-dais";
3918                                                         #address-cells = <1>;
3919                                                         #size-cells = <0>;
3920                                                         #sound-dai-cells = <1>;
3921                                                         iommus = <&apps_smmu 0x1001 0x0>;
3922                                                 };
3923                                         };
3924
3925                                         q6adm: service@8 {
3926                                                 compatible = "qcom,q6adm";
3927                                                 reg = <APR_SVC_ADM>;
3928                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3929
3930                                                 q6routing: routing {
3931                                                         compatible = "qcom,q6adm-routing";
3932                                                         #sound-dai-cells = <0>;
3933                                                 };
3934                                         };
3935                                 };
3936
3937                                 fastrpc {
3938                                         compatible = "qcom,fastrpc";
3939                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3940                                         label = "adsp";
3941                                         #address-cells = <1>;
3942                                         #size-cells = <0>;
3943
3944                                         compute-cb@3 {
3945                                                 compatible = "qcom,fastrpc-compute-cb";
3946                                                 reg = <3>;
3947                                                 iommus = <&apps_smmu 0x1003 0x0>;
3948                                         };
3949
3950                                         compute-cb@4 {
3951                                                 compatible = "qcom,fastrpc-compute-cb";
3952                                                 reg = <4>;
3953                                                 iommus = <&apps_smmu 0x1004 0x0>;
3954                                         };
3955
3956                                         compute-cb@5 {
3957                                                 compatible = "qcom,fastrpc-compute-cb";
3958                                                 reg = <5>;
3959                                                 iommus = <&apps_smmu 0x1005 0x0>;
3960                                                 qcom,nsessions = <5>;
3961                                         };
3962                                 };
3963                         };
3964                 };
3965
3966                 lpasscc: clock-controller@62d00000 {
3967                         compatible = "qcom,sc7180-lpasscorecc";
3968                         reg = <0 0x62d00000 0 0x50000>,
3969                               <0 0x62780000 0 0x30000>;
3970                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3971                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3972                                  <&rpmhcc RPMH_CXO_CLK>;
3973                         clock-names = "iface", "bi_tcxo";
3974                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3975                         #clock-cells = <1>;
3976                         #power-domain-cells = <1>;
3977
3978                         status = "reserved"; /* Controlled by ADSP */
3979                 };
3980
3981                 lpass_cpu: lpass@62d87000 {
3982                         compatible = "qcom,sc7180-lpass-cpu";
3983
3984                         reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3985                         reg-names = "lpass-hdmiif", "lpass-lpaif";
3986
3987                         iommus = <&apps_smmu 0x1020 0>,
3988                                 <&apps_smmu 0x1021 0>,
3989                                 <&apps_smmu 0x1032 0>;
3990
3991                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3992                         required-opps = <&rpmhpd_opp_nom>;
3993
3994                         status = "disabled";
3995
3996                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3997                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3998                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3999                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4000                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4001                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4002
4003                         clock-names = "pcnoc-sway-clk", "audio-core",
4004                                         "mclk0", "pcnoc-mport-clk",
4005                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
4006
4007
4008                         #sound-dai-cells = <1>;
4009                         #address-cells = <1>;
4010                         #size-cells = <0>;
4011
4012                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4013                                         <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4014                         interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4015                 };
4016
4017                 lpass_hm: clock-controller@63000000 {
4018                         compatible = "qcom,sc7180-lpasshm";
4019                         reg = <0 0x63000000 0 0x28>;
4020                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4021                                  <&rpmhcc RPMH_CXO_CLK>;
4022                         clock-names = "iface", "bi_tcxo";
4023                         power-domains = <&rpmhpd SC7180_CX>;
4024
4025                         #clock-cells = <1>;
4026                         #power-domain-cells = <1>;
4027
4028                         status = "reserved"; /* Controlled by ADSP */
4029                 };
4030         };
4031
4032         thermal-zones {
4033                 cpu0_thermal: cpu0-thermal {
4034                         polling-delay-passive = <250>;
4035                         polling-delay = <0>;
4036
4037                         thermal-sensors = <&tsens0 1>;
4038                         sustainable-power = <1052>;
4039
4040                         trips {
4041                                 cpu0_alert0: trip-point0 {
4042                                         temperature = <90000>;
4043                                         hysteresis = <2000>;
4044                                         type = "passive";
4045                                 };
4046
4047                                 cpu0_alert1: trip-point1 {
4048                                         temperature = <95000>;
4049                                         hysteresis = <2000>;
4050                                         type = "passive";
4051                                 };
4052
4053                                 cpu0_crit: cpu-crit {
4054                                         temperature = <110000>;
4055                                         hysteresis = <1000>;
4056                                         type = "critical";
4057                                 };
4058                         };
4059
4060                         cooling-maps {
4061                                 map0 {
4062                                         trip = <&cpu0_alert0>;
4063                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4064                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4065                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4066                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4069                                 };
4070                                 map1 {
4071                                         trip = <&cpu0_alert1>;
4072                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4073                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4074                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4075                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4078                                 };
4079                         };
4080                 };
4081
4082                 cpu1_thermal: cpu1-thermal {
4083                         polling-delay-passive = <250>;
4084                         polling-delay = <0>;
4085
4086                         thermal-sensors = <&tsens0 2>;
4087                         sustainable-power = <1052>;
4088
4089                         trips {
4090                                 cpu1_alert0: trip-point0 {
4091                                         temperature = <90000>;
4092                                         hysteresis = <2000>;
4093                                         type = "passive";
4094                                 };
4095
4096                                 cpu1_alert1: trip-point1 {
4097                                         temperature = <95000>;
4098                                         hysteresis = <2000>;
4099                                         type = "passive";
4100                                 };
4101
4102                                 cpu1_crit: cpu-crit {
4103                                         temperature = <110000>;
4104                                         hysteresis = <1000>;
4105                                         type = "critical";
4106                                 };
4107                         };
4108
4109                         cooling-maps {
4110                                 map0 {
4111                                         trip = <&cpu1_alert0>;
4112                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4113                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4114                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4118                                 };
4119                                 map1 {
4120                                         trip = <&cpu1_alert1>;
4121                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4122                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4123                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4127                                 };
4128                         };
4129                 };
4130
4131                 cpu2_thermal: cpu2-thermal {
4132                         polling-delay-passive = <250>;
4133                         polling-delay = <0>;
4134
4135                         thermal-sensors = <&tsens0 3>;
4136                         sustainable-power = <1052>;
4137
4138                         trips {
4139                                 cpu2_alert0: trip-point0 {
4140                                         temperature = <90000>;
4141                                         hysteresis = <2000>;
4142                                         type = "passive";
4143                                 };
4144
4145                                 cpu2_alert1: trip-point1 {
4146                                         temperature = <95000>;
4147                                         hysteresis = <2000>;
4148                                         type = "passive";
4149                                 };
4150
4151                                 cpu2_crit: cpu-crit {
4152                                         temperature = <110000>;
4153                                         hysteresis = <1000>;
4154                                         type = "critical";
4155                                 };
4156                         };
4157
4158                         cooling-maps {
4159                                 map0 {
4160                                         trip = <&cpu2_alert0>;
4161                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4162                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4167                                 };
4168                                 map1 {
4169                                         trip = <&cpu2_alert1>;
4170                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4171                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4176                                 };
4177                         };
4178                 };
4179
4180                 cpu3_thermal: cpu3-thermal {
4181                         polling-delay-passive = <250>;
4182                         polling-delay = <0>;
4183
4184                         thermal-sensors = <&tsens0 4>;
4185                         sustainable-power = <1052>;
4186
4187                         trips {
4188                                 cpu3_alert0: trip-point0 {
4189                                         temperature = <90000>;
4190                                         hysteresis = <2000>;
4191                                         type = "passive";
4192                                 };
4193
4194                                 cpu3_alert1: trip-point1 {
4195                                         temperature = <95000>;
4196                                         hysteresis = <2000>;
4197                                         type = "passive";
4198                                 };
4199
4200                                 cpu3_crit: cpu-crit {
4201                                         temperature = <110000>;
4202                                         hysteresis = <1000>;
4203                                         type = "critical";
4204                                 };
4205                         };
4206
4207                         cooling-maps {
4208                                 map0 {
4209                                         trip = <&cpu3_alert0>;
4210                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216                                 };
4217                                 map1 {
4218                                         trip = <&cpu3_alert1>;
4219                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225                                 };
4226                         };
4227                 };
4228
4229                 cpu4_thermal: cpu4-thermal {
4230                         polling-delay-passive = <250>;
4231                         polling-delay = <0>;
4232
4233                         thermal-sensors = <&tsens0 5>;
4234                         sustainable-power = <1052>;
4235
4236                         trips {
4237                                 cpu4_alert0: trip-point0 {
4238                                         temperature = <90000>;
4239                                         hysteresis = <2000>;
4240                                         type = "passive";
4241                                 };
4242
4243                                 cpu4_alert1: trip-point1 {
4244                                         temperature = <95000>;
4245                                         hysteresis = <2000>;
4246                                         type = "passive";
4247                                 };
4248
4249                                 cpu4_crit: cpu-crit {
4250                                         temperature = <110000>;
4251                                         hysteresis = <1000>;
4252                                         type = "critical";
4253                                 };
4254                         };
4255
4256                         cooling-maps {
4257                                 map0 {
4258                                         trip = <&cpu4_alert0>;
4259                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4264                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4265                                 };
4266                                 map1 {
4267                                         trip = <&cpu4_alert1>;
4268                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4273                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4274                                 };
4275                         };
4276                 };
4277
4278                 cpu5_thermal: cpu5-thermal {
4279                         polling-delay-passive = <250>;
4280                         polling-delay = <0>;
4281
4282                         thermal-sensors = <&tsens0 6>;
4283                         sustainable-power = <1052>;
4284
4285                         trips {
4286                                 cpu5_alert0: trip-point0 {
4287                                         temperature = <90000>;
4288                                         hysteresis = <2000>;
4289                                         type = "passive";
4290                                 };
4291
4292                                 cpu5_alert1: trip-point1 {
4293                                         temperature = <95000>;
4294                                         hysteresis = <2000>;
4295                                         type = "passive";
4296                                 };
4297
4298                                 cpu5_crit: cpu-crit {
4299                                         temperature = <110000>;
4300                                         hysteresis = <1000>;
4301                                         type = "critical";
4302                                 };
4303                         };
4304
4305                         cooling-maps {
4306                                 map0 {
4307                                         trip = <&cpu5_alert0>;
4308                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4312                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4313                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4314                                 };
4315                                 map1 {
4316                                         trip = <&cpu5_alert1>;
4317                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4321                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4322                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4323                                 };
4324                         };
4325                 };
4326
4327                 cpu6_thermal: cpu6-thermal {
4328                         polling-delay-passive = <250>;
4329                         polling-delay = <0>;
4330
4331                         thermal-sensors = <&tsens0 9>;
4332                         sustainable-power = <1425>;
4333
4334                         trips {
4335                                 cpu6_alert0: trip-point0 {
4336                                         temperature = <90000>;
4337                                         hysteresis = <2000>;
4338                                         type = "passive";
4339                                 };
4340
4341                                 cpu6_alert1: trip-point1 {
4342                                         temperature = <95000>;
4343                                         hysteresis = <2000>;
4344                                         type = "passive";
4345                                 };
4346
4347                                 cpu6_crit: cpu-crit {
4348                                         temperature = <110000>;
4349                                         hysteresis = <1000>;
4350                                         type = "critical";
4351                                 };
4352                         };
4353
4354                         cooling-maps {
4355                                 map0 {
4356                                         trip = <&cpu6_alert0>;
4357                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4358                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4359                                 };
4360                                 map1 {
4361                                         trip = <&cpu6_alert1>;
4362                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4363                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4364                                 };
4365                         };
4366                 };
4367
4368                 cpu7_thermal: cpu7-thermal {
4369                         polling-delay-passive = <250>;
4370                         polling-delay = <0>;
4371
4372                         thermal-sensors = <&tsens0 10>;
4373                         sustainable-power = <1425>;
4374
4375                         trips {
4376                                 cpu7_alert0: trip-point0 {
4377                                         temperature = <90000>;
4378                                         hysteresis = <2000>;
4379                                         type = "passive";
4380                                 };
4381
4382                                 cpu7_alert1: trip-point1 {
4383                                         temperature = <95000>;
4384                                         hysteresis = <2000>;
4385                                         type = "passive";
4386                                 };
4387
4388                                 cpu7_crit: cpu-crit {
4389                                         temperature = <110000>;
4390                                         hysteresis = <1000>;
4391                                         type = "critical";
4392                                 };
4393                         };
4394
4395                         cooling-maps {
4396                                 map0 {
4397                                         trip = <&cpu7_alert0>;
4398                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4399                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4400                                 };
4401                                 map1 {
4402                                         trip = <&cpu7_alert1>;
4403                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4404                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4405                                 };
4406                         };
4407                 };
4408
4409                 cpu8_thermal: cpu8-thermal {
4410                         polling-delay-passive = <250>;
4411                         polling-delay = <0>;
4412
4413                         thermal-sensors = <&tsens0 11>;
4414                         sustainable-power = <1425>;
4415
4416                         trips {
4417                                 cpu8_alert0: trip-point0 {
4418                                         temperature = <90000>;
4419                                         hysteresis = <2000>;
4420                                         type = "passive";
4421                                 };
4422
4423                                 cpu8_alert1: trip-point1 {
4424                                         temperature = <95000>;
4425                                         hysteresis = <2000>;
4426                                         type = "passive";
4427                                 };
4428
4429                                 cpu8_crit: cpu-crit {
4430                                         temperature = <110000>;
4431                                         hysteresis = <1000>;
4432                                         type = "critical";
4433                                 };
4434                         };
4435
4436                         cooling-maps {
4437                                 map0 {
4438                                         trip = <&cpu8_alert0>;
4439                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441                                 };
4442                                 map1 {
4443                                         trip = <&cpu8_alert1>;
4444                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4445                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4446                                 };
4447                         };
4448                 };
4449
4450                 cpu9_thermal: cpu9-thermal {
4451                         polling-delay-passive = <250>;
4452                         polling-delay = <0>;
4453
4454                         thermal-sensors = <&tsens0 12>;
4455                         sustainable-power = <1425>;
4456
4457                         trips {
4458                                 cpu9_alert0: trip-point0 {
4459                                         temperature = <90000>;
4460                                         hysteresis = <2000>;
4461                                         type = "passive";
4462                                 };
4463
4464                                 cpu9_alert1: trip-point1 {
4465                                         temperature = <95000>;
4466                                         hysteresis = <2000>;
4467                                         type = "passive";
4468                                 };
4469
4470                                 cpu9_crit: cpu-crit {
4471                                         temperature = <110000>;
4472                                         hysteresis = <1000>;
4473                                         type = "critical";
4474                                 };
4475                         };
4476
4477                         cooling-maps {
4478                                 map0 {
4479                                         trip = <&cpu9_alert0>;
4480                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4481                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4482                                 };
4483                                 map1 {
4484                                         trip = <&cpu9_alert1>;
4485                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4486                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4487                                 };
4488                         };
4489                 };
4490
4491                 aoss0-thermal {
4492                         polling-delay-passive = <250>;
4493                         polling-delay = <0>;
4494
4495                         thermal-sensors = <&tsens0 0>;
4496
4497                         trips {
4498                                 aoss0_alert0: trip-point0 {
4499                                         temperature = <90000>;
4500                                         hysteresis = <2000>;
4501                                         type = "hot";
4502                                 };
4503
4504                                 aoss0_crit: aoss0-crit {
4505                                         temperature = <110000>;
4506                                         hysteresis = <2000>;
4507                                         type = "critical";
4508                                 };
4509                         };
4510                 };
4511
4512                 cpuss0-thermal {
4513                         polling-delay-passive = <250>;
4514                         polling-delay = <0>;
4515
4516                         thermal-sensors = <&tsens0 7>;
4517
4518                         trips {
4519                                 cpuss0_alert0: trip-point0 {
4520                                         temperature = <90000>;
4521                                         hysteresis = <2000>;
4522                                         type = "hot";
4523                                 };
4524                                 cpuss0_crit: cluster0-crit {
4525                                         temperature = <110000>;
4526                                         hysteresis = <2000>;
4527                                         type = "critical";
4528                                 };
4529                         };
4530                 };
4531
4532                 cpuss1-thermal {
4533                         polling-delay-passive = <250>;
4534                         polling-delay = <0>;
4535
4536                         thermal-sensors = <&tsens0 8>;
4537
4538                         trips {
4539                                 cpuss1_alert0: trip-point0 {
4540                                         temperature = <90000>;
4541                                         hysteresis = <2000>;
4542                                         type = "hot";
4543                                 };
4544                                 cpuss1_crit: cluster0-crit {
4545                                         temperature = <110000>;
4546                                         hysteresis = <2000>;
4547                                         type = "critical";
4548                                 };
4549                         };
4550                 };
4551
4552                 gpuss0-thermal {
4553                         polling-delay-passive = <250>;
4554                         polling-delay = <0>;
4555
4556                         thermal-sensors = <&tsens0 13>;
4557
4558                         trips {
4559                                 gpuss0_alert0: trip-point0 {
4560                                         temperature = <95000>;
4561                                         hysteresis = <2000>;
4562                                         type = "passive";
4563                                 };
4564
4565                                 gpuss0_crit: gpuss0-crit {
4566                                         temperature = <110000>;
4567                                         hysteresis = <2000>;
4568                                         type = "critical";
4569                                 };
4570                         };
4571
4572                         cooling-maps {
4573                                 map0 {
4574                                         trip = <&gpuss0_alert0>;
4575                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4576                                 };
4577                         };
4578                 };
4579
4580                 gpuss1-thermal {
4581                         polling-delay-passive = <250>;
4582                         polling-delay = <0>;
4583
4584                         thermal-sensors = <&tsens0 14>;
4585
4586                         trips {
4587                                 gpuss1_alert0: trip-point0 {
4588                                         temperature = <95000>;
4589                                         hysteresis = <2000>;
4590                                         type = "passive";
4591                                 };
4592
4593                                 gpuss1_crit: gpuss1-crit {
4594                                         temperature = <110000>;
4595                                         hysteresis = <2000>;
4596                                         type = "critical";
4597                                 };
4598                         };
4599
4600                         cooling-maps {
4601                                 map0 {
4602                                         trip = <&gpuss1_alert0>;
4603                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4604                                 };
4605                         };
4606                 };
4607
4608                 aoss1-thermal {
4609                         polling-delay-passive = <250>;
4610                         polling-delay = <0>;
4611
4612                         thermal-sensors = <&tsens1 0>;
4613
4614                         trips {
4615                                 aoss1_alert0: trip-point0 {
4616                                         temperature = <90000>;
4617                                         hysteresis = <2000>;
4618                                         type = "hot";
4619                                 };
4620
4621                                 aoss1_crit: aoss1-crit {
4622                                         temperature = <110000>;
4623                                         hysteresis = <2000>;
4624                                         type = "critical";
4625                                 };
4626                         };
4627                 };
4628
4629                 cwlan-thermal {
4630                         polling-delay-passive = <250>;
4631                         polling-delay = <0>;
4632
4633                         thermal-sensors = <&tsens1 1>;
4634
4635                         trips {
4636                                 cwlan_alert0: trip-point0 {
4637                                         temperature = <90000>;
4638                                         hysteresis = <2000>;
4639                                         type = "hot";
4640                                 };
4641
4642                                 cwlan_crit: cwlan-crit {
4643                                         temperature = <110000>;
4644                                         hysteresis = <2000>;
4645                                         type = "critical";
4646                                 };
4647                         };
4648                 };
4649
4650                 audio-thermal {
4651                         polling-delay-passive = <250>;
4652                         polling-delay = <0>;
4653
4654                         thermal-sensors = <&tsens1 2>;
4655
4656                         trips {
4657                                 audio_alert0: trip-point0 {
4658                                         temperature = <90000>;
4659                                         hysteresis = <2000>;
4660                                         type = "hot";
4661                                 };
4662
4663                                 audio_crit: audio-crit {
4664                                         temperature = <110000>;
4665                                         hysteresis = <2000>;
4666                                         type = "critical";
4667                                 };
4668                         };
4669                 };
4670
4671                 ddr-thermal {
4672                         polling-delay-passive = <250>;
4673                         polling-delay = <0>;
4674
4675                         thermal-sensors = <&tsens1 3>;
4676
4677                         trips {
4678                                 ddr_alert0: trip-point0 {
4679                                         temperature = <90000>;
4680                                         hysteresis = <2000>;
4681                                         type = "hot";
4682                                 };
4683
4684                                 ddr_crit: ddr-crit {
4685                                         temperature = <110000>;
4686                                         hysteresis = <2000>;
4687                                         type = "critical";
4688                                 };
4689                         };
4690                 };
4691
4692                 q6-hvx-thermal {
4693                         polling-delay-passive = <250>;
4694                         polling-delay = <0>;
4695
4696                         thermal-sensors = <&tsens1 4>;
4697
4698                         trips {
4699                                 q6_hvx_alert0: trip-point0 {
4700                                         temperature = <90000>;
4701                                         hysteresis = <2000>;
4702                                         type = "hot";
4703                                 };
4704
4705                                 q6_hvx_crit: q6-hvx-crit {
4706                                         temperature = <110000>;
4707                                         hysteresis = <2000>;
4708                                         type = "critical";
4709                                 };
4710                         };
4711                 };
4712
4713                 camera-thermal {
4714                         polling-delay-passive = <250>;
4715                         polling-delay = <0>;
4716
4717                         thermal-sensors = <&tsens1 5>;
4718
4719                         trips {
4720                                 camera_alert0: trip-point0 {
4721                                         temperature = <90000>;
4722                                         hysteresis = <2000>;
4723                                         type = "hot";
4724                                 };
4725
4726                                 camera_crit: camera-crit {
4727                                         temperature = <110000>;
4728                                         hysteresis = <2000>;
4729                                         type = "critical";
4730                                 };
4731                         };
4732                 };
4733
4734                 mdm-core-thermal {
4735                         polling-delay-passive = <250>;
4736                         polling-delay = <0>;
4737
4738                         thermal-sensors = <&tsens1 6>;
4739
4740                         trips {
4741                                 mdm_alert0: trip-point0 {
4742                                         temperature = <90000>;
4743                                         hysteresis = <2000>;
4744                                         type = "hot";
4745                                 };
4746
4747                                 mdm_crit: mdm-crit {
4748                                         temperature = <110000>;
4749                                         hysteresis = <2000>;
4750                                         type = "critical";
4751                                 };
4752                         };
4753                 };
4754
4755                 mdm-dsp-thermal {
4756                         polling-delay-passive = <250>;
4757                         polling-delay = <0>;
4758
4759                         thermal-sensors = <&tsens1 7>;
4760
4761                         trips {
4762                                 mdm_dsp_alert0: trip-point0 {
4763                                         temperature = <90000>;
4764                                         hysteresis = <2000>;
4765                                         type = "hot";
4766                                 };
4767
4768                                 mdm_dsp_crit: mdm-dsp-crit {
4769                                         temperature = <110000>;
4770                                         hysteresis = <2000>;
4771                                         type = "critical";
4772                                 };
4773                         };
4774                 };
4775
4776                 npu-thermal {
4777                         polling-delay-passive = <250>;
4778                         polling-delay = <0>;
4779
4780                         thermal-sensors = <&tsens1 8>;
4781
4782                         trips {
4783                                 npu_alert0: trip-point0 {
4784                                         temperature = <90000>;
4785                                         hysteresis = <2000>;
4786                                         type = "hot";
4787                                 };
4788
4789                                 npu_crit: npu-crit {
4790                                         temperature = <110000>;
4791                                         hysteresis = <2000>;
4792                                         type = "critical";
4793                                 };
4794                         };
4795                 };
4796
4797                 video-thermal {
4798                         polling-delay-passive = <250>;
4799                         polling-delay = <0>;
4800
4801                         thermal-sensors = <&tsens1 9>;
4802
4803                         trips {
4804                                 video_alert0: trip-point0 {
4805                                         temperature = <90000>;
4806                                         hysteresis = <2000>;
4807                                         type = "hot";
4808                                 };
4809
4810                                 video_crit: video-crit {
4811                                         temperature = <110000>;
4812                                         hysteresis = <2000>;
4813                                         type = "critical";
4814                                 };
4815                         };
4816                 };
4817         };
4818
4819         timer {
4820                 compatible = "arm,armv8-timer";
4821                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4822                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4823                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4824                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4825         };
4826 };