arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 ipa_fw_mem: memory@8b700000 {
 114                         reg = <0 0x8b700000 0 0x10000>;
 115                         no-map;
 116                 };
 117
 118                 rmtfs_mem: memory@94600000 {
 119                         compatible = "qcom,rmtfs-mem";
 120                         reg = <0x0 0x94600000 0x0 0x200000>;
 121                         no-map;
 122
 123                         qcom,client-id = <1>;
 124                         qcom,vmid = <15>;
 125                 };
 126         };
 127
 128         cpus {
 129                 #address-cells = <2>;
 130                 #size-cells = <0>;
 131
 132                 CPU0: cpu@0 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo468";
 135                         reg = <0x0 0x0>;
 136                         enable-method = "psci";
 137                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 138                                            &LITTLE_CPU_SLEEP_1
 139                                            &CLUSTER_SLEEP_0>;
 140                         capacity-dmips-mhz = <1024>;
 141                         dynamic-power-coefficient = <100>;
 142                         operating-points-v2 = <&cpu0_opp_table>;
 143                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 144                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 145                         next-level-cache = <&L2_0>;
 146                         #cooling-cells = <2>;
 147                         qcom,freq-domain = <&cpufreq_hw 0>;
 148                         L2_0: l2-cache {
 149                                 compatible = "cache";
 150                                 next-level-cache = <&L3_0>;
 151                                 L3_0: l3-cache {
 152                                         compatible = "cache";
 153                                 };
 154                         };
 155                 };
 156
 157                 CPU1: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "qcom,kryo468";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 163                                            &LITTLE_CPU_SLEEP_1
 164                                            &CLUSTER_SLEEP_0>;
 165                         capacity-dmips-mhz = <1024>;
 166                         dynamic-power-coefficient = <100>;
 167                         next-level-cache = <&L2_100>;
 168                         operating-points-v2 = <&cpu0_opp_table>;
 169                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 170                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 171                         #cooling-cells = <2>;
 172                         qcom,freq-domain = <&cpufreq_hw 0>;
 173                         L2_100: l2-cache {
 174                                 compatible = "cache";
 175                                 next-level-cache = <&L3_0>;
 176                         };
 177                 };
 178
 179                 CPU2: cpu@200 {
 180                         device_type = "cpu";
 181                         compatible = "qcom,kryo468";
 182                         reg = <0x0 0x200>;
 183                         enable-method = "psci";
 184                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 185                                            &LITTLE_CPU_SLEEP_1
 186                                            &CLUSTER_SLEEP_0>;
 187                         capacity-dmips-mhz = <1024>;
 188                         dynamic-power-coefficient = <100>;
 189                         next-level-cache = <&L2_200>;
 190                         operating-points-v2 = <&cpu0_opp_table>;
 191                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 192                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 193                         #cooling-cells = <2>;
 194                         qcom,freq-domain = <&cpufreq_hw 0>;
 195                         L2_200: l2-cache {
 196                                 compatible = "cache";
 197                                 next-level-cache = <&L3_0>;
 198                         };
 199                 };
 200
 201                 CPU3: cpu@300 {
 202                         device_type = "cpu";
 203                         compatible = "qcom,kryo468";
 204                         reg = <0x0 0x300>;
 205                         enable-method = "psci";
 206                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 207                                            &LITTLE_CPU_SLEEP_1
 208                                            &CLUSTER_SLEEP_0>;
 209                         capacity-dmips-mhz = <1024>;
 210                         dynamic-power-coefficient = <100>;
 211                         next-level-cache = <&L2_300>;
 212                         operating-points-v2 = <&cpu0_opp_table>;
 213                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 214                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 215                         #cooling-cells = <2>;
 216                         qcom,freq-domain = <&cpufreq_hw 0>;
 217                         L2_300: l2-cache {
 218                                 compatible = "cache";
 219                                 next-level-cache = <&L3_0>;
 220                         };
 221                 };
 222
 223                 CPU4: cpu@400 {
 224                         device_type = "cpu";
 225                         compatible = "qcom,kryo468";
 226                         reg = <0x0 0x400>;
 227                         enable-method = "psci";
 228                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 229                                            &LITTLE_CPU_SLEEP_1
 230                                            &CLUSTER_SLEEP_0>;
 231                         capacity-dmips-mhz = <1024>;
 232                         dynamic-power-coefficient = <100>;
 233                         next-level-cache = <&L2_400>;
 234                         operating-points-v2 = <&cpu0_opp_table>;
 235                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 236                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 237                         #cooling-cells = <2>;
 238                         qcom,freq-domain = <&cpufreq_hw 0>;
 239                         L2_400: l2-cache {
 240                                 compatible = "cache";
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 CPU5: cpu@500 {
 246                         device_type = "cpu";
 247                         compatible = "qcom,kryo468";
 248                         reg = <0x0 0x500>;
 249                         enable-method = "psci";
 250                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 251                                            &LITTLE_CPU_SLEEP_1
 252                                            &CLUSTER_SLEEP_0>;
 253                         capacity-dmips-mhz = <1024>;
 254                         dynamic-power-coefficient = <100>;
 255                         next-level-cache = <&L2_500>;
 256                         operating-points-v2 = <&cpu0_opp_table>;
 257                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 258                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 259                         #cooling-cells = <2>;
 260                         qcom,freq-domain = <&cpufreq_hw 0>;
 261                         L2_500: l2-cache {
 262                                 compatible = "cache";
 263                                 next-level-cache = <&L3_0>;
 264                         };
 265                 };
 266
 267                 CPU6: cpu@600 {
 268                         device_type = "cpu";
 269                         compatible = "qcom,kryo468";
 270                         reg = <0x0 0x600>;
 271                         enable-method = "psci";
 272                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 273                                            &BIG_CPU_SLEEP_1
 274                                            &CLUSTER_SLEEP_0>;
 275                         capacity-dmips-mhz = <1740>;
 276                         dynamic-power-coefficient = <405>;
 277                         next-level-cache = <&L2_600>;
 278                         operating-points-v2 = <&cpu6_opp_table>;
 279                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 280                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 281                         #cooling-cells = <2>;
 282                         qcom,freq-domain = <&cpufreq_hw 1>;
 283                         L2_600: l2-cache {
 284                                 compatible = "cache";
 285                                 next-level-cache = <&L3_0>;
 286                         };
 287                 };
 288
 289                 CPU7: cpu@700 {
 290                         device_type = "cpu";
 291                         compatible = "qcom,kryo468";
 292                         reg = <0x0 0x700>;
 293                         enable-method = "psci";
 294                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 295                                            &BIG_CPU_SLEEP_1
 296                                            &CLUSTER_SLEEP_0>;
 297                         capacity-dmips-mhz = <1740>;
 298                         dynamic-power-coefficient = <405>;
 299                         next-level-cache = <&L2_700>;
 300                         operating-points-v2 = <&cpu6_opp_table>;
 301                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 302                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 303                         #cooling-cells = <2>;
 304                         qcom,freq-domain = <&cpufreq_hw 1>;
 305                         L2_700: l2-cache {
 306                                 compatible = "cache";
 307                                 next-level-cache = <&L3_0>;
 308                         };
 309                 };
 310
 311                 cpu-map {
 312                         cluster0 {
 313                                 core0 {
 314                                         cpu = <&CPU0>;
 315                                 };
 316
 317                                 core1 {
 318                                         cpu = <&CPU1>;
 319                                 };
 320
 321                                 core2 {
 322                                         cpu = <&CPU2>;
 323                                 };
 324
 325                                 core3 {
 326                                         cpu = <&CPU3>;
 327                                 };
 328
 329                                 core4 {
 330                                         cpu = <&CPU4>;
 331                                 };
 332
 333                                 core5 {
 334                                         cpu = <&CPU5>;
 335                                 };
 336
 337                                 core6 {
 338                                         cpu = <&CPU6>;
 339                                 };
 340
 341                                 core7 {
 342                                         cpu = <&CPU7>;
 343                                 };
 344                         };
 345                 };
 346
 347                 idle-states {
 348                         entry-method = "psci";
 349
 350                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 351                                 compatible = "arm,idle-state";
 352                                 idle-state-name = "little-power-down";
 353                                 arm,psci-suspend-param = <0x40000003>;
 354                                 entry-latency-us = <549>;
 355                                 exit-latency-us = <901>;
 356                                 min-residency-us = <1774>;
 357                                 local-timer-stop;
 358                         };
 359
 360                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 361                                 compatible = "arm,idle-state";
 362                                 idle-state-name = "little-rail-power-down";
 363                                 arm,psci-suspend-param = <0x40000004>;
 364                                 entry-latency-us = <702>;
 365                                 exit-latency-us = <915>;
 366                                 min-residency-us = <4001>;
 367                                 local-timer-stop;
 368                         };
 369
 370                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 371                                 compatible = "arm,idle-state";
 372                                 idle-state-name = "big-power-down";
 373                                 arm,psci-suspend-param = <0x40000003>;
 374                                 entry-latency-us = <523>;
 375                                 exit-latency-us = <1244>;
 376                                 min-residency-us = <2207>;
 377                                 local-timer-stop;
 378                         };
 379
 380                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 381                                 compatible = "arm,idle-state";
 382                                 idle-state-name = "big-rail-power-down";
 383                                 arm,psci-suspend-param = <0x40000004>;
 384                                 entry-latency-us = <526>;
 385                                 exit-latency-us = <1854>;
 386                                 min-residency-us = <5555>;
 387                                 local-timer-stop;
 388                         };
 389
 390                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 391                                 compatible = "arm,idle-state";
 392                                 idle-state-name = "cluster-power-down";
 393                                 arm,psci-suspend-param = <0x40003444>;
 394                                 entry-latency-us = <3263>;
 395                                 exit-latency-us = <6562>;
 396                                 min-residency-us = <9926>;
 397                                 local-timer-stop;
 398                         };
 399                 };
 400         };
 401
 402         cpu0_opp_table: cpu0_opp_table {
 403                 compatible = "operating-points-v2";
 404                 opp-shared;
 405
 406                 cpu0_opp1: opp-300000000 {
 407                         opp-hz = /bits/ 64 <300000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp2: opp-576000000 {
 412                         opp-hz = /bits/ 64 <576000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp3: opp-768000000 {
 417                         opp-hz = /bits/ 64 <768000000>;
 418                         opp-peak-kBps = <1200000 4800000>;
 419                 };
 420
 421                 cpu0_opp4: opp-1017600000 {
 422                         opp-hz = /bits/ 64 <1017600000>;
 423                         opp-peak-kBps = <1804000 8908800>;
 424                 };
 425
 426                 cpu0_opp5: opp-1248000000 {
 427                         opp-hz = /bits/ 64 <1248000000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp6: opp-1324800000 {
 432                         opp-hz = /bits/ 64 <1324800000>;
 433                         opp-peak-kBps = <2188000 12902400>;
 434                 };
 435
 436                 cpu0_opp7: opp-1516800000 {
 437                         opp-hz = /bits/ 64 <1516800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp8: opp-1612800000 {
 442                         opp-hz = /bits/ 64 <1612800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp9: opp-1708800000 {
 447                         opp-hz = /bits/ 64 <1708800000>;
 448                         opp-peak-kBps = <3072000 15052800>;
 449                 };
 450
 451                 cpu0_opp10: opp-1804800000 {
 452                         opp-hz = /bits/ 64 <1804800000>;
 453                         opp-peak-kBps = <4068000 22425600>;
 454                 };
 455         };
 456
 457         cpu6_opp_table: cpu6_opp_table {
 458                 compatible = "operating-points-v2";
 459                 opp-shared;
 460
 461                 cpu6_opp1: opp-300000000 {
 462                         opp-hz = /bits/ 64 <300000000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp2: opp-652800000 {
 467                         opp-hz = /bits/ 64 <652800000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp3: opp-825600000 {
 472                         opp-hz = /bits/ 64 <825600000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp4: opp-979200000 {
 477                         opp-hz = /bits/ 64 <979200000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp5: opp-1113600000 {
 482                         opp-hz = /bits/ 64 <1113600000>;
 483                         opp-peak-kBps = <2188000 8908800>;
 484                 };
 485
 486                 cpu6_opp6: opp-1267200000 {
 487                         opp-hz = /bits/ 64 <1267200000>;
 488                         opp-peak-kBps = <4068000 12902400>;
 489                 };
 490
 491                 cpu6_opp7: opp-1555200000 {
 492                         opp-hz = /bits/ 64 <1555200000>;
 493                         opp-peak-kBps = <4068000 15052800>;
 494                 };
 495
 496                 cpu6_opp8: opp-1708800000 {
 497                         opp-hz = /bits/ 64 <1708800000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp9: opp-1843200000 {
 502                         opp-hz = /bits/ 64 <1843200000>;
 503                         opp-peak-kBps = <6220000 19353600>;
 504                 };
 505
 506                 cpu6_opp10: opp-1900800000 {
 507                         opp-hz = /bits/ 64 <1900800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp11: opp-1996800000 {
 512                         opp-hz = /bits/ 64 <1996800000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp12: opp-2112000000 {
 517                         opp-hz = /bits/ 64 <2112000000>;
 518                         opp-peak-kBps = <6220000 22425600>;
 519                 };
 520
 521                 cpu6_opp13: opp-2208000000 {
 522                         opp-hz = /bits/ 64 <2208000000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp14: opp-2323200000 {
 527                         opp-hz = /bits/ 64 <2323200000>;
 528                         opp-peak-kBps = <7216000 22425600>;
 529                 };
 530
 531                 cpu6_opp15: opp-2400000000 {
 532                         opp-hz = /bits/ 64 <2400000000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535
 536                 cpu6_opp16: opp-2553600000 {
 537                         opp-hz = /bits/ 64 <2553600000>;
 538                         opp-peak-kBps = <8532000 23347200>;
 539                 };
 540         };
 541
 542         memory@80000000 {
 543                 device_type = "memory";
 544                 /* We expect the bootloader to fill in the size */
 545                 reg = <0 0x80000000 0 0>;
 546         };
 547
 548         pmu {
 549                 compatible = "arm,armv8-pmuv3";
 550                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 551         };
 552
 553         firmware {
 554                 scm {
 555                         compatible = "qcom,scm-sc7180", "qcom,scm";
 556                 };
 557         };
 558
 559         tcsr_mutex: hwlock {
 560                 compatible = "qcom,tcsr-mutex";
 561                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 562                 #hwlock-cells = <1>;
 563         };
 564
 565         smem {
 566                 compatible = "qcom,smem";
 567                 memory-region = <&smem_mem>;
 568                 hwlocks = <&tcsr_mutex 3>;
 569         };
 570
 571         smp2p-cdsp {
 572                 compatible = "qcom,smp2p";
 573                 qcom,smem = <94>, <432>;
 574
 575                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 576
 577                 mboxes = <&apss_shared 6>;
 578
 579                 qcom,local-pid = <0>;
 580                 qcom,remote-pid = <5>;
 581
 582                 cdsp_smp2p_out: master-kernel {
 583                         qcom,entry-name = "master-kernel";
 584                         #qcom,smem-state-cells = <1>;
 585                 };
 586
 587                 cdsp_smp2p_in: slave-kernel {
 588                         qcom,entry-name = "slave-kernel";
 589
 590                         interrupt-controller;
 591                         #interrupt-cells = <2>;
 592                 };
 593         };
 594
 595         smp2p-lpass {
 596                 compatible = "qcom,smp2p";
 597                 qcom,smem = <443>, <429>;
 598
 599                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 600
 601                 mboxes = <&apss_shared 10>;
 602
 603                 qcom,local-pid = <0>;
 604                 qcom,remote-pid = <2>;
 605
 606                 adsp_smp2p_out: master-kernel {
 607                         qcom,entry-name = "master-kernel";
 608                         #qcom,smem-state-cells = <1>;
 609                 };
 610
 611                 adsp_smp2p_in: slave-kernel {
 612                         qcom,entry-name = "slave-kernel";
 613
 614                         interrupt-controller;
 615                         #interrupt-cells = <2>;
 616                 };
 617         };
 618
 619         smp2p-mpss {
 620                 compatible = "qcom,smp2p";
 621                 qcom,smem = <435>, <428>;
 622                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 623                 mboxes = <&apss_shared 14>;
 624                 qcom,local-pid = <0>;
 625                 qcom,remote-pid = <1>;
 626
 627                 modem_smp2p_out: master-kernel {
 628                         qcom,entry-name = "master-kernel";
 629                         #qcom,smem-state-cells = <1>;
 630                 };
 631
 632                 modem_smp2p_in: slave-kernel {
 633                         qcom,entry-name = "slave-kernel";
 634                         interrupt-controller;
 635                         #interrupt-cells = <2>;
 636                 };
 637
 638                 ipa_smp2p_out: ipa-ap-to-modem {
 639                         qcom,entry-name = "ipa";
 640                         #qcom,smem-state-cells = <1>;
 641                 };
 642
 643                 ipa_smp2p_in: ipa-modem-to-ap {
 644                         qcom,entry-name = "ipa";
 645                         interrupt-controller;
 646                         #interrupt-cells = <2>;
 647                 };
 648         };
 649
 650         psci {
 651                 compatible = "arm,psci-1.0";
 652                 method = "smc";
 653         };
 654
 655         soc: soc@0 {
 656                 #address-cells = <2>;
 657                 #size-cells = <2>;
 658                 ranges = <0 0 0 0 0x10 0>;
 659                 dma-ranges = <0 0 0 0 0x10 0>;
 660                 compatible = "simple-bus";
 661
 662                 gcc: clock-controller@100000 {
 663                         compatible = "qcom,gcc-sc7180";
 664                         reg = <0 0x00100000 0 0x1f0000>;
 665                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 666                                  <&rpmhcc RPMH_CXO_CLK_A>,
 667                                  <&sleep_clk>;
 668                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 669                         #clock-cells = <1>;
 670                         #reset-cells = <1>;
 671                         #power-domain-cells = <1>;
 672                 };
 673
 674                 qfprom: efuse@784000 {
 675                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 676                         reg = <0 0x00784000 0 0x7a0>,
 677                               <0 0x00780000 0 0x7a0>,
 678                               <0 0x00782000 0 0x100>,
 679                               <0 0x00786000 0 0x1fff>;
 680
 681                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 682                         clock-names = "core";
 683                         #address-cells = <1>;
 684                         #size-cells = <1>;
 685
 686                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 687                                 reg = <0x25b 0x1>;
 688                                 bits = <1 3>;
 689                         };
 690
 691                         gpu_speed_bin: gpu_speed_bin@1d2 {
 692                                 reg = <0x1d2 0x2>;
 693                                 bits = <5 8>;
 694                         };
 695                 };
 696
 697                 sdhc_1: sdhci@7c4000 {
 698                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 699                         reg = <0 0x7c4000 0 0x1000>,
 700                                 <0 0x07c5000 0 0x1000>;
 701                         reg-names = "hc", "cqhci";
 702
 703                         iommus = <&apps_smmu 0x60 0x0>;
 704                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 705                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 706                         interrupt-names = "hc_irq", "pwr_irq";
 707
 708                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 709                                  <&gcc GCC_SDCC1_AHB_CLK>,
 710                                  <&rpmhcc RPMH_CXO_CLK>;
 711                         clock-names = "core", "iface", "xo";
 712                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 713                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 714                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 715                         power-domains = <&rpmhpd SC7180_CX>;
 716                         operating-points-v2 = <&sdhc1_opp_table>;
 717
 718                         bus-width = <8>;
 719                         non-removable;
 720                         supports-cqe;
 721
 722                         mmc-ddr-1_8v;
 723                         mmc-hs200-1_8v;
 724                         mmc-hs400-1_8v;
 725                         mmc-hs400-enhanced-strobe;
 726
 727                         status = "disabled";
 728
 729                         sdhc1_opp_table: sdhc1-opp-table {
 730                                 compatible = "operating-points-v2";
 731
 732                                 opp-100000000 {
 733                                         opp-hz = /bits/ 64 <100000000>;
 734                                         required-opps = <&rpmhpd_opp_low_svs>;
 735                                         opp-peak-kBps = <1800000 600000>;
 736                                         opp-avg-kBps = <100000 0>;
 737                                 };
 738
 739                                 opp-384000000 {
 740                                         opp-hz = /bits/ 64 <384000000>;
 741                                         required-opps = <&rpmhpd_opp_nom>;
 742                                         opp-peak-kBps = <5400000 1600000>;
 743                                         opp-avg-kBps = <390000 0>;
 744                                 };
 745                         };
 746                 };
 747
 748                 qup_opp_table: qup-opp-table {
 749                         compatible = "operating-points-v2";
 750
 751                         opp-75000000 {
 752                                 opp-hz = /bits/ 64 <75000000>;
 753                                 required-opps = <&rpmhpd_opp_low_svs>;
 754                         };
 755
 756                         opp-100000000 {
 757                                 opp-hz = /bits/ 64 <100000000>;
 758                                 required-opps = <&rpmhpd_opp_svs>;
 759                         };
 760
 761                         opp-128000000 {
 762                                 opp-hz = /bits/ 64 <128000000>;
 763                                 required-opps = <&rpmhpd_opp_nom>;
 764                         };
 765                 };
 766
 767                 qupv3_id_0: geniqup@8c0000 {
 768                         compatible = "qcom,geni-se-qup";
 769                         reg = <0 0x008c0000 0 0x6000>;
 770                         clock-names = "m-ahb", "s-ahb";
 771                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 772                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 773                         #address-cells = <2>;
 774                         #size-cells = <2>;
 775                         ranges;
 776                         iommus = <&apps_smmu 0x43 0x0>;
 777                         status = "disabled";
 778
 779                         i2c0: i2c@880000 {
 780                                 compatible = "qcom,geni-i2c";
 781                                 reg = <0 0x00880000 0 0x4000>;
 782                                 clock-names = "se";
 783                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 784                                 pinctrl-names = "default";
 785                                 pinctrl-0 = <&qup_i2c0_default>;
 786                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 787                                 #address-cells = <1>;
 788                                 #size-cells = <0>;
 789                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 790                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 791                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 792                                 interconnect-names = "qup-core", "qup-config",
 793                                                         "qup-memory";
 794                                 status = "disabled";
 795                         };
 796
 797                         spi0: spi@880000 {
 798                                 compatible = "qcom,geni-spi";
 799                                 reg = <0 0x00880000 0 0x4000>;
 800                                 clock-names = "se";
 801                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 802                                 pinctrl-names = "default";
 803                                 pinctrl-0 = <&qup_spi0_default>;
 804                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 805                                 #address-cells = <1>;
 806                                 #size-cells = <0>;
 807                                 power-domains = <&rpmhpd SC7180_CX>;
 808                                 operating-points-v2 = <&qup_opp_table>;
 809                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 810                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 811                                 interconnect-names = "qup-core", "qup-config";
 812                                 status = "disabled";
 813                         };
 814
 815                         uart0: serial@880000 {
 816                                 compatible = "qcom,geni-uart";
 817                                 reg = <0 0x00880000 0 0x4000>;
 818                                 clock-names = "se";
 819                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 820                                 pinctrl-names = "default";
 821                                 pinctrl-0 = <&qup_uart0_default>;
 822                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 823                                 power-domains = <&rpmhpd SC7180_CX>;
 824                                 operating-points-v2 = <&qup_opp_table>;
 825                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 826                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 827                                 interconnect-names = "qup-core", "qup-config";
 828                                 status = "disabled";
 829                         };
 830
 831                         i2c1: i2c@884000 {
 832                                 compatible = "qcom,geni-i2c";
 833                                 reg = <0 0x00884000 0 0x4000>;
 834                                 clock-names = "se";
 835                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 836                                 pinctrl-names = "default";
 837                                 pinctrl-0 = <&qup_i2c1_default>;
 838                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 842                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 843                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 844                                 interconnect-names = "qup-core", "qup-config",
 845                                                         "qup-memory";
 846                                 status = "disabled";
 847                         };
 848
 849                         spi1: spi@884000 {
 850                                 compatible = "qcom,geni-spi";
 851                                 reg = <0 0x00884000 0 0x4000>;
 852                                 clock-names = "se";
 853                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 854                                 pinctrl-names = "default";
 855                                 pinctrl-0 = <&qup_spi1_default>;
 856                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 857                                 #address-cells = <1>;
 858                                 #size-cells = <0>;
 859                                 power-domains = <&rpmhpd SC7180_CX>;
 860                                 operating-points-v2 = <&qup_opp_table>;
 861                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 862                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 863                                 interconnect-names = "qup-core", "qup-config";
 864                                 status = "disabled";
 865                         };
 866
 867                         uart1: serial@884000 {
 868                                 compatible = "qcom,geni-uart";
 869                                 reg = <0 0x00884000 0 0x4000>;
 870                                 clock-names = "se";
 871                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 872                                 pinctrl-names = "default";
 873                                 pinctrl-0 = <&qup_uart1_default>;
 874                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 875                                 power-domains = <&rpmhpd SC7180_CX>;
 876                                 operating-points-v2 = <&qup_opp_table>;
 877                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 878                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 879                                 interconnect-names = "qup-core", "qup-config";
 880                                 status = "disabled";
 881                         };
 882
 883                         i2c2: i2c@888000 {
 884                                 compatible = "qcom,geni-i2c";
 885                                 reg = <0 0x00888000 0 0x4000>;
 886                                 clock-names = "se";
 887                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 888                                 pinctrl-names = "default";
 889                                 pinctrl-0 = <&qup_i2c2_default>;
 890                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 894                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 895                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 896                                 interconnect-names = "qup-core", "qup-config",
 897                                                         "qup-memory";
 898                                 status = "disabled";
 899                         };
 900
 901                         uart2: serial@888000 {
 902                                 compatible = "qcom,geni-uart";
 903                                 reg = <0 0x00888000 0 0x4000>;
 904                                 clock-names = "se";
 905                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 906                                 pinctrl-names = "default";
 907                                 pinctrl-0 = <&qup_uart2_default>;
 908                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 909                                 power-domains = <&rpmhpd SC7180_CX>;
 910                                 operating-points-v2 = <&qup_opp_table>;
 911                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 912                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 913                                 interconnect-names = "qup-core", "qup-config";
 914                                 status = "disabled";
 915                         };
 916
 917                         i2c3: i2c@88c000 {
 918                                 compatible = "qcom,geni-i2c";
 919                                 reg = <0 0x0088c000 0 0x4000>;
 920                                 clock-names = "se";
 921                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 922                                 pinctrl-names = "default";
 923                                 pinctrl-0 = <&qup_i2c3_default>;
 924                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 928                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 929                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 930                                 interconnect-names = "qup-core", "qup-config",
 931                                                         "qup-memory";
 932                                 status = "disabled";
 933                         };
 934
 935                         spi3: spi@88c000 {
 936                                 compatible = "qcom,geni-spi";
 937                                 reg = <0 0x0088c000 0 0x4000>;
 938                                 clock-names = "se";
 939                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 940                                 pinctrl-names = "default";
 941                                 pinctrl-0 = <&qup_spi3_default>;
 942                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 943                                 #address-cells = <1>;
 944                                 #size-cells = <0>;
 945                                 power-domains = <&rpmhpd SC7180_CX>;
 946                                 operating-points-v2 = <&qup_opp_table>;
 947                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 948                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 949                                 interconnect-names = "qup-core", "qup-config";
 950                                 status = "disabled";
 951                         };
 952
 953                         uart3: serial@88c000 {
 954                                 compatible = "qcom,geni-uart";
 955                                 reg = <0 0x0088c000 0 0x4000>;
 956                                 clock-names = "se";
 957                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 958                                 pinctrl-names = "default";
 959                                 pinctrl-0 = <&qup_uart3_default>;
 960                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 961                                 power-domains = <&rpmhpd SC7180_CX>;
 962                                 operating-points-v2 = <&qup_opp_table>;
 963                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 964                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 965                                 interconnect-names = "qup-core", "qup-config";
 966                                 status = "disabled";
 967                         };
 968
 969                         i2c4: i2c@890000 {
 970                                 compatible = "qcom,geni-i2c";
 971                                 reg = <0 0x00890000 0 0x4000>;
 972                                 clock-names = "se";
 973                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 974                                 pinctrl-names = "default";
 975                                 pinctrl-0 = <&qup_i2c4_default>;
 976                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 977                                 #address-cells = <1>;
 978                                 #size-cells = <0>;
 979                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 980                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 981                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 982                                 interconnect-names = "qup-core", "qup-config",
 983                                                         "qup-memory";
 984                                 status = "disabled";
 985                         };
 986
 987                         uart4: serial@890000 {
 988                                 compatible = "qcom,geni-uart";
 989                                 reg = <0 0x00890000 0 0x4000>;
 990                                 clock-names = "se";
 991                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 992                                 pinctrl-names = "default";
 993                                 pinctrl-0 = <&qup_uart4_default>;
 994                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 995                                 power-domains = <&rpmhpd SC7180_CX>;
 996                                 operating-points-v2 = <&qup_opp_table>;
 997                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 998                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 999                                 interconnect-names = "qup-core", "qup-config";
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c5: i2c@894000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0 0x00894000 0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c5_default>;
1010                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1014                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1015                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1016                                 interconnect-names = "qup-core", "qup-config",
1017                                                         "qup-memory";
1018                                 status = "disabled";
1019                         };
1020
1021                         spi5: spi@894000 {
1022                                 compatible = "qcom,geni-spi";
1023                                 reg = <0 0x00894000 0 0x4000>;
1024                                 clock-names = "se";
1025                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1026                                 pinctrl-names = "default";
1027                                 pinctrl-0 = <&qup_spi5_default>;
1028                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031                                 power-domains = <&rpmhpd SC7180_CX>;
1032                                 operating-points-v2 = <&qup_opp_table>;
1033                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1034                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1035                                 interconnect-names = "qup-core", "qup-config";
1036                                 status = "disabled";
1037                         };
1038
1039                         uart5: serial@894000 {
1040                                 compatible = "qcom,geni-uart";
1041                                 reg = <0 0x00894000 0 0x4000>;
1042                                 clock-names = "se";
1043                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1044                                 pinctrl-names = "default";
1045                                 pinctrl-0 = <&qup_uart5_default>;
1046                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1047                                 power-domains = <&rpmhpd SC7180_CX>;
1048                                 operating-points-v2 = <&qup_opp_table>;
1049                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1050                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1051                                 interconnect-names = "qup-core", "qup-config";
1052                                 status = "disabled";
1053                         };
1054                 };
1055
1056                 qupv3_id_1: geniqup@ac0000 {
1057                         compatible = "qcom,geni-se-qup";
1058                         reg = <0 0x00ac0000 0 0x6000>;
1059                         clock-names = "m-ahb", "s-ahb";
1060                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1061                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1062                         #address-cells = <2>;
1063                         #size-cells = <2>;
1064                         ranges;
1065                         iommus = <&apps_smmu 0x4c3 0x0>;
1066                         status = "disabled";
1067
1068                         i2c6: i2c@a80000 {
1069                                 compatible = "qcom,geni-i2c";
1070                                 reg = <0 0x00a80000 0 0x4000>;
1071                                 clock-names = "se";
1072                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1073                                 pinctrl-names = "default";
1074                                 pinctrl-0 = <&qup_i2c6_default>;
1075                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1076                                 #address-cells = <1>;
1077                                 #size-cells = <0>;
1078                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1079                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1080                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1081                                 interconnect-names = "qup-core", "qup-config",
1082                                                         "qup-memory";
1083                                 status = "disabled";
1084                         };
1085
1086                         spi6: spi@a80000 {
1087                                 compatible = "qcom,geni-spi";
1088                                 reg = <0 0x00a80000 0 0x4000>;
1089                                 clock-names = "se";
1090                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1091                                 pinctrl-names = "default";
1092                                 pinctrl-0 = <&qup_spi6_default>;
1093                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 power-domains = <&rpmhpd SC7180_CX>;
1097                                 operating-points-v2 = <&qup_opp_table>;
1098                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1099                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1100                                 interconnect-names = "qup-core", "qup-config";
1101                                 status = "disabled";
1102                         };
1103
1104                         uart6: serial@a80000 {
1105                                 compatible = "qcom,geni-uart";
1106                                 reg = <0 0x00a80000 0 0x4000>;
1107                                 clock-names = "se";
1108                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1109                                 pinctrl-names = "default";
1110                                 pinctrl-0 = <&qup_uart6_default>;
1111                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1112                                 power-domains = <&rpmhpd SC7180_CX>;
1113                                 operating-points-v2 = <&qup_opp_table>;
1114                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1115                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1116                                 interconnect-names = "qup-core", "qup-config";
1117                                 status = "disabled";
1118                         };
1119
1120                         i2c7: i2c@a84000 {
1121                                 compatible = "qcom,geni-i2c";
1122                                 reg = <0 0x00a84000 0 0x4000>;
1123                                 clock-names = "se";
1124                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1125                                 pinctrl-names = "default";
1126                                 pinctrl-0 = <&qup_i2c7_default>;
1127                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1128                                 #address-cells = <1>;
1129                                 #size-cells = <0>;
1130                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1131                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1132                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1133                                 interconnect-names = "qup-core", "qup-config",
1134                                                         "qup-memory";
1135                                 status = "disabled";
1136                         };
1137
1138                         uart7: serial@a84000 {
1139                                 compatible = "qcom,geni-uart";
1140                                 reg = <0 0x00a84000 0 0x4000>;
1141                                 clock-names = "se";
1142                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1143                                 pinctrl-names = "default";
1144                                 pinctrl-0 = <&qup_uart7_default>;
1145                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1146                                 power-domains = <&rpmhpd SC7180_CX>;
1147                                 operating-points-v2 = <&qup_opp_table>;
1148                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1149                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1150                                 interconnect-names = "qup-core", "qup-config";
1151                                 status = "disabled";
1152                         };
1153
1154                         i2c8: i2c@a88000 {
1155                                 compatible = "qcom,geni-i2c";
1156                                 reg = <0 0x00a88000 0 0x4000>;
1157                                 clock-names = "se";
1158                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1159                                 pinctrl-names = "default";
1160                                 pinctrl-0 = <&qup_i2c8_default>;
1161                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1162                                 #address-cells = <1>;
1163                                 #size-cells = <0>;
1164                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1165                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1166                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1167                                 interconnect-names = "qup-core", "qup-config",
1168                                                         "qup-memory";
1169                                 status = "disabled";
1170                         };
1171
1172                         spi8: spi@a88000 {
1173                                 compatible = "qcom,geni-spi";
1174                                 reg = <0 0x00a88000 0 0x4000>;
1175                                 clock-names = "se";
1176                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1177                                 pinctrl-names = "default";
1178                                 pinctrl-0 = <&qup_spi8_default>;
1179                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1180                                 #address-cells = <1>;
1181                                 #size-cells = <0>;
1182                                 power-domains = <&rpmhpd SC7180_CX>;
1183                                 operating-points-v2 = <&qup_opp_table>;
1184                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1185                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1186                                 interconnect-names = "qup-core", "qup-config";
1187                                 status = "disabled";
1188                         };
1189
1190                         uart8: serial@a88000 {
1191                                 compatible = "qcom,geni-debug-uart";
1192                                 reg = <0 0x00a88000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&qup_uart8_default>;
1197                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1198                                 power-domains = <&rpmhpd SC7180_CX>;
1199                                 operating-points-v2 = <&qup_opp_table>;
1200                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1202                                 interconnect-names = "qup-core", "qup-config";
1203                                 status = "disabled";
1204                         };
1205
1206                         i2c9: i2c@a8c000 {
1207                                 compatible = "qcom,geni-i2c";
1208                                 reg = <0 0x00a8c000 0 0x4000>;
1209                                 clock-names = "se";
1210                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1211                                 pinctrl-names = "default";
1212                                 pinctrl-0 = <&qup_i2c9_default>;
1213                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1214                                 #address-cells = <1>;
1215                                 #size-cells = <0>;
1216                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1217                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1218                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1219                                 interconnect-names = "qup-core", "qup-config",
1220                                                         "qup-memory";
1221                                 status = "disabled";
1222                         };
1223
1224                         uart9: serial@a8c000 {
1225                                 compatible = "qcom,geni-uart";
1226                                 reg = <0 0x00a8c000 0 0x4000>;
1227                                 clock-names = "se";
1228                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1229                                 pinctrl-names = "default";
1230                                 pinctrl-0 = <&qup_uart9_default>;
1231                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1232                                 power-domains = <&rpmhpd SC7180_CX>;
1233                                 operating-points-v2 = <&qup_opp_table>;
1234                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1235                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1236                                 interconnect-names = "qup-core", "qup-config";
1237                                 status = "disabled";
1238                         };
1239
1240                         i2c10: i2c@a90000 {
1241                                 compatible = "qcom,geni-i2c";
1242                                 reg = <0 0x00a90000 0 0x4000>;
1243                                 clock-names = "se";
1244                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1245                                 pinctrl-names = "default";
1246                                 pinctrl-0 = <&qup_i2c10_default>;
1247                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1248                                 #address-cells = <1>;
1249                                 #size-cells = <0>;
1250                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1251                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1252                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1253                                 interconnect-names = "qup-core", "qup-config",
1254                                                         "qup-memory";
1255                                 status = "disabled";
1256                         };
1257
1258                         spi10: spi@a90000 {
1259                                 compatible = "qcom,geni-spi";
1260                                 reg = <0 0x00a90000 0 0x4000>;
1261                                 clock-names = "se";
1262                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1263                                 pinctrl-names = "default";
1264                                 pinctrl-0 = <&qup_spi10_default>;
1265                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1266                                 #address-cells = <1>;
1267                                 #size-cells = <0>;
1268                                 power-domains = <&rpmhpd SC7180_CX>;
1269                                 operating-points-v2 = <&qup_opp_table>;
1270                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1271                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1272                                 interconnect-names = "qup-core", "qup-config";
1273                                 status = "disabled";
1274                         };
1275
1276                         uart10: serial@a90000 {
1277                                 compatible = "qcom,geni-uart";
1278                                 reg = <0 0x00a90000 0 0x4000>;
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1281                                 pinctrl-names = "default";
1282                                 pinctrl-0 = <&qup_uart10_default>;
1283                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1284                                 power-domains = <&rpmhpd SC7180_CX>;
1285                                 operating-points-v2 = <&qup_opp_table>;
1286                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1287                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1288                                 interconnect-names = "qup-core", "qup-config";
1289                                 status = "disabled";
1290                         };
1291
1292                         i2c11: i2c@a94000 {
1293                                 compatible = "qcom,geni-i2c";
1294                                 reg = <0 0x00a94000 0 0x4000>;
1295                                 clock-names = "se";
1296                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1297                                 pinctrl-names = "default";
1298                                 pinctrl-0 = <&qup_i2c11_default>;
1299                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1300                                 #address-cells = <1>;
1301                                 #size-cells = <0>;
1302                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1303                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1304                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1305                                 interconnect-names = "qup-core", "qup-config",
1306                                                         "qup-memory";
1307                                 status = "disabled";
1308                         };
1309
1310                         spi11: spi@a94000 {
1311                                 compatible = "qcom,geni-spi";
1312                                 reg = <0 0x00a94000 0 0x4000>;
1313                                 clock-names = "se";
1314                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1315                                 pinctrl-names = "default";
1316                                 pinctrl-0 = <&qup_spi11_default>;
1317                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1318                                 #address-cells = <1>;
1319                                 #size-cells = <0>;
1320                                 power-domains = <&rpmhpd SC7180_CX>;
1321                                 operating-points-v2 = <&qup_opp_table>;
1322                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1323                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1324                                 interconnect-names = "qup-core", "qup-config";
1325                                 status = "disabled";
1326                         };
1327
1328                         uart11: serial@a94000 {
1329                                 compatible = "qcom,geni-uart";
1330                                 reg = <0 0x00a94000 0 0x4000>;
1331                                 clock-names = "se";
1332                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1333                                 pinctrl-names = "default";
1334                                 pinctrl-0 = <&qup_uart11_default>;
1335                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1336                                 power-domains = <&rpmhpd SC7180_CX>;
1337                                 operating-points-v2 = <&qup_opp_table>;
1338                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1339                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1340                                 interconnect-names = "qup-core", "qup-config";
1341                                 status = "disabled";
1342                         };
1343                 };
1344
1345                 config_noc: interconnect@1500000 {
1346                         compatible = "qcom,sc7180-config-noc";
1347                         reg = <0 0x01500000 0 0x28000>;
1348                         #interconnect-cells = <2>;
1349                         qcom,bcm-voters = <&apps_bcm_voter>;
1350                 };
1351
1352                 system_noc: interconnect@1620000 {
1353                         compatible = "qcom,sc7180-system-noc";
1354                         reg = <0 0x01620000 0 0x17080>;
1355                         #interconnect-cells = <2>;
1356                         qcom,bcm-voters = <&apps_bcm_voter>;
1357                 };
1358
1359                 mc_virt: interconnect@1638000 {
1360                         compatible = "qcom,sc7180-mc-virt";
1361                         reg = <0 0x01638000 0 0x1000>;
1362                         #interconnect-cells = <2>;
1363                         qcom,bcm-voters = <&apps_bcm_voter>;
1364                 };
1365
1366                 qup_virt: interconnect@1650000 {
1367                         compatible = "qcom,sc7180-qup-virt";
1368                         reg = <0 0x01650000 0 0x1000>;
1369                         #interconnect-cells = <2>;
1370                         qcom,bcm-voters = <&apps_bcm_voter>;
1371                 };
1372
1373                 aggre1_noc: interconnect@16e0000 {
1374                         compatible = "qcom,sc7180-aggre1-noc";
1375                         reg = <0 0x016e0000 0 0x15080>;
1376                         #interconnect-cells = <2>;
1377                         qcom,bcm-voters = <&apps_bcm_voter>;
1378                 };
1379
1380                 aggre2_noc: interconnect@1705000 {
1381                         compatible = "qcom,sc7180-aggre2-noc";
1382                         reg = <0 0x01705000 0 0x9000>;
1383                         #interconnect-cells = <2>;
1384                         qcom,bcm-voters = <&apps_bcm_voter>;
1385                 };
1386
1387                 compute_noc: interconnect@170e000 {
1388                         compatible = "qcom,sc7180-compute-noc";
1389                         reg = <0 0x0170e000 0 0x6000>;
1390                         #interconnect-cells = <2>;
1391                         qcom,bcm-voters = <&apps_bcm_voter>;
1392                 };
1393
1394                 mmss_noc: interconnect@1740000 {
1395                         compatible = "qcom,sc7180-mmss-noc";
1396                         reg = <0 0x01740000 0 0x1c100>;
1397                         #interconnect-cells = <2>;
1398                         qcom,bcm-voters = <&apps_bcm_voter>;
1399                 };
1400
1401                 ipa_virt: interconnect@1e00000 {
1402                         compatible = "qcom,sc7180-ipa-virt";
1403                         reg = <0 0x01e00000 0 0x1000>;
1404                         #interconnect-cells = <2>;
1405                         qcom,bcm-voters = <&apps_bcm_voter>;
1406                 };
1407
1408                 ipa: ipa@1e40000 {
1409                         compatible = "qcom,sc7180-ipa";
1410
1411                         iommus = <&apps_smmu 0x440 0x0>,
1412                                  <&apps_smmu 0x442 0x0>;
1413                         reg = <0 0x1e40000 0 0x7000>,
1414                               <0 0x1e47000 0 0x2000>,
1415                               <0 0x1e04000 0 0x2c000>;
1416                         reg-names = "ipa-reg",
1417                                     "ipa-shared",
1418                                     "gsi";
1419
1420                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1421                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1422                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1423                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1424                         interrupt-names = "ipa",
1425                                           "gsi",
1426                                           "ipa-clock-query",
1427                                           "ipa-setup-ready";
1428
1429                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1430                         clock-names = "core";
1431
1432                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1433                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1434                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1435                         interconnect-names = "memory",
1436                                              "imem",
1437                                              "config";
1438
1439                         qcom,smem-states = <&ipa_smp2p_out 0>,
1440                                            <&ipa_smp2p_out 1>;
1441                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1442                                                 "ipa-clock-enabled";
1443
1444                         status = "disabled";
1445                 };
1446
1447                 tcsr_mutex_regs: syscon@1f40000 {
1448                         compatible = "syscon";
1449                         reg = <0 0x01f40000 0 0x40000>;
1450                 };
1451
1452                 tcsr_regs: syscon@1fc0000 {
1453                         compatible = "syscon";
1454                         reg = <0 0x01fc0000 0 0x40000>;
1455                 };
1456
1457                 tlmm: pinctrl@3500000 {
1458                         compatible = "qcom,sc7180-pinctrl";
1459                         reg = <0 0x03500000 0 0x300000>,
1460                               <0 0x03900000 0 0x300000>,
1461                               <0 0x03d00000 0 0x300000>;
1462                         reg-names = "west", "north", "south";
1463                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1464                         gpio-controller;
1465                         #gpio-cells = <2>;
1466                         interrupt-controller;
1467                         #interrupt-cells = <2>;
1468                         gpio-ranges = <&tlmm 0 0 120>;
1469                         wakeup-parent = <&pdc>;
1470
1471                         dp_hot_plug_det: dp-hot-plug-det {
1472                                 pinmux {
1473                                         pins = "gpio117";
1474                                         function = "dp_hot";
1475                                 };
1476                         };
1477
1478                         qspi_clk: qspi-clk {
1479                                 pinmux {
1480                                         pins = "gpio63";
1481                                         function = "qspi_clk";
1482                                 };
1483                         };
1484
1485                         qspi_cs0: qspi-cs0 {
1486                                 pinmux {
1487                                         pins = "gpio68";
1488                                         function = "qspi_cs";
1489                                 };
1490                         };
1491
1492                         qspi_cs1: qspi-cs1 {
1493                                 pinmux {
1494                                         pins = "gpio72";
1495                                         function = "qspi_cs";
1496                                 };
1497                         };
1498
1499                         qspi_data01: qspi-data01 {
1500                                 pinmux-data {
1501                                         pins = "gpio64", "gpio65";
1502                                         function = "qspi_data";
1503                                 };
1504                         };
1505
1506                         qspi_data12: qspi-data12 {
1507                                 pinmux-data {
1508                                         pins = "gpio66", "gpio67";
1509                                         function = "qspi_data";
1510                                 };
1511                         };
1512
1513                         qup_i2c0_default: qup-i2c0-default {
1514                                 pinmux {
1515                                         pins = "gpio34", "gpio35";
1516                                         function = "qup00";
1517                                 };
1518                         };
1519
1520                         qup_i2c1_default: qup-i2c1-default {
1521                                 pinmux {
1522                                         pins = "gpio0", "gpio1";
1523                                         function = "qup01";
1524                                 };
1525                         };
1526
1527                         qup_i2c2_default: qup-i2c2-default {
1528                                 pinmux {
1529                                         pins = "gpio15", "gpio16";
1530                                         function = "qup02_i2c";
1531                                 };
1532                         };
1533
1534                         qup_i2c3_default: qup-i2c3-default {
1535                                 pinmux {
1536                                         pins = "gpio38", "gpio39";
1537                                         function = "qup03";
1538                                 };
1539                         };
1540
1541                         qup_i2c4_default: qup-i2c4-default {
1542                                 pinmux {
1543                                         pins = "gpio115", "gpio116";
1544                                         function = "qup04_i2c";
1545                                 };
1546                         };
1547
1548                         qup_i2c5_default: qup-i2c5-default {
1549                                 pinmux {
1550                                         pins = "gpio25", "gpio26";
1551                                         function = "qup05";
1552                                 };
1553                         };
1554
1555                         qup_i2c6_default: qup-i2c6-default {
1556                                 pinmux {
1557                                         pins = "gpio59", "gpio60";
1558                                         function = "qup10";
1559                                 };
1560                         };
1561
1562                         qup_i2c7_default: qup-i2c7-default {
1563                                 pinmux {
1564                                         pins = "gpio6", "gpio7";
1565                                         function = "qup11_i2c";
1566                                 };
1567                         };
1568
1569                         qup_i2c8_default: qup-i2c8-default {
1570                                 pinmux {
1571                                         pins = "gpio42", "gpio43";
1572                                         function = "qup12";
1573                                 };
1574                         };
1575
1576                         qup_i2c9_default: qup-i2c9-default {
1577                                 pinmux {
1578                                         pins = "gpio46", "gpio47";
1579                                         function = "qup13_i2c";
1580                                 };
1581                         };
1582
1583                         qup_i2c10_default: qup-i2c10-default {
1584                                 pinmux {
1585                                         pins = "gpio86", "gpio87";
1586                                         function = "qup14";
1587                                 };
1588                         };
1589
1590                         qup_i2c11_default: qup-i2c11-default {
1591                                 pinmux {
1592                                         pins = "gpio53", "gpio54";
1593                                         function = "qup15";
1594                                 };
1595                         };
1596
1597                         qup_spi0_default: qup-spi0-default {
1598                                 pinmux {
1599                                         pins = "gpio34", "gpio35",
1600                                                "gpio36", "gpio37";
1601                                         function = "qup00";
1602                                 };
1603                         };
1604
1605                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1606                                 pinmux {
1607                                         pins = "gpio34", "gpio35",
1608                                                "gpio36";
1609                                         function = "qup00";
1610                                 };
1611
1612                                 pinmux-cs {
1613                                         pins = "gpio37";
1614                                         function = "gpio";
1615                                 };
1616                         };
1617
1618                         qup_spi1_default: qup-spi1-default {
1619                                 pinmux {
1620                                         pins = "gpio0", "gpio1",
1621                                                "gpio2", "gpio3";
1622                                         function = "qup01";
1623                                 };
1624                         };
1625
1626                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1627                                 pinmux {
1628                                         pins = "gpio0", "gpio1",
1629                                                "gpio2";
1630                                         function = "qup01";
1631                                 };
1632
1633                                 pinmux-cs {
1634                                         pins = "gpio3";
1635                                         function = "gpio";
1636                                 };
1637                         };
1638
1639                         qup_spi3_default: qup-spi3-default {
1640                                 pinmux {
1641                                         pins = "gpio38", "gpio39",
1642                                                "gpio40", "gpio41";
1643                                         function = "qup03";
1644                                 };
1645                         };
1646
1647                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1648                                 pinmux {
1649                                         pins = "gpio38", "gpio39",
1650                                                "gpio40";
1651                                         function = "qup03";
1652                                 };
1653
1654                                 pinmux-cs {
1655                                         pins = "gpio41";
1656                                         function = "gpio";
1657                                 };
1658                         };
1659
1660                         qup_spi5_default: qup-spi5-default {
1661                                 pinmux {
1662                                         pins = "gpio25", "gpio26",
1663                                                "gpio27", "gpio28";
1664                                         function = "qup05";
1665                                 };
1666                         };
1667
1668                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1669                                 pinmux {
1670                                         pins = "gpio25", "gpio26",
1671                                                "gpio27";
1672                                         function = "qup05";
1673                                 };
1674
1675                                 pinmux-cs {
1676                                         pins = "gpio28";
1677                                         function = "gpio";
1678                                 };
1679                         };
1680
1681                         qup_spi6_default: qup-spi6-default {
1682                                 pinmux {
1683                                         pins = "gpio59", "gpio60",
1684                                                "gpio61", "gpio62";
1685                                         function = "qup10";
1686                                 };
1687                         };
1688
1689                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1690                                 pinmux {
1691                                         pins = "gpio59", "gpio60",
1692                                                "gpio61";
1693                                         function = "qup10";
1694                                 };
1695
1696                                 pinmux-cs {
1697                                         pins = "gpio62";
1698                                         function = "gpio";
1699                                 };
1700                         };
1701
1702                         qup_spi8_default: qup-spi8-default {
1703                                 pinmux {
1704                                         pins = "gpio42", "gpio43",
1705                                                "gpio44", "gpio45";
1706                                         function = "qup12";
1707                                 };
1708                         };
1709
1710                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1711                                 pinmux {
1712                                         pins = "gpio42", "gpio43",
1713                                                "gpio44";
1714                                         function = "qup12";
1715                                 };
1716
1717                                 pinmux-cs {
1718                                         pins = "gpio45";
1719                                         function = "gpio";
1720                                 };
1721                         };
1722
1723                         qup_spi10_default: qup-spi10-default {
1724                                 pinmux {
1725                                         pins = "gpio86", "gpio87",
1726                                                "gpio88", "gpio89";
1727                                         function = "qup14";
1728                                 };
1729                         };
1730
1731                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1732                                 pinmux {
1733                                         pins = "gpio86", "gpio87",
1734                                                "gpio88";
1735                                         function = "qup14";
1736                                 };
1737
1738                                 pinmux-cs {
1739                                         pins = "gpio89";
1740                                         function = "gpio";
1741                                 };
1742                         };
1743
1744                         qup_spi11_default: qup-spi11-default {
1745                                 pinmux {
1746                                         pins = "gpio53", "gpio54",
1747                                                "gpio55", "gpio56";
1748                                         function = "qup15";
1749                                 };
1750                         };
1751
1752                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1753                                 pinmux {
1754                                         pins = "gpio53", "gpio54",
1755                                                "gpio55";
1756                                         function = "qup15";
1757                                 };
1758
1759                                 pinmux-cs {
1760                                         pins = "gpio56";
1761                                         function = "gpio";
1762                                 };
1763                         };
1764
1765                         qup_uart0_default: qup-uart0-default {
1766                                 pinmux {
1767                                         pins = "gpio34", "gpio35",
1768                                                "gpio36", "gpio37";
1769                                         function = "qup00";
1770                                 };
1771                         };
1772
1773                         qup_uart1_default: qup-uart1-default {
1774                                 pinmux {
1775                                         pins = "gpio0", "gpio1",
1776                                                "gpio2", "gpio3";
1777                                         function = "qup01";
1778                                 };
1779                         };
1780
1781                         qup_uart2_default: qup-uart2-default {
1782                                 pinmux {
1783                                         pins = "gpio15", "gpio16";
1784                                         function = "qup02_uart";
1785                                 };
1786                         };
1787
1788                         qup_uart3_default: qup-uart3-default {
1789                                 pinmux {
1790                                         pins = "gpio38", "gpio39",
1791                                                "gpio40", "gpio41";
1792                                         function = "qup03";
1793                                 };
1794                         };
1795
1796                         qup_uart4_default: qup-uart4-default {
1797                                 pinmux {
1798                                         pins = "gpio115", "gpio116";
1799                                         function = "qup04_uart";
1800                                 };
1801                         };
1802
1803                         qup_uart5_default: qup-uart5-default {
1804                                 pinmux {
1805                                         pins = "gpio25", "gpio26",
1806                                                "gpio27", "gpio28";
1807                                         function = "qup05";
1808                                 };
1809                         };
1810
1811                         qup_uart6_default: qup-uart6-default {
1812                                 pinmux {
1813                                         pins = "gpio59", "gpio60",
1814                                                "gpio61", "gpio62";
1815                                         function = "qup10";
1816                                 };
1817                         };
1818
1819                         qup_uart7_default: qup-uart7-default {
1820                                 pinmux {
1821                                         pins = "gpio6", "gpio7";
1822                                         function = "qup11_uart";
1823                                 };
1824                         };
1825
1826                         qup_uart8_default: qup-uart8-default {
1827                                 pinmux {
1828                                         pins = "gpio44", "gpio45";
1829                                         function = "qup12";
1830                                 };
1831                         };
1832
1833                         qup_uart9_default: qup-uart9-default {
1834                                 pinmux {
1835                                         pins = "gpio46", "gpio47";
1836                                         function = "qup13_uart";
1837                                 };
1838                         };
1839
1840                         qup_uart10_default: qup-uart10-default {
1841                                 pinmux {
1842                                         pins = "gpio86", "gpio87",
1843                                                "gpio88", "gpio89";
1844                                         function = "qup14";
1845                                 };
1846                         };
1847
1848                         qup_uart11_default: qup-uart11-default {
1849                                 pinmux {
1850                                         pins = "gpio53", "gpio54",
1851                                                "gpio55", "gpio56";
1852                                         function = "qup15";
1853                                 };
1854                         };
1855
1856                         sec_mi2s_active: sec-mi2s-active {
1857                                 pinmux {
1858                                         pins = "gpio49", "gpio50", "gpio51";
1859                                         function = "mi2s_1";
1860                                 };
1861                         };
1862
1863                         pri_mi2s_active: pri-mi2s-active {
1864                                 pinmux {
1865                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1866                                         function = "mi2s_0";
1867                                 };
1868                         };
1869
1870                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1871                                 pinmux {
1872                                         pins = "gpio57";
1873                                         function = "lpass_ext";
1874                                 };
1875                         };
1876                 };
1877
1878                 remoteproc_mpss: remoteproc@4080000 {
1879                         compatible = "qcom,sc7180-mpss-pas";
1880                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1881                         reg-names = "qdsp6", "rmb";
1882
1883                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1884                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1885                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1886                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1887                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1888                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1889                         interrupt-names = "wdog", "fatal", "ready", "handover",
1890                                           "stop-ack", "shutdown-ack";
1891
1892                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1893                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1894                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
1895                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1896                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1897                                  <&rpmhcc RPMH_CXO_CLK>;
1898                         clock-names = "iface", "bus", "nav", "snoc_axi",
1899                                       "mnoc_axi", "xo";
1900
1901                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1902                                         <&rpmhpd SC7180_CX>,
1903                                         <&rpmhpd SC7180_MX>,
1904                                         <&rpmhpd SC7180_MSS>;
1905                         power-domain-names = "load_state", "cx", "mx", "mss";
1906
1907                         memory-region = <&mpss_mem>;
1908
1909                         qcom,smem-states = <&modem_smp2p_out 0>;
1910                         qcom,smem-state-names = "stop";
1911
1912                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1913                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1914                         reset-names = "mss_restart", "pdc_reset";
1915
1916                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1917                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1918
1919                         status = "disabled";
1920
1921                         glink-edge {
1922                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1923                                 label = "modem";
1924                                 qcom,remote-pid = <1>;
1925                                 mboxes = <&apss_shared 12>;
1926                         };
1927                 };
1928
1929                 gpu: gpu@5000000 {
1930                         compatible = "qcom,adreno-618.0", "qcom,adreno";
1931                         #stream-id-cells = <16>;
1932                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1933                                 <0 0x05061000 0 0x800>;
1934                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1935                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1936                         iommus = <&adreno_smmu 0>;
1937                         operating-points-v2 = <&gpu_opp_table>;
1938                         qcom,gmu = <&gmu>;
1939
1940                         #cooling-cells = <2>;
1941
1942                         nvmem-cells = <&gpu_speed_bin>;
1943                         nvmem-cell-names = "speed_bin";
1944
1945                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1946                         interconnect-names = "gfx-mem";
1947
1948                         gpu_opp_table: opp-table {
1949                                 compatible = "operating-points-v2";
1950
1951                                 opp-825000000 {
1952                                         opp-hz = /bits/ 64 <825000000>;
1953                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1954                                         opp-peak-kBps = <8532000>;
1955                                         opp-supported-hw = <0x04>;
1956                                 };
1957
1958                                 opp-800000000 {
1959                                         opp-hz = /bits/ 64 <800000000>;
1960                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1961                                         opp-peak-kBps = <8532000>;
1962                                         opp-supported-hw = <0x07>;
1963                                 };
1964
1965                                 opp-650000000 {
1966                                         opp-hz = /bits/ 64 <650000000>;
1967                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1968                                         opp-peak-kBps = <7216000>;
1969                                         opp-supported-hw = <0x07>;
1970                                 };
1971
1972                                 opp-565000000 {
1973                                         opp-hz = /bits/ 64 <565000000>;
1974                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1975                                         opp-peak-kBps = <5412000>;
1976                                         opp-supported-hw = <0x07>;
1977                                 };
1978
1979                                 opp-430000000 {
1980                                         opp-hz = /bits/ 64 <430000000>;
1981                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1982                                         opp-peak-kBps = <5412000>;
1983                                         opp-supported-hw = <0x07>;
1984                                 };
1985
1986                                 opp-355000000 {
1987                                         opp-hz = /bits/ 64 <355000000>;
1988                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1989                                         opp-peak-kBps = <3072000>;
1990                                         opp-supported-hw = <0x07>;
1991                                 };
1992
1993                                 opp-267000000 {
1994                                         opp-hz = /bits/ 64 <267000000>;
1995                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1996                                         opp-peak-kBps = <3072000>;
1997                                         opp-supported-hw = <0x07>;
1998                                 };
1999
2000                                 opp-180000000 {
2001                                         opp-hz = /bits/ 64 <180000000>;
2002                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2003                                         opp-peak-kBps = <1804000>;
2004                                         opp-supported-hw = <0x07>;
2005                                 };
2006                         };
2007                 };
2008
2009                 adreno_smmu: iommu@5040000 {
2010                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2011                         reg = <0 0x05040000 0 0x10000>;
2012                         #iommu-cells = <1>;
2013                         #global-interrupts = <2>;
2014                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2015                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2016                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2017                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2018                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2019                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2020                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2021                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2022                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2023                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2024
2025                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2026                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2027                         clock-names = "bus", "iface";
2028
2029                         power-domains = <&gpucc CX_GDSC>;
2030                 };
2031
2032                 gmu: gmu@506a000 {
2033                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2034                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2035                                 <0 0x0b490000 0 0x10000>;
2036                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2037                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2038                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2039                         interrupt-names = "hfi", "gmu";
2040                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2041                                <&gpucc GPU_CC_CXO_CLK>,
2042                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2043                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2044                         clock-names = "gmu", "cxo", "axi", "memnoc";
2045                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2046                         power-domain-names = "cx", "gx";
2047                         iommus = <&adreno_smmu 5>;
2048                         operating-points-v2 = <&gmu_opp_table>;
2049
2050                         gmu_opp_table: opp-table {
2051                                 compatible = "operating-points-v2";
2052
2053                                 opp-200000000 {
2054                                         opp-hz = /bits/ 64 <200000000>;
2055                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2056                                 };
2057                         };
2058                 };
2059
2060                 gpucc: clock-controller@5090000 {
2061                         compatible = "qcom,sc7180-gpucc";
2062                         reg = <0 0x05090000 0 0x9000>;
2063                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2064                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2065                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2066                         clock-names = "bi_tcxo",
2067                                       "gcc_gpu_gpll0_clk_src",
2068                                       "gcc_gpu_gpll0_div_clk_src";
2069                         #clock-cells = <1>;
2070                         #reset-cells = <1>;
2071                         #power-domain-cells = <1>;
2072                 };
2073
2074                 stm@6002000 {
2075                         compatible = "arm,coresight-stm", "arm,primecell";
2076                         reg = <0 0x06002000 0 0x1000>,
2077                               <0 0x16280000 0 0x180000>;
2078                         reg-names = "stm-base", "stm-stimulus-base";
2079
2080                         clocks = <&aoss_qmp>;
2081                         clock-names = "apb_pclk";
2082
2083                         out-ports {
2084                                 port {
2085                                         stm_out: endpoint {
2086                                                 remote-endpoint = <&funnel0_in7>;
2087                                         };
2088                                 };
2089                         };
2090                 };
2091
2092                 funnel@6041000 {
2093                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2094                         reg = <0 0x06041000 0 0x1000>;
2095
2096                         clocks = <&aoss_qmp>;
2097                         clock-names = "apb_pclk";
2098
2099                         out-ports {
2100                                 port {
2101                                         funnel0_out: endpoint {
2102                                                 remote-endpoint = <&merge_funnel_in0>;
2103                                         };
2104                                 };
2105                         };
2106
2107                         in-ports {
2108                                 #address-cells = <1>;
2109                                 #size-cells = <0>;
2110
2111                                 port@7 {
2112                                         reg = <7>;
2113                                         funnel0_in7: endpoint {
2114                                                 remote-endpoint = <&stm_out>;
2115                                         };
2116                                 };
2117                         };
2118                 };
2119
2120                 funnel@6042000 {
2121                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2122                         reg = <0 0x06042000 0 0x1000>;
2123
2124                         clocks = <&aoss_qmp>;
2125                         clock-names = "apb_pclk";
2126
2127                         out-ports {
2128                                 port {
2129                                         funnel1_out: endpoint {
2130                                                 remote-endpoint = <&merge_funnel_in1>;
2131                                         };
2132                                 };
2133                         };
2134
2135                         in-ports {
2136                                 #address-cells = <1>;
2137                                 #size-cells = <0>;
2138
2139                                 port@4 {
2140                                         reg = <4>;
2141                                         funnel1_in4: endpoint {
2142                                                 remote-endpoint = <&apss_merge_funnel_out>;
2143                                         };
2144                                 };
2145                         };
2146                 };
2147
2148                 funnel@6045000 {
2149                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2150                         reg = <0 0x06045000 0 0x1000>;
2151
2152                         clocks = <&aoss_qmp>;
2153                         clock-names = "apb_pclk";
2154
2155                         out-ports {
2156                                 port {
2157                                         merge_funnel_out: endpoint {
2158                                                 remote-endpoint = <&swao_funnel_in>;
2159                                         };
2160                                 };
2161                         };
2162
2163                         in-ports {
2164                                 #address-cells = <1>;
2165                                 #size-cells = <0>;
2166
2167                                 port@0 {
2168                                         reg = <0>;
2169                                         merge_funnel_in0: endpoint {
2170                                                 remote-endpoint = <&funnel0_out>;
2171                                         };
2172                                 };
2173
2174                                 port@1 {
2175                                         reg = <1>;
2176                                         merge_funnel_in1: endpoint {
2177                                                 remote-endpoint = <&funnel1_out>;
2178                                         };
2179                                 };
2180                         };
2181                 };
2182
2183                 replicator@6046000 {
2184                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2185                         reg = <0 0x06046000 0 0x1000>;
2186
2187                         clocks = <&aoss_qmp>;
2188                         clock-names = "apb_pclk";
2189
2190                         out-ports {
2191                                 port {
2192                                         replicator_out: endpoint {
2193                                                 remote-endpoint = <&etr_in>;
2194                                         };
2195                                 };
2196                         };
2197
2198                         in-ports {
2199                                 port {
2200                                         replicator_in: endpoint {
2201                                                 remote-endpoint = <&swao_replicator_out>;
2202                                         };
2203                                 };
2204                         };
2205                 };
2206
2207                 etr@6048000 {
2208                         compatible = "arm,coresight-tmc", "arm,primecell";
2209                         reg = <0 0x06048000 0 0x1000>;
2210                         iommus = <&apps_smmu 0x04a0 0x20>;
2211
2212                         clocks = <&aoss_qmp>;
2213                         clock-names = "apb_pclk";
2214                         arm,scatter-gather;
2215
2216                         in-ports {
2217                                 port {
2218                                         etr_in: endpoint {
2219                                                 remote-endpoint = <&replicator_out>;
2220                                         };
2221                                 };
2222                         };
2223                 };
2224
2225                 funnel@6b04000 {
2226                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2227                         reg = <0 0x06b04000 0 0x1000>;
2228
2229                         clocks = <&aoss_qmp>;
2230                         clock-names = "apb_pclk";
2231
2232                         out-ports {
2233                                 port {
2234                                         swao_funnel_out: endpoint {
2235                                                 remote-endpoint = <&etf_in>;
2236                                         };
2237                                 };
2238                         };
2239
2240                         in-ports {
2241                                 #address-cells = <1>;
2242                                 #size-cells = <0>;
2243
2244                                 port@7 {
2245                                         reg = <7>;
2246                                         swao_funnel_in: endpoint {
2247                                                 remote-endpoint = <&merge_funnel_out>;
2248                                         };
2249                                 };
2250                         };
2251                 };
2252
2253                 etf@6b05000 {
2254                         compatible = "arm,coresight-tmc", "arm,primecell";
2255                         reg = <0 0x06b05000 0 0x1000>;
2256
2257                         clocks = <&aoss_qmp>;
2258                         clock-names = "apb_pclk";
2259
2260                         out-ports {
2261                                 port {
2262                                         etf_out: endpoint {
2263                                                 remote-endpoint = <&swao_replicator_in>;
2264                                         };
2265                                 };
2266                         };
2267
2268                         in-ports {
2269                                 port {
2270                                         etf_in: endpoint {
2271                                                 remote-endpoint = <&swao_funnel_out>;
2272                                         };
2273                                 };
2274                         };
2275                 };
2276
2277                 replicator@6b06000 {
2278                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2279                         reg = <0 0x06b06000 0 0x1000>;
2280
2281                         clocks = <&aoss_qmp>;
2282                         clock-names = "apb_pclk";
2283                         qcom,replicator-loses-context;
2284
2285                         out-ports {
2286                                 port {
2287                                         swao_replicator_out: endpoint {
2288                                                 remote-endpoint = <&replicator_in>;
2289                                         };
2290                                 };
2291                         };
2292
2293                         in-ports {
2294                                 port {
2295                                         swao_replicator_in: endpoint {
2296                                                 remote-endpoint = <&etf_out>;
2297                                         };
2298                                 };
2299                         };
2300                 };
2301
2302                 etm@7040000 {
2303                         compatible = "arm,coresight-etm4x", "arm,primecell";
2304                         reg = <0 0x07040000 0 0x1000>;
2305
2306                         cpu = <&CPU0>;
2307
2308                         clocks = <&aoss_qmp>;
2309                         clock-names = "apb_pclk";
2310                         arm,coresight-loses-context-with-cpu;
2311                         qcom,skip-power-up;
2312
2313                         out-ports {
2314                                 port {
2315                                         etm0_out: endpoint {
2316                                                 remote-endpoint = <&apss_funnel_in0>;
2317                                         };
2318                                 };
2319                         };
2320                 };
2321
2322                 etm@7140000 {
2323                         compatible = "arm,coresight-etm4x", "arm,primecell";
2324                         reg = <0 0x07140000 0 0x1000>;
2325
2326                         cpu = <&CPU1>;
2327
2328                         clocks = <&aoss_qmp>;
2329                         clock-names = "apb_pclk";
2330                         arm,coresight-loses-context-with-cpu;
2331                         qcom,skip-power-up;
2332
2333                         out-ports {
2334                                 port {
2335                                         etm1_out: endpoint {
2336                                                 remote-endpoint = <&apss_funnel_in1>;
2337                                         };
2338                                 };
2339                         };
2340                 };
2341
2342                 etm@7240000 {
2343                         compatible = "arm,coresight-etm4x", "arm,primecell";
2344                         reg = <0 0x07240000 0 0x1000>;
2345
2346                         cpu = <&CPU2>;
2347
2348                         clocks = <&aoss_qmp>;
2349                         clock-names = "apb_pclk";
2350                         arm,coresight-loses-context-with-cpu;
2351                         qcom,skip-power-up;
2352
2353                         out-ports {
2354                                 port {
2355                                         etm2_out: endpoint {
2356                                                 remote-endpoint = <&apss_funnel_in2>;
2357                                         };
2358                                 };
2359                         };
2360                 };
2361
2362                 etm@7340000 {
2363                         compatible = "arm,coresight-etm4x", "arm,primecell";
2364                         reg = <0 0x07340000 0 0x1000>;
2365
2366                         cpu = <&CPU3>;
2367
2368                         clocks = <&aoss_qmp>;
2369                         clock-names = "apb_pclk";
2370                         arm,coresight-loses-context-with-cpu;
2371                         qcom,skip-power-up;
2372
2373                         out-ports {
2374                                 port {
2375                                         etm3_out: endpoint {
2376                                                 remote-endpoint = <&apss_funnel_in3>;
2377                                         };
2378                                 };
2379                         };
2380                 };
2381
2382                 etm@7440000 {
2383                         compatible = "arm,coresight-etm4x", "arm,primecell";
2384                         reg = <0 0x07440000 0 0x1000>;
2385
2386                         cpu = <&CPU4>;
2387
2388                         clocks = <&aoss_qmp>;
2389                         clock-names = "apb_pclk";
2390                         arm,coresight-loses-context-with-cpu;
2391                         qcom,skip-power-up;
2392
2393                         out-ports {
2394                                 port {
2395                                         etm4_out: endpoint {
2396                                                 remote-endpoint = <&apss_funnel_in4>;
2397                                         };
2398                                 };
2399                         };
2400                 };
2401
2402                 etm@7540000 {
2403                         compatible = "arm,coresight-etm4x", "arm,primecell";
2404                         reg = <0 0x07540000 0 0x1000>;
2405
2406                         cpu = <&CPU5>;
2407
2408                         clocks = <&aoss_qmp>;
2409                         clock-names = "apb_pclk";
2410                         arm,coresight-loses-context-with-cpu;
2411                         qcom,skip-power-up;
2412
2413                         out-ports {
2414                                 port {
2415                                         etm5_out: endpoint {
2416                                                 remote-endpoint = <&apss_funnel_in5>;
2417                                         };
2418                                 };
2419                         };
2420                 };
2421
2422                 etm@7640000 {
2423                         compatible = "arm,coresight-etm4x", "arm,primecell";
2424                         reg = <0 0x07640000 0 0x1000>;
2425
2426                         cpu = <&CPU6>;
2427
2428                         clocks = <&aoss_qmp>;
2429                         clock-names = "apb_pclk";
2430                         arm,coresight-loses-context-with-cpu;
2431                         qcom,skip-power-up;
2432
2433                         out-ports {
2434                                 port {
2435                                         etm6_out: endpoint {
2436                                                 remote-endpoint = <&apss_funnel_in6>;
2437                                         };
2438                                 };
2439                         };
2440                 };
2441
2442                 etm@7740000 {
2443                         compatible = "arm,coresight-etm4x", "arm,primecell";
2444                         reg = <0 0x07740000 0 0x1000>;
2445
2446                         cpu = <&CPU7>;
2447
2448                         clocks = <&aoss_qmp>;
2449                         clock-names = "apb_pclk";
2450                         arm,coresight-loses-context-with-cpu;
2451                         qcom,skip-power-up;
2452
2453                         out-ports {
2454                                 port {
2455                                         etm7_out: endpoint {
2456                                                 remote-endpoint = <&apss_funnel_in7>;
2457                                         };
2458                                 };
2459                         };
2460                 };
2461
2462                 funnel@7800000 { /* APSS Funnel */
2463                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2464                         reg = <0 0x07800000 0 0x1000>;
2465
2466                         clocks = <&aoss_qmp>;
2467                         clock-names = "apb_pclk";
2468
2469                         out-ports {
2470                                 port {
2471                                         apss_funnel_out: endpoint {
2472                                                 remote-endpoint = <&apss_merge_funnel_in>;
2473                                         };
2474                                 };
2475                         };
2476
2477                         in-ports {
2478                                 #address-cells = <1>;
2479                                 #size-cells = <0>;
2480
2481                                 port@0 {
2482                                         reg = <0>;
2483                                         apss_funnel_in0: endpoint {
2484                                                 remote-endpoint = <&etm0_out>;
2485                                         };
2486                                 };
2487
2488                                 port@1 {
2489                                         reg = <1>;
2490                                         apss_funnel_in1: endpoint {
2491                                                 remote-endpoint = <&etm1_out>;
2492                                         };
2493                                 };
2494
2495                                 port@2 {
2496                                         reg = <2>;
2497                                         apss_funnel_in2: endpoint {
2498                                                 remote-endpoint = <&etm2_out>;
2499                                         };
2500                                 };
2501
2502                                 port@3 {
2503                                         reg = <3>;
2504                                         apss_funnel_in3: endpoint {
2505                                                 remote-endpoint = <&etm3_out>;
2506                                         };
2507                                 };
2508
2509                                 port@4 {
2510                                         reg = <4>;
2511                                         apss_funnel_in4: endpoint {
2512                                                 remote-endpoint = <&etm4_out>;
2513                                         };
2514                                 };
2515
2516                                 port@5 {
2517                                         reg = <5>;
2518                                         apss_funnel_in5: endpoint {
2519                                                 remote-endpoint = <&etm5_out>;
2520                                         };
2521                                 };
2522
2523                                 port@6 {
2524                                         reg = <6>;
2525                                         apss_funnel_in6: endpoint {
2526                                                 remote-endpoint = <&etm6_out>;
2527                                         };
2528                                 };
2529
2530                                 port@7 {
2531                                         reg = <7>;
2532                                         apss_funnel_in7: endpoint {
2533                                                 remote-endpoint = <&etm7_out>;
2534                                         };
2535                                 };
2536                         };
2537                 };
2538
2539                 funnel@7810000 {
2540                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2541                         reg = <0 0x07810000 0 0x1000>;
2542
2543                         clocks = <&aoss_qmp>;
2544                         clock-names = "apb_pclk";
2545
2546                         out-ports {
2547                                 port {
2548                                         apss_merge_funnel_out: endpoint {
2549                                                 remote-endpoint = <&funnel1_in4>;
2550                                         };
2551                                 };
2552                         };
2553
2554                         in-ports {
2555                                 port {
2556                                         apss_merge_funnel_in: endpoint {
2557                                                 remote-endpoint = <&apss_funnel_out>;
2558                                         };
2559                                 };
2560                         };
2561                 };
2562
2563                 sdhc_2: sdhci@8804000 {
2564                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2565                         reg = <0 0x08804000 0 0x1000>;
2566
2567                         iommus = <&apps_smmu 0x80 0>;
2568                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2569                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2570                         interrupt-names = "hc_irq", "pwr_irq";
2571
2572                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2573                                  <&gcc GCC_SDCC2_AHB_CLK>,
2574                                  <&rpmhcc RPMH_CXO_CLK>;
2575                         clock-names = "core", "iface", "xo";
2576
2577                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2578                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2579                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2580                         power-domains = <&rpmhpd SC7180_CX>;
2581                         operating-points-v2 = <&sdhc2_opp_table>;
2582
2583                         bus-width = <4>;
2584
2585                         status = "disabled";
2586
2587                         sdhc2_opp_table: sdhc2-opp-table {
2588                                 compatible = "operating-points-v2";
2589
2590                                 opp-100000000 {
2591                                         opp-hz = /bits/ 64 <100000000>;
2592                                         required-opps = <&rpmhpd_opp_low_svs>;
2593                                         opp-peak-kBps = <1800000 600000>;
2594                                         opp-avg-kBps = <100000 0>;
2595                                 };
2596
2597                                 opp-202000000 {
2598                                         opp-hz = /bits/ 64 <202000000>;
2599                                         required-opps = <&rpmhpd_opp_nom>;
2600                                         opp-peak-kBps = <5400000 1600000>;
2601                                         opp-avg-kBps = <200000 0>;
2602                                 };
2603                         };
2604                 };
2605
2606                 qspi_opp_table: qspi-opp-table {
2607                         compatible = "operating-points-v2";
2608
2609                         opp-75000000 {
2610                                 opp-hz = /bits/ 64 <75000000>;
2611                                 required-opps = <&rpmhpd_opp_low_svs>;
2612                         };
2613
2614                         opp-150000000 {
2615                                 opp-hz = /bits/ 64 <150000000>;
2616                                 required-opps = <&rpmhpd_opp_svs>;
2617                         };
2618
2619                         opp-300000000 {
2620                                 opp-hz = /bits/ 64 <300000000>;
2621                                 required-opps = <&rpmhpd_opp_nom>;
2622                         };
2623                 };
2624
2625                 qspi: spi@88dc000 {
2626                         compatible = "qcom,qspi-v1";
2627                         reg = <0 0x088dc000 0 0x600>;
2628                         #address-cells = <1>;
2629                         #size-cells = <0>;
2630                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2631                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2632                                  <&gcc GCC_QSPI_CORE_CLK>;
2633                         clock-names = "iface", "core";
2634                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2635                                         &config_noc SLAVE_QSPI_0 0>;
2636                         interconnect-names = "qspi-config";
2637                         power-domains = <&rpmhpd SC7180_CX>;
2638                         operating-points-v2 = <&qspi_opp_table>;
2639                         status = "disabled";
2640                 };
2641
2642                 usb_1_hsphy: phy@88e3000 {
2643                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2644                         reg = <0 0x088e3000 0 0x400>;
2645                         status = "disabled";
2646                         #phy-cells = <0>;
2647                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2648                                  <&rpmhcc RPMH_CXO_CLK>;
2649                         clock-names = "cfg_ahb", "ref";
2650                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2651
2652                         nvmem-cells = <&qusb2p_hstx_trim>;
2653                 };
2654
2655                 usb_1_qmpphy: phy-wrapper@88e9000 {
2656                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2657                         reg = <0 0x088e9000 0 0x18c>,
2658                               <0 0x088e8000 0 0x3c>,
2659                               <0 0x088ea000 0 0x18c>;
2660                         status = "disabled";
2661                         #address-cells = <2>;
2662                         #size-cells = <2>;
2663                         ranges;
2664
2665                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2666                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2667                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2668                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2669                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2670
2671                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2672                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2673                         reset-names = "phy", "common";
2674
2675                         usb_1_ssphy: usb3-phy@88e9200 {
2676                                 reg = <0 0x088e9200 0 0x128>,
2677                                       <0 0x088e9400 0 0x200>,
2678                                       <0 0x088e9c00 0 0x218>,
2679                                       <0 0x088e9600 0 0x128>,
2680                                       <0 0x088e9800 0 0x200>,
2681                                       <0 0x088e9a00 0 0x18>;
2682                                 #clock-cells = <0>;
2683                                 #phy-cells = <0>;
2684                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2685                                 clock-names = "pipe0";
2686                                 clock-output-names = "usb3_phy_pipe_clk_src";
2687                         };
2688
2689                         dp_phy: dp-phy@88ea200 {
2690                                 reg = <0 0x088ea200 0 0x200>,
2691                                       <0 0x088ea400 0 0x200>,
2692                                       <0 0x088eaa00 0 0x200>,
2693                                       <0 0x088ea600 0 0x200>,
2694                                       <0 0x088ea800 0 0x200>;
2695                                 #clock-cells = <1>;
2696                                 #phy-cells = <0>;
2697                         };
2698                 };
2699
2700                 dc_noc: interconnect@9160000 {
2701                         compatible = "qcom,sc7180-dc-noc";
2702                         reg = <0 0x09160000 0 0x03200>;
2703                         #interconnect-cells = <2>;
2704                         qcom,bcm-voters = <&apps_bcm_voter>;
2705                 };
2706
2707                 system-cache-controller@9200000 {
2708                         compatible = "qcom,sc7180-llcc";
2709                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2710                         reg-names = "llcc_base", "llcc_broadcast_base";
2711                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2712                 };
2713
2714                 gem_noc: interconnect@9680000 {
2715                         compatible = "qcom,sc7180-gem-noc";
2716                         reg = <0 0x09680000 0 0x3e200>;
2717                         #interconnect-cells = <2>;
2718                         qcom,bcm-voters = <&apps_bcm_voter>;
2719                 };
2720
2721                 npu_noc: interconnect@9990000 {
2722                         compatible = "qcom,sc7180-npu-noc";
2723                         reg = <0 0x09990000 0 0x1600>;
2724                         #interconnect-cells = <2>;
2725                         qcom,bcm-voters = <&apps_bcm_voter>;
2726                 };
2727
2728                 usb_1: usb@a6f8800 {
2729                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2730                         reg = <0 0x0a6f8800 0 0x400>;
2731                         status = "disabled";
2732                         #address-cells = <2>;
2733                         #size-cells = <2>;
2734                         ranges;
2735                         dma-ranges;
2736
2737                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2738                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2739                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2740                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2741                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2742                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2743                                       "sleep";
2744
2745                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2746                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2747                         assigned-clock-rates = <19200000>, <150000000>;
2748
2749                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2750                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2751                                               <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2752                                               <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2753                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2754                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2755
2756                         power-domains = <&gcc USB30_PRIM_GDSC>;
2757
2758                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2759
2760                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2761                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2762                         interconnect-names = "usb-ddr", "apps-usb";
2763
2764                         usb_1_dwc3: dwc3@a600000 {
2765                                 compatible = "snps,dwc3";
2766                                 reg = <0 0x0a600000 0 0xe000>;
2767                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2768                                 iommus = <&apps_smmu 0x540 0>;
2769                                 snps,dis_u2_susphy_quirk;
2770                                 snps,dis_enblslpm_quirk;
2771                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2772                                 phy-names = "usb2-phy", "usb3-phy";
2773                                 maximum-speed = "super-speed";
2774                         };
2775                 };
2776
2777                 venus: video-codec@aa00000 {
2778                         compatible = "qcom,sc7180-venus";
2779                         reg = <0 0x0aa00000 0 0xff000>;
2780                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2781                         power-domains = <&videocc VENUS_GDSC>,
2782                                         <&videocc VCODEC0_GDSC>,
2783                                         <&rpmhpd SC7180_CX>;
2784                         power-domain-names = "venus", "vcodec0", "cx";
2785                         operating-points-v2 = <&venus_opp_table>;
2786                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2787                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2788                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2789                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2790                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2791                         clock-names = "core", "iface", "bus",
2792                                       "vcodec0_core", "vcodec0_bus";
2793                         iommus = <&apps_smmu 0x0c00 0x60>;
2794                         memory-region = <&venus_mem>;
2795                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2796                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2797                         interconnect-names = "video-mem", "cpu-cfg";
2798
2799                         video-decoder {
2800                                 compatible = "venus-decoder";
2801                         };
2802
2803                         video-encoder {
2804                                 compatible = "venus-encoder";
2805                         };
2806
2807                         venus_opp_table: venus-opp-table {
2808                                 compatible = "operating-points-v2";
2809
2810                                 opp-150000000 {
2811                                         opp-hz = /bits/ 64 <150000000>;
2812                                         required-opps = <&rpmhpd_opp_low_svs>;
2813                                 };
2814
2815                                 opp-270000000 {
2816                                         opp-hz = /bits/ 64 <270000000>;
2817                                         required-opps = <&rpmhpd_opp_svs>;
2818                                 };
2819
2820                                 opp-340000000 {
2821                                         opp-hz = /bits/ 64 <340000000>;
2822                                         required-opps = <&rpmhpd_opp_svs_l1>;
2823                                 };
2824
2825                                 opp-434000000 {
2826                                         opp-hz = /bits/ 64 <434000000>;
2827                                         required-opps = <&rpmhpd_opp_nom>;
2828                                 };
2829
2830                                 opp-500000097 {
2831                                         opp-hz = /bits/ 64 <500000097>;
2832                                         required-opps = <&rpmhpd_opp_turbo>;
2833                                 };
2834                         };
2835                 };
2836
2837                 videocc: clock-controller@ab00000 {
2838                         compatible = "qcom,sc7180-videocc";
2839                         reg = <0 0x0ab00000 0 0x10000>;
2840                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2841                         clock-names = "bi_tcxo";
2842                         #clock-cells = <1>;
2843                         #reset-cells = <1>;
2844                         #power-domain-cells = <1>;
2845                 };
2846
2847                 camnoc_virt: interconnect@ac00000 {
2848                         compatible = "qcom,sc7180-camnoc-virt";
2849                         reg = <0 0x0ac00000 0 0x1000>;
2850                         #interconnect-cells = <2>;
2851                         qcom,bcm-voters = <&apps_bcm_voter>;
2852                 };
2853
2854                 camcc: clock-controller@ad00000 {
2855                         compatible = "qcom,sc7180-camcc";
2856                         reg = <0 0x0ad00000 0 0x10000>;
2857                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2858                                <&gcc GCC_CAMERA_AHB_CLK>,
2859                                <&gcc GCC_CAMERA_XO_CLK>;
2860                         clock-names = "bi_tcxo", "iface", "xo";
2861                         #clock-cells = <1>;
2862                         #reset-cells = <1>;
2863                         #power-domain-cells = <1>;
2864                 };
2865
2866                 mdss: mdss@ae00000 {
2867                         compatible = "qcom,sc7180-mdss";
2868                         reg = <0 0x0ae00000 0 0x1000>;
2869                         reg-names = "mdss";
2870
2871                         power-domains = <&dispcc MDSS_GDSC>;
2872
2873                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2874                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2875                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2876                         clock-names = "iface", "ahb", "core";
2877
2878                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2879                         assigned-clock-rates = <300000000>;
2880
2881                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2882                         interrupt-controller;
2883                         #interrupt-cells = <1>;
2884
2885                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2886                         interconnect-names = "mdp0-mem";
2887
2888                         iommus = <&apps_smmu 0x800 0x2>;
2889
2890                         #address-cells = <2>;
2891                         #size-cells = <2>;
2892                         ranges;
2893
2894                         status = "disabled";
2895
2896                         mdp: mdp@ae01000 {
2897                                 compatible = "qcom,sc7180-dpu";
2898                                 reg = <0 0x0ae01000 0 0x8f000>,
2899                                       <0 0x0aeb0000 0 0x2008>;
2900                                 reg-names = "mdp", "vbif";
2901
2902                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2903                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2904                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2905                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2906                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2907                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2908                                 clock-names = "bus", "iface", "rot", "lut", "core",
2909                                               "vsync";
2910                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2911                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2912                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
2913                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
2914                                 assigned-clock-rates = <300000000>,
2915                                                        <19200000>,
2916                                                        <19200000>,
2917                                                        <19200000>;
2918                                 operating-points-v2 = <&mdp_opp_table>;
2919                                 power-domains = <&rpmhpd SC7180_CX>;
2920
2921                                 interrupt-parent = <&mdss>;
2922                                 interrupts = <0>;
2923
2924                                 status = "disabled";
2925
2926                                 ports {
2927                                         #address-cells = <1>;
2928                                         #size-cells = <0>;
2929
2930                                         port@0 {
2931                                                 reg = <0>;
2932                                                 dpu_intf1_out: endpoint {
2933                                                         remote-endpoint = <&dsi0_in>;
2934                                                 };
2935                                         };
2936
2937                                         port@2 {
2938                                                 reg = <2>;
2939                                                 dpu_intf0_out: endpoint {
2940                                                         remote-endpoint = <&dp_in>;
2941                                                 };
2942                                         };
2943                                 };
2944
2945                                 mdp_opp_table: mdp-opp-table {
2946                                         compatible = "operating-points-v2";
2947
2948                                         opp-200000000 {
2949                                                 opp-hz = /bits/ 64 <200000000>;
2950                                                 required-opps = <&rpmhpd_opp_low_svs>;
2951                                         };
2952
2953                                         opp-300000000 {
2954                                                 opp-hz = /bits/ 64 <300000000>;
2955                                                 required-opps = <&rpmhpd_opp_svs>;
2956                                         };
2957
2958                                         opp-345000000 {
2959                                                 opp-hz = /bits/ 64 <345000000>;
2960                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2961                                         };
2962
2963                                         opp-460000000 {
2964                                                 opp-hz = /bits/ 64 <460000000>;
2965                                                 required-opps = <&rpmhpd_opp_nom>;
2966                                         };
2967                                 };
2968
2969                         };
2970
2971                         dsi0: dsi@ae94000 {
2972                                 compatible = "qcom,mdss-dsi-ctrl";
2973                                 reg = <0 0x0ae94000 0 0x400>;
2974                                 reg-names = "dsi_ctrl";
2975
2976                                 interrupt-parent = <&mdss>;
2977                                 interrupts = <4>;
2978
2979                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2980                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2981                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2982                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2983                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2984                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2985                                 clock-names = "byte",
2986                                               "byte_intf",
2987                                               "pixel",
2988                                               "core",
2989                                               "iface",
2990                                               "bus";
2991
2992                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2993                                 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
2994
2995                                 operating-points-v2 = <&dsi_opp_table>;
2996                                 power-domains = <&rpmhpd SC7180_CX>;
2997
2998                                 phys = <&dsi_phy>;
2999                                 phy-names = "dsi";
3000
3001                                 #address-cells = <1>;
3002                                 #size-cells = <0>;
3003
3004                                 status = "disabled";
3005
3006                                 ports {
3007                                         #address-cells = <1>;
3008                                         #size-cells = <0>;
3009
3010                                         port@0 {
3011                                                 reg = <0>;
3012                                                 dsi0_in: endpoint {
3013                                                         remote-endpoint = <&dpu_intf1_out>;
3014                                                 };
3015                                         };
3016
3017                                         port@1 {
3018                                                 reg = <1>;
3019                                                 dsi0_out: endpoint {
3020                                                 };
3021                                         };
3022                                 };
3023
3024                                 dsi_opp_table: dsi-opp-table {
3025                                         compatible = "operating-points-v2";
3026
3027                                         opp-187500000 {
3028                                                 opp-hz = /bits/ 64 <187500000>;
3029                                                 required-opps = <&rpmhpd_opp_low_svs>;
3030                                         };
3031
3032                                         opp-300000000 {
3033                                                 opp-hz = /bits/ 64 <300000000>;
3034                                                 required-opps = <&rpmhpd_opp_svs>;
3035                                         };
3036
3037                                         opp-358000000 {
3038                                                 opp-hz = /bits/ 64 <358000000>;
3039                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3040                                         };
3041                                 };
3042                         };
3043
3044                         dsi_phy: dsi-phy@ae94400 {
3045                                 compatible = "qcom,dsi-phy-10nm";
3046                                 reg = <0 0x0ae94400 0 0x200>,
3047                                       <0 0x0ae94600 0 0x280>,
3048                                       <0 0x0ae94a00 0 0x1e0>;
3049                                 reg-names = "dsi_phy",
3050                                             "dsi_phy_lane",
3051                                             "dsi_pll";
3052
3053                                 #clock-cells = <1>;
3054                                 #phy-cells = <0>;
3055
3056                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3057                                          <&rpmhcc RPMH_CXO_CLK>;
3058                                 clock-names = "iface", "ref";
3059
3060                                 status = "disabled";
3061                         };
3062
3063                         mdss_dp: displayport-controller@ae90000 {
3064                                 compatible = "qcom,sc7180-dp";
3065                                 status = "disabled";
3066
3067                                 reg = <0 0x0ae90000 0 0x1400>;
3068
3069                                 interrupt-parent = <&mdss>;
3070                                 interrupts = <12>;
3071
3072                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3073                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3074                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3075                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3076                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3077                                 clock-names = "core_iface", "core_aux", "ctrl_link",
3078                                               "ctrl_link_iface", "stream_pixel";
3079                                 #clock-cells = <1>;
3080                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3081                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3082                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3083                                 phys = <&dp_phy>;
3084                                 phy-names = "dp";
3085
3086                                 operating-points-v2 = <&dp_opp_table>;
3087                                 power-domains = <&rpmhpd SC7180_CX>;
3088
3089                                 #sound-dai-cells = <0>;
3090
3091                                 ports {
3092                                         #address-cells = <1>;
3093                                         #size-cells = <0>;
3094                                         port@0 {
3095                                                 reg = <0>;
3096                                                 dp_in: endpoint {
3097                                                         remote-endpoint = <&dpu_intf0_out>;
3098                                                 };
3099                                         };
3100
3101                                         port@1 {
3102                                                 reg = <1>;
3103                                                 dp_out: endpoint { };
3104                                         };
3105                                 };
3106
3107                                 dp_opp_table: opp-table {
3108                                         compatible = "operating-points-v2";
3109
3110                                         opp-160000000 {
3111                                                 opp-hz = /bits/ 64 <160000000>;
3112                                                 required-opps = <&rpmhpd_opp_low_svs>;
3113                                         };
3114
3115                                         opp-270000000 {
3116                                                 opp-hz = /bits/ 64 <270000000>;
3117                                                 required-opps = <&rpmhpd_opp_svs>;
3118                                         };
3119
3120                                         opp-540000000 {
3121                                                 opp-hz = /bits/ 64 <540000000>;
3122                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3123                                         };
3124
3125                                         opp-810000000 {
3126                                                 opp-hz = /bits/ 64 <810000000>;
3127                                                 required-opps = <&rpmhpd_opp_nom>;
3128                                         };
3129                                 };
3130                         };
3131                 };
3132
3133                 dispcc: clock-controller@af00000 {
3134                         compatible = "qcom,sc7180-dispcc";
3135                         reg = <0 0x0af00000 0 0x200000>;
3136                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3137                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3138                                  <&dsi_phy 0>,
3139                                  <&dsi_phy 1>,
3140                                  <&dp_phy 0>,
3141                                  <&dp_phy 1>;
3142                         clock-names = "bi_tcxo",
3143                                       "gcc_disp_gpll0_clk_src",
3144                                       "dsi0_phy_pll_out_byteclk",
3145                                       "dsi0_phy_pll_out_dsiclk",
3146                                       "dp_phy_pll_link_clk",
3147                                       "dp_phy_pll_vco_div_clk";
3148                         #clock-cells = <1>;
3149                         #reset-cells = <1>;
3150                         #power-domain-cells = <1>;
3151                 };
3152
3153                 pdc: interrupt-controller@b220000 {
3154                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3155                         reg = <0 0x0b220000 0 0x30000>;
3156                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3157                         #interrupt-cells = <2>;
3158                         interrupt-parent = <&intc>;
3159                         interrupt-controller;
3160                 };
3161
3162                 pdc_reset: reset-controller@b2e0000 {
3163                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3164                         reg = <0 0x0b2e0000 0 0x20000>;
3165                         #reset-cells = <1>;
3166                 };
3167
3168                 tsens0: thermal-sensor@c263000 {
3169                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3170                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3171                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3172                         #qcom,sensors = <15>;
3173                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3174                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3175                         interrupt-names = "uplow","critical";
3176                         #thermal-sensor-cells = <1>;
3177                 };
3178
3179                 tsens1: thermal-sensor@c265000 {
3180                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3181                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3182                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3183                         #qcom,sensors = <10>;
3184                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3185                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3186                         interrupt-names = "uplow","critical";
3187                         #thermal-sensor-cells = <1>;
3188                 };
3189
3190                 aoss_reset: reset-controller@c2a0000 {
3191                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3192                         reg = <0 0x0c2a0000 0 0x31000>;
3193                         #reset-cells = <1>;
3194                 };
3195
3196                 aoss_qmp: power-controller@c300000 {
3197                         compatible = "qcom,sc7180-aoss-qmp";
3198                         reg = <0 0x0c300000 0 0x100000>;
3199                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3200                         mboxes = <&apss_shared 0>;
3201
3202                         #clock-cells = <0>;
3203                         #power-domain-cells = <1>;
3204                 };
3205
3206                 spmi_bus: spmi@c440000 {
3207                         compatible = "qcom,spmi-pmic-arb";
3208                         reg = <0 0x0c440000 0 0x1100>,
3209                               <0 0x0c600000 0 0x2000000>,
3210                               <0 0x0e600000 0 0x100000>,
3211                               <0 0x0e700000 0 0xa0000>,
3212                               <0 0x0c40a000 0 0x26000>;
3213                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3214                         interrupt-names = "periph_irq";
3215                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3216                         qcom,ee = <0>;
3217                         qcom,channel = <0>;
3218                         #address-cells = <1>;
3219                         #size-cells = <1>;
3220                         interrupt-controller;
3221                         #interrupt-cells = <4>;
3222                         cell-index = <0>;
3223                 };
3224
3225                 apps_smmu: iommu@15000000 {
3226                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3227                         reg = <0 0x15000000 0 0x100000>;
3228                         #iommu-cells = <2>;
3229                         #global-interrupts = <1>;
3230                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3231                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3232                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3233                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3234                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3235                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3236                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3237                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3238                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3239                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3240                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3241                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3242                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3243                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3244                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3245                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3246                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3247                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3248                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3249                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3250                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3251                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3252                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3253                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3254                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3255                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3256                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3257                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3258                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3259                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3260                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3261                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3262                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3263                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3264                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3265                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3266                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3287                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3288                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3289                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3290                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3291                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3292                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3311                 };
3312
3313                 intc: interrupt-controller@17a00000 {
3314                         compatible = "arm,gic-v3";
3315                         #address-cells = <2>;
3316                         #size-cells = <2>;
3317                         ranges;
3318                         #interrupt-cells = <3>;
3319                         interrupt-controller;
3320                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3321                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3322                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3323
3324                         msi-controller@17a40000 {
3325                                 compatible = "arm,gic-v3-its";
3326                                 msi-controller;
3327                                 #msi-cells = <1>;
3328                                 reg = <0 0x17a40000 0 0x20000>;
3329                                 status = "disabled";
3330                         };
3331                 };
3332
3333                 apss_shared: mailbox@17c00000 {
3334                         compatible = "qcom,sc7180-apss-shared";
3335                         reg = <0 0x17c00000 0 0x10000>;
3336                         #mbox-cells = <1>;
3337                 };
3338
3339                 watchdog@17c10000 {
3340                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3341                         reg = <0 0x17c10000 0 0x1000>;
3342                         clocks = <&sleep_clk>;
3343                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3344                 };
3345
3346                 timer@17c20000{
3347                         #address-cells = <2>;
3348                         #size-cells = <2>;
3349                         ranges;
3350                         compatible = "arm,armv7-timer-mem";
3351                         reg = <0 0x17c20000 0 0x1000>;
3352
3353                         frame@17c21000 {
3354                                 frame-number = <0>;
3355                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3356                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3357                                 reg = <0 0x17c21000 0 0x1000>,
3358                                       <0 0x17c22000 0 0x1000>;
3359                         };
3360
3361                         frame@17c23000 {
3362                                 frame-number = <1>;
3363                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3364                                 reg = <0 0x17c23000 0 0x1000>;
3365                                 status = "disabled";
3366                         };
3367
3368                         frame@17c25000 {
3369                                 frame-number = <2>;
3370                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3371                                 reg = <0 0x17c25000 0 0x1000>;
3372                                 status = "disabled";
3373                         };
3374
3375                         frame@17c27000 {
3376                                 frame-number = <3>;
3377                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3378                                 reg = <0 0x17c27000 0 0x1000>;
3379                                 status = "disabled";
3380                         };
3381
3382                         frame@17c29000 {
3383                                 frame-number = <4>;
3384                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3385                                 reg = <0 0x17c29000 0 0x1000>;
3386                                 status = "disabled";
3387                         };
3388
3389                         frame@17c2b000 {
3390                                 frame-number = <5>;
3391                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3392                                 reg = <0 0x17c2b000 0 0x1000>;
3393                                 status = "disabled";
3394                         };
3395
3396                         frame@17c2d000 {
3397                                 frame-number = <6>;
3398                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3399                                 reg = <0 0x17c2d000 0 0x1000>;
3400                                 status = "disabled";
3401                         };
3402                 };
3403
3404                 apps_rsc: rsc@18200000 {
3405                         compatible = "qcom,rpmh-rsc";
3406                         reg = <0 0x18200000 0 0x10000>,
3407                               <0 0x18210000 0 0x10000>,
3408                               <0 0x18220000 0 0x10000>;
3409                         reg-names = "drv-0", "drv-1", "drv-2";
3410                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3411                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3412                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3413                         qcom,tcs-offset = <0xd00>;
3414                         qcom,drv-id = <2>;
3415                         qcom,tcs-config = <ACTIVE_TCS  2>,
3416                                           <SLEEP_TCS   3>,
3417                                           <WAKE_TCS    3>,
3418                                           <CONTROL_TCS 1>;
3419
3420                         rpmhcc: clock-controller {
3421                                 compatible = "qcom,sc7180-rpmh-clk";
3422                                 clocks = <&xo_board>;
3423                                 clock-names = "xo";
3424                                 #clock-cells = <1>;
3425                         };
3426
3427                         rpmhpd: power-controller {
3428                                 compatible = "qcom,sc7180-rpmhpd";
3429                                 #power-domain-cells = <1>;
3430                                 operating-points-v2 = <&rpmhpd_opp_table>;
3431
3432                                 rpmhpd_opp_table: opp-table {
3433                                         compatible = "operating-points-v2";
3434
3435                                         rpmhpd_opp_ret: opp1 {
3436                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3437                                         };
3438
3439                                         rpmhpd_opp_min_svs: opp2 {
3440                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3441                                         };
3442
3443                                         rpmhpd_opp_low_svs: opp3 {
3444                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3445                                         };
3446
3447                                         rpmhpd_opp_svs: opp4 {
3448                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3449                                         };
3450
3451                                         rpmhpd_opp_svs_l1: opp5 {
3452                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3453                                         };
3454
3455                                         rpmhpd_opp_svs_l2: opp6 {
3456                                                 opp-level = <224>;
3457                                         };
3458
3459                                         rpmhpd_opp_nom: opp7 {
3460                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3461                                         };
3462
3463                                         rpmhpd_opp_nom_l1: opp8 {
3464                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3465                                         };
3466
3467                                         rpmhpd_opp_nom_l2: opp9 {
3468                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3469                                         };
3470
3471                                         rpmhpd_opp_turbo: opp10 {
3472                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3473                                         };
3474
3475                                         rpmhpd_opp_turbo_l1: opp11 {
3476                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3477                                         };
3478                                 };
3479                         };
3480
3481                         apps_bcm_voter: bcm_voter {
3482                                 compatible = "qcom,bcm-voter";
3483                         };
3484                 };
3485
3486                 osm_l3: interconnect@18321000 {
3487                         compatible = "qcom,sc7180-osm-l3";
3488                         reg = <0 0x18321000 0 0x1400>;
3489
3490                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3491                         clock-names = "xo", "alternate";
3492
3493                         #interconnect-cells = <1>;
3494                 };
3495
3496                 cpufreq_hw: cpufreq@18323000 {
3497                         compatible = "qcom,cpufreq-hw";
3498                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3499                         reg-names = "freq-domain0", "freq-domain1";
3500
3501                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3502                         clock-names = "xo", "alternate";
3503
3504                         #freq-domain-cells = <1>;
3505                 };
3506
3507                 wifi: wifi@18800000 {
3508                         compatible = "qcom,wcn3990-wifi";
3509                         reg = <0 0x18800000 0 0x800000>;
3510                         reg-names = "membase";
3511                         iommus = <&apps_smmu 0xc0 0x1>;
3512                         interrupts =
3513                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3514                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3515                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3516                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3517                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3518                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3519                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3520                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3521                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3522                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3523                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3524                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3525                         memory-region = <&wlan_mem>;
3526                         qcom,msa-fixed-perm;
3527                         status = "disabled";
3528                 };
3529
3530                 lpasscc: clock-controller@62d00000 {
3531                         compatible = "qcom,sc7180-lpasscorecc";
3532                         reg = <0 0x62d00000 0 0x50000>,
3533                               <0 0x62780000 0 0x30000>;
3534                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3535                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3536                                  <&rpmhcc RPMH_CXO_CLK>;
3537                         clock-names = "iface", "bi_tcxo";
3538                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3539                         #clock-cells = <1>;
3540                         #power-domain-cells = <1>;
3541                 };
3542
3543                 lpass_cpu: lpass@62d87000 {
3544                         compatible = "qcom,sc7180-lpass-cpu";
3545
3546                         reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3547                         reg-names =  "lpass-hdmiif", "lpass-lpaif";
3548
3549                         iommus = <&apps_smmu 0x1020 0>,
3550                                 <&apps_smmu 0x1021 0>,
3551                                 <&apps_smmu 0x1032 0>;
3552
3553                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3554
3555                         status = "disabled";
3556
3557                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3558                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3559                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3560                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3561                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3562                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3563
3564                         clock-names = "pcnoc-sway-clk", "audio-core",
3565                                         "mclk0", "pcnoc-mport-clk",
3566                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3567
3568
3569                         #sound-dai-cells = <1>;
3570                         #address-cells = <1>;
3571                         #size-cells = <0>;
3572
3573                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3574                                         <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3575                         interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3576                 };
3577
3578                 lpass_hm: clock-controller@63000000 {
3579                         compatible = "qcom,sc7180-lpasshm";
3580                         reg = <0 0x63000000 0 0x28>;
3581                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3582                                  <&rpmhcc RPMH_CXO_CLK>;
3583                         clock-names = "iface", "bi_tcxo";
3584                         #clock-cells = <1>;
3585                         #power-domain-cells = <1>;
3586                 };
3587         };
3588
3589         thermal-zones {
3590                 cpu0_thermal: cpu0-thermal {
3591                         polling-delay-passive = <250>;
3592                         polling-delay = <0>;
3593
3594                         thermal-sensors = <&tsens0 1>;
3595                         sustainable-power = <768>;
3596
3597                         trips {
3598                                 cpu0_alert0: trip-point0 {
3599                                         temperature = <90000>;
3600                                         hysteresis = <2000>;
3601                                         type = "passive";
3602                                 };
3603
3604                                 cpu0_alert1: trip-point1 {
3605                                         temperature = <95000>;
3606                                         hysteresis = <2000>;
3607                                         type = "passive";
3608                                 };
3609
3610                                 cpu0_crit: cpu_crit {
3611                                         temperature = <110000>;
3612                                         hysteresis = <1000>;
3613                                         type = "critical";
3614                                 };
3615                         };
3616
3617                         cooling-maps {
3618                                 map0 {
3619                                         trip = <&cpu0_alert0>;
3620                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3622                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3623                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3624                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3625                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3626                                 };
3627                                 map1 {
3628                                         trip = <&cpu0_alert1>;
3629                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3630                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3631                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3632                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3633                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3634                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3635                                 };
3636                         };
3637                 };
3638
3639                 cpu1_thermal: cpu1-thermal {
3640                         polling-delay-passive = <250>;
3641                         polling-delay = <0>;
3642
3643                         thermal-sensors = <&tsens0 2>;
3644                         sustainable-power = <768>;
3645
3646                         trips {
3647                                 cpu1_alert0: trip-point0 {
3648                                         temperature = <90000>;
3649                                         hysteresis = <2000>;
3650                                         type = "passive";
3651                                 };
3652
3653                                 cpu1_alert1: trip-point1 {
3654                                         temperature = <95000>;
3655                                         hysteresis = <2000>;
3656                                         type = "passive";
3657                                 };
3658
3659                                 cpu1_crit: cpu_crit {
3660                                         temperature = <110000>;
3661                                         hysteresis = <1000>;
3662                                         type = "critical";
3663                                 };
3664                         };
3665
3666                         cooling-maps {
3667                                 map0 {
3668                                         trip = <&cpu1_alert0>;
3669                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3670                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3672                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3673                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3674                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3675                                 };
3676                                 map1 {
3677                                         trip = <&cpu1_alert1>;
3678                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3679                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3680                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3681                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3684                                 };
3685                         };
3686                 };
3687
3688                 cpu2_thermal: cpu2-thermal {
3689                         polling-delay-passive = <250>;
3690                         polling-delay = <0>;
3691
3692                         thermal-sensors = <&tsens0 3>;
3693                         sustainable-power = <768>;
3694
3695                         trips {
3696                                 cpu2_alert0: trip-point0 {
3697                                         temperature = <90000>;
3698                                         hysteresis = <2000>;
3699                                         type = "passive";
3700                                 };
3701
3702                                 cpu2_alert1: trip-point1 {
3703                                         temperature = <95000>;
3704                                         hysteresis = <2000>;
3705                                         type = "passive";
3706                                 };
3707
3708                                 cpu2_crit: cpu_crit {
3709                                         temperature = <110000>;
3710                                         hysteresis = <1000>;
3711                                         type = "critical";
3712                                 };
3713                         };
3714
3715                         cooling-maps {
3716                                 map0 {
3717                                         trip = <&cpu2_alert0>;
3718                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3720                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3721                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3722                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3723                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3724                                 };
3725                                 map1 {
3726                                         trip = <&cpu2_alert1>;
3727                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3728                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3730                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3731                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3732                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3733                                 };
3734                         };
3735                 };
3736
3737                 cpu3_thermal: cpu3-thermal {
3738                         polling-delay-passive = <250>;
3739                         polling-delay = <0>;
3740
3741                         thermal-sensors = <&tsens0 4>;
3742                         sustainable-power = <768>;
3743
3744                         trips {
3745                                 cpu3_alert0: trip-point0 {
3746                                         temperature = <90000>;
3747                                         hysteresis = <2000>;
3748                                         type = "passive";
3749                                 };
3750
3751                                 cpu3_alert1: trip-point1 {
3752                                         temperature = <95000>;
3753                                         hysteresis = <2000>;
3754                                         type = "passive";
3755                                 };
3756
3757                                 cpu3_crit: cpu_crit {
3758                                         temperature = <110000>;
3759                                         hysteresis = <1000>;
3760                                         type = "critical";
3761                                 };
3762                         };
3763
3764                         cooling-maps {
3765                                 map0 {
3766                                         trip = <&cpu3_alert0>;
3767                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3768                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3769                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3770                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3773                                 };
3774                                 map1 {
3775                                         trip = <&cpu3_alert1>;
3776                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3780                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3781                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3782                                 };
3783                         };
3784                 };
3785
3786                 cpu4_thermal: cpu4-thermal {
3787                         polling-delay-passive = <250>;
3788                         polling-delay = <0>;
3789
3790                         thermal-sensors = <&tsens0 5>;
3791                         sustainable-power = <768>;
3792
3793                         trips {
3794                                 cpu4_alert0: trip-point0 {
3795                                         temperature = <90000>;
3796                                         hysteresis = <2000>;
3797                                         type = "passive";
3798                                 };
3799
3800                                 cpu4_alert1: trip-point1 {
3801                                         temperature = <95000>;
3802                                         hysteresis = <2000>;
3803                                         type = "passive";
3804                                 };
3805
3806                                 cpu4_crit: cpu_crit {
3807                                         temperature = <110000>;
3808                                         hysteresis = <1000>;
3809                                         type = "critical";
3810                                 };
3811                         };
3812
3813                         cooling-maps {
3814                                 map0 {
3815                                         trip = <&cpu4_alert0>;
3816                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3817                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3820                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3821                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3822                                 };
3823                                 map1 {
3824                                         trip = <&cpu4_alert1>;
3825                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3826                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3828                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3829                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3830                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3831                                 };
3832                         };
3833                 };
3834
3835                 cpu5_thermal: cpu5-thermal {
3836                         polling-delay-passive = <250>;
3837                         polling-delay = <0>;
3838
3839                         thermal-sensors = <&tsens0 6>;
3840                         sustainable-power = <768>;
3841
3842                         trips {
3843                                 cpu5_alert0: trip-point0 {
3844                                         temperature = <90000>;
3845                                         hysteresis = <2000>;
3846                                         type = "passive";
3847                                 };
3848
3849                                 cpu5_alert1: trip-point1 {
3850                                         temperature = <95000>;
3851                                         hysteresis = <2000>;
3852                                         type = "passive";
3853                                 };
3854
3855                                 cpu5_crit: cpu_crit {
3856                                         temperature = <110000>;
3857                                         hysteresis = <1000>;
3858                                         type = "critical";
3859                                 };
3860                         };
3861
3862                         cooling-maps {
3863                                 map0 {
3864                                         trip = <&cpu5_alert0>;
3865                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3866                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3869                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3870                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3871                                 };
3872                                 map1 {
3873                                         trip = <&cpu5_alert1>;
3874                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3875                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3876                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3878                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3879                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3880                                 };
3881                         };
3882                 };
3883
3884                 cpu6_thermal: cpu6-thermal {
3885                         polling-delay-passive = <250>;
3886                         polling-delay = <0>;
3887
3888                         thermal-sensors = <&tsens0 9>;
3889                         sustainable-power = <1202>;
3890
3891                         trips {
3892                                 cpu6_alert0: trip-point0 {
3893                                         temperature = <90000>;
3894                                         hysteresis = <2000>;
3895                                         type = "passive";
3896                                 };
3897
3898                                 cpu6_alert1: trip-point1 {
3899                                         temperature = <95000>;
3900                                         hysteresis = <2000>;
3901                                         type = "passive";
3902                                 };
3903
3904                                 cpu6_crit: cpu_crit {
3905                                         temperature = <110000>;
3906                                         hysteresis = <1000>;
3907                                         type = "critical";
3908                                 };
3909                         };
3910
3911                         cooling-maps {
3912                                 map0 {
3913                                         trip = <&cpu6_alert0>;
3914                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3915                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3916                                 };
3917                                 map1 {
3918                                         trip = <&cpu6_alert1>;
3919                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3920                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3921                                 };
3922                         };
3923                 };
3924
3925                 cpu7_thermal: cpu7-thermal {
3926                         polling-delay-passive = <250>;
3927                         polling-delay = <0>;
3928
3929                         thermal-sensors = <&tsens0 10>;
3930                         sustainable-power = <1202>;
3931
3932                         trips {
3933                                 cpu7_alert0: trip-point0 {
3934                                         temperature = <90000>;
3935                                         hysteresis = <2000>;
3936                                         type = "passive";
3937                                 };
3938
3939                                 cpu7_alert1: trip-point1 {
3940                                         temperature = <95000>;
3941                                         hysteresis = <2000>;
3942                                         type = "passive";
3943                                 };
3944
3945                                 cpu7_crit: cpu_crit {
3946                                         temperature = <110000>;
3947                                         hysteresis = <1000>;
3948                                         type = "critical";
3949                                 };
3950                         };
3951
3952                         cooling-maps {
3953                                 map0 {
3954                                         trip = <&cpu7_alert0>;
3955                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3956                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3957                                 };
3958                                 map1 {
3959                                         trip = <&cpu7_alert1>;
3960                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3961                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3962                                 };
3963                         };
3964                 };
3965
3966                 cpu8_thermal: cpu8-thermal {
3967                         polling-delay-passive = <250>;
3968                         polling-delay = <0>;
3969
3970                         thermal-sensors = <&tsens0 11>;
3971                         sustainable-power = <1202>;
3972
3973                         trips {
3974                                 cpu8_alert0: trip-point0 {
3975                                         temperature = <90000>;
3976                                         hysteresis = <2000>;
3977                                         type = "passive";
3978                                 };
3979
3980                                 cpu8_alert1: trip-point1 {
3981                                         temperature = <95000>;
3982                                         hysteresis = <2000>;
3983                                         type = "passive";
3984                                 };
3985
3986                                 cpu8_crit: cpu_crit {
3987                                         temperature = <110000>;
3988                                         hysteresis = <1000>;
3989                                         type = "critical";
3990                                 };
3991                         };
3992
3993                         cooling-maps {
3994                                 map0 {
3995                                         trip = <&cpu8_alert0>;
3996                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3998                                 };
3999                                 map1 {
4000                                         trip = <&cpu8_alert1>;
4001                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4002                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4003                                 };
4004                         };
4005                 };
4006
4007                 cpu9_thermal: cpu9-thermal {
4008                         polling-delay-passive = <250>;
4009                         polling-delay = <0>;
4010
4011                         thermal-sensors = <&tsens0 12>;
4012                         sustainable-power = <1202>;
4013
4014                         trips {
4015                                 cpu9_alert0: trip-point0 {
4016                                         temperature = <90000>;
4017                                         hysteresis = <2000>;
4018                                         type = "passive";
4019                                 };
4020
4021                                 cpu9_alert1: trip-point1 {
4022                                         temperature = <95000>;
4023                                         hysteresis = <2000>;
4024                                         type = "passive";
4025                                 };
4026
4027                                 cpu9_crit: cpu_crit {
4028                                         temperature = <110000>;
4029                                         hysteresis = <1000>;
4030                                         type = "critical";
4031                                 };
4032                         };
4033
4034                         cooling-maps {
4035                                 map0 {
4036                                         trip = <&cpu9_alert0>;
4037                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4038                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4039                                 };
4040                                 map1 {
4041                                         trip = <&cpu9_alert1>;
4042                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4043                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4044                                 };
4045                         };
4046                 };
4047
4048                 aoss0-thermal {
4049                         polling-delay-passive = <250>;
4050                         polling-delay = <0>;
4051
4052                         thermal-sensors = <&tsens0 0>;
4053
4054                         trips {
4055                                 aoss0_alert0: trip-point0 {
4056                                         temperature = <90000>;
4057                                         hysteresis = <2000>;
4058                                         type = "hot";
4059                                 };
4060
4061                                 aoss0_crit: aoss0_crit {
4062                                         temperature = <110000>;
4063                                         hysteresis = <2000>;
4064                                         type = "critical";
4065                                 };
4066                         };
4067                 };
4068
4069                 cpuss0-thermal {
4070                         polling-delay-passive = <250>;
4071                         polling-delay = <0>;
4072
4073                         thermal-sensors = <&tsens0 7>;
4074
4075                         trips {
4076                                 cpuss0_alert0: trip-point0 {
4077                                         temperature = <90000>;
4078                                         hysteresis = <2000>;
4079                                         type = "hot";
4080                                 };
4081                                 cpuss0_crit: cluster0_crit {
4082                                         temperature = <110000>;
4083                                         hysteresis = <2000>;
4084                                         type = "critical";
4085                                 };
4086                         };
4087                 };
4088
4089                 cpuss1-thermal {
4090                         polling-delay-passive = <250>;
4091                         polling-delay = <0>;
4092
4093                         thermal-sensors = <&tsens0 8>;
4094
4095                         trips {
4096                                 cpuss1_alert0: trip-point0 {
4097                                         temperature = <90000>;
4098                                         hysteresis = <2000>;
4099                                         type = "hot";
4100                                 };
4101                                 cpuss1_crit: cluster0_crit {
4102                                         temperature = <110000>;
4103                                         hysteresis = <2000>;
4104                                         type = "critical";
4105                                 };
4106                         };
4107                 };
4108
4109                 gpuss0-thermal {
4110                         polling-delay-passive = <250>;
4111                         polling-delay = <0>;
4112
4113                         thermal-sensors = <&tsens0 13>;
4114
4115                         trips {
4116                                 gpuss0_alert0: trip-point0 {
4117                                         temperature = <95000>;
4118                                         hysteresis = <2000>;
4119                                         type = "passive";
4120                                 };
4121
4122                                 gpuss0_crit: gpuss0_crit {
4123                                         temperature = <110000>;
4124                                         hysteresis = <2000>;
4125                                         type = "critical";
4126                                 };
4127                         };
4128
4129                         cooling-maps {
4130                                 map0 {
4131                                         trip = <&gpuss0_alert0>;
4132                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4133                                 };
4134                         };
4135                 };
4136
4137                 gpuss1-thermal {
4138                         polling-delay-passive = <250>;
4139                         polling-delay = <0>;
4140
4141                         thermal-sensors = <&tsens0 14>;
4142
4143                         trips {
4144                                 gpuss1_alert0: trip-point0 {
4145                                         temperature = <95000>;
4146                                         hysteresis = <2000>;
4147                                         type = "passive";
4148                                 };
4149
4150                                 gpuss1_crit: gpuss1_crit {
4151                                         temperature = <110000>;
4152                                         hysteresis = <2000>;
4153                                         type = "critical";
4154                                 };
4155                         };
4156
4157                         cooling-maps {
4158                                 map0 {
4159                                         trip = <&gpuss1_alert0>;
4160                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4161                                 };
4162                         };
4163                 };
4164
4165                 aoss1-thermal {
4166                         polling-delay-passive = <250>;
4167                         polling-delay = <0>;
4168
4169                         thermal-sensors = <&tsens1 0>;
4170
4171                         trips {
4172                                 aoss1_alert0: trip-point0 {
4173                                         temperature = <90000>;
4174                                         hysteresis = <2000>;
4175                                         type = "hot";
4176                                 };
4177
4178                                 aoss1_crit: aoss1_crit {
4179                                         temperature = <110000>;
4180                                         hysteresis = <2000>;
4181                                         type = "critical";
4182                                 };
4183                         };
4184                 };
4185
4186                 cwlan-thermal {
4187                         polling-delay-passive = <250>;
4188                         polling-delay = <0>;
4189
4190                         thermal-sensors = <&tsens1 1>;
4191
4192                         trips {
4193                                 cwlan_alert0: trip-point0 {
4194                                         temperature = <90000>;
4195                                         hysteresis = <2000>;
4196                                         type = "hot";
4197                                 };
4198
4199                                 cwlan_crit: cwlan_crit {
4200                                         temperature = <110000>;
4201                                         hysteresis = <2000>;
4202                                         type = "critical";
4203                                 };
4204                         };
4205                 };
4206
4207                 audio-thermal {
4208                         polling-delay-passive = <250>;
4209                         polling-delay = <0>;
4210
4211                         thermal-sensors = <&tsens1 2>;
4212
4213                         trips {
4214                                 audio_alert0: trip-point0 {
4215                                         temperature = <90000>;
4216                                         hysteresis = <2000>;
4217                                         type = "hot";
4218                                 };
4219
4220                                 audio_crit: audio_crit {
4221                                         temperature = <110000>;
4222                                         hysteresis = <2000>;
4223                                         type = "critical";
4224                                 };
4225                         };
4226                 };
4227
4228                 ddr-thermal {
4229                         polling-delay-passive = <250>;
4230                         polling-delay = <0>;
4231
4232                         thermal-sensors = <&tsens1 3>;
4233
4234                         trips {
4235                                 ddr_alert0: trip-point0 {
4236                                         temperature = <90000>;
4237                                         hysteresis = <2000>;
4238                                         type = "hot";
4239                                 };
4240
4241                                 ddr_crit: ddr_crit {
4242                                         temperature = <110000>;
4243                                         hysteresis = <2000>;
4244                                         type = "critical";
4245                                 };
4246                         };
4247                 };
4248
4249                 q6-hvx-thermal {
4250                         polling-delay-passive = <250>;
4251                         polling-delay = <0>;
4252
4253                         thermal-sensors = <&tsens1 4>;
4254
4255                         trips {
4256                                 q6_hvx_alert0: trip-point0 {
4257                                         temperature = <90000>;
4258                                         hysteresis = <2000>;
4259                                         type = "hot";
4260                                 };
4261
4262                                 q6_hvx_crit: q6_hvx_crit {
4263                                         temperature = <110000>;
4264                                         hysteresis = <2000>;
4265                                         type = "critical";
4266                                 };
4267                         };
4268                 };
4269
4270                 camera-thermal {
4271                         polling-delay-passive = <250>;
4272                         polling-delay = <0>;
4273
4274                         thermal-sensors = <&tsens1 5>;
4275
4276                         trips {
4277                                 camera_alert0: trip-point0 {
4278                                         temperature = <90000>;
4279                                         hysteresis = <2000>;
4280                                         type = "hot";
4281                                 };
4282
4283                                 camera_crit: camera_crit {
4284                                         temperature = <110000>;
4285                                         hysteresis = <2000>;
4286                                         type = "critical";
4287                                 };
4288                         };
4289                 };
4290
4291                 mdm-core-thermal {
4292                         polling-delay-passive = <250>;
4293                         polling-delay = <0>;
4294
4295                         thermal-sensors = <&tsens1 6>;
4296
4297                         trips {
4298                                 mdm_alert0: trip-point0 {
4299                                         temperature = <90000>;
4300                                         hysteresis = <2000>;
4301                                         type = "hot";
4302                                 };
4303
4304                                 mdm_crit: mdm_crit {
4305                                         temperature = <110000>;
4306                                         hysteresis = <2000>;
4307                                         type = "critical";
4308                                 };
4309                         };
4310                 };
4311
4312                 mdm-dsp-thermal {
4313                         polling-delay-passive = <250>;
4314                         polling-delay = <0>;
4315
4316                         thermal-sensors = <&tsens1 7>;
4317
4318                         trips {
4319                                 mdm_dsp_alert0: trip-point0 {
4320                                         temperature = <90000>;
4321                                         hysteresis = <2000>;
4322                                         type = "hot";
4323                                 };
4324
4325                                 mdm_dsp_crit: mdm_dsp_crit {
4326                                         temperature = <110000>;
4327                                         hysteresis = <2000>;
4328                                         type = "critical";
4329                                 };
4330                         };
4331                 };
4332
4333                 npu-thermal {
4334                         polling-delay-passive = <250>;
4335                         polling-delay = <0>;
4336
4337                         thermal-sensors = <&tsens1 8>;
4338
4339                         trips {
4340                                 npu_alert0: trip-point0 {
4341                                         temperature = <90000>;
4342                                         hysteresis = <2000>;
4343                                         type = "hot";
4344                                 };
4345
4346                                 npu_crit: npu_crit {
4347                                         temperature = <110000>;
4348                                         hysteresis = <2000>;
4349                                         type = "critical";
4350                                 };
4351                         };
4352                 };
4353
4354                 video-thermal {
4355                         polling-delay-passive = <250>;
4356                         polling-delay = <0>;
4357
4358                         thermal-sensors = <&tsens1 9>;
4359
4360                         trips {
4361                                 video_alert0: trip-point0 {
4362                                         temperature = <90000>;
4363                                         hysteresis = <2000>;
4364                                         type = "hot";
4365                                 };
4366
4367                                 video_crit: video_crit {
4368                                         temperature = <110000>;
4369                                         hysteresis = <2000>;
4370                                         type = "critical";
4371                                 };
4372                         };
4373                 };
4374         };
4375
4376         timer {
4377                 compatible = "arm,armv8-timer";
4378                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4379                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4380                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4381                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4382         };
4383 };