arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2020 Compass Electronics Group, LLC
   4  */
   5
   6 / {
   7         aliases {
   8                 rtc0 = &rtc;
   9                 rtc1 = &snvs_rtc;
  10                 spi0 = &flexspi;
  11         };
  12
  13         usdhc1_pwrseq: usdhc1_pwrseq {
  14                 compatible = "mmc-pwrseq-simple";
  15                 pinctrl-names = "default";
  16                 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  17                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  18                 clocks = <&osc_32k>;
  19                 clock-names = "ext_clock";
  20                 post-power-on-delay-ms = <80>;
  21         };
  22
  23         memory@40000000 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x40000000 0 0x80000000>;
  26         };
  27 };
  28
  29 &A53_0 {
  30         cpu-supply = <&buck2_reg>;
  31 };
  32
  33 &A53_1 {
  34         cpu-supply = <&buck2_reg>;
  35 };
  36
  37 &A53_2 {
  38         cpu-supply = <&buck2_reg>;
  39 };
  40
  41 &A53_3 {
  42         cpu-supply = <&buck2_reg>;
  43 };
  44
  45 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
  46 &a53_opp_table {
  47         opp-1200000000 {
  48                 opp-microvolt = <950000>;
  49         };
  50 };
  51
  52 &ddrc {
  53         operating-points-v2 = <&ddrc_opp_table>;
  54
  55         ddrc_opp_table: opp-table {
  56                 compatible = "operating-points-v2";
  57
  58                 opp-25M {
  59                         opp-hz = /bits/ 64 <25000000>;
  60                 };
  61
  62                 opp-100M {
  63                         opp-hz = /bits/ 64 <100000000>;
  64                 };
  65
  66                 opp-800M {
  67                         opp-hz = /bits/ 64 <800000000>;
  68                 };
  69         };
  70 };
  71
  72 &fec1 {
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_fec1>;
  75         phy-mode = "rgmii-id";
  76         phy-handle = <&ethphy0>;
  77         phy-supply = <&buck6_reg>;
  78         phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  79         fsl,magic-packet;
  80         status = "okay";
  81
  82         mdio {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 ethphy0: ethernet-phy@0 {
  87                         compatible = "ethernet-phy-ieee802.3-c22";
  88                         reg = <0>;
  89                 };
  90         };
  91 };
  92
  93 &flexspi {
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&pinctrl_flexspi>;
  96         status = "okay";
  97
  98         flash@0 {
  99                 reg = <0>;
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "jedec,spi-nor";
 103                 spi-max-frequency = <80000000>;
 104                 spi-tx-bus-width = <4>;
 105                 spi-rx-bus-width = <4>;
 106         };
 107 };
 108
 109 &i2c1 {
 110         clock-frequency = <400000>;
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_i2c1>;
 113         status = "okay";
 114
 115         pmic@4b {
 116                 compatible = "rohm,bd71847";
 117                 reg = <0x4b>;
 118                 pinctrl-names = "default";
 119                 pinctrl-0 = <&pinctrl_pmic>;
 120                 interrupt-parent = <&gpio1>;
 121                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 122                 rohm,reset-snvs-powered;
 123
 124                 regulators {
 125                         buck1_reg: BUCK1 {
 126                                 regulator-name = "buck1";
 127                                 regulator-min-microvolt = <700000>;
 128                                 regulator-max-microvolt = <1300000>;
 129                                 regulator-boot-on;
 130                                 regulator-always-on;
 131                                 regulator-ramp-delay = <1250>;
 132                         };
 133
 134                         buck2_reg: BUCK2 {
 135                                 regulator-name = "buck2";
 136                                 regulator-min-microvolt = <700000>;
 137                                 regulator-max-microvolt = <1300000>;
 138                                 regulator-boot-on;
 139                                 regulator-always-on;
 140                                 regulator-ramp-delay = <1250>;
 141                                 rohm,dvs-run-voltage = <1000000>;
 142                                 rohm,dvs-idle-voltage = <900000>;
 143                         };
 144
 145                         buck3_reg: BUCK3 {
 146                                 // BUCK5 in datasheet
 147                                 regulator-name = "buck3";
 148                                 regulator-min-microvolt = <700000>;
 149                                 regulator-max-microvolt = <1350000>;
 150                                 regulator-boot-on;
 151                                 regulator-always-on;
 152                         };
 153
 154                         buck4_reg: BUCK4 {
 155                                 // BUCK6 in datasheet
 156                                 regulator-name = "buck4";
 157                                 regulator-min-microvolt = <3000000>;
 158                                 regulator-max-microvolt = <3300000>;
 159                                 regulator-boot-on;
 160                                 regulator-always-on;
 161                         };
 162
 163                         buck5_reg: BUCK5 {
 164                                 // BUCK7 in datasheet
 165                                 regulator-name = "buck5";
 166                                 regulator-min-microvolt = <1605000>;
 167                                 regulator-max-microvolt = <1995000>;
 168                                 regulator-boot-on;
 169                                 regulator-always-on;
 170                         };
 171
 172                         buck6_reg: BUCK6 {
 173                                 // BUCK8 in datasheet
 174                                 regulator-name = "buck6";
 175                                 regulator-min-microvolt = <800000>;
 176                                 regulator-max-microvolt = <1400000>;
 177                                 regulator-boot-on;
 178                                 regulator-always-on;
 179                         };
 180
 181                         ldo1_reg: LDO1 {
 182                                 regulator-name = "ldo1";
 183                                 regulator-min-microvolt = <1600000>;
 184                                 regulator-max-microvolt = <3300000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                         };
 188
 189                         ldo2_reg: LDO2 {
 190                                 regulator-name = "ldo2";
 191                                 regulator-min-microvolt = <800000>;
 192                                 regulator-max-microvolt = <900000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         ldo3_reg: LDO3 {
 198                                 regulator-name = "ldo3";
 199                                 regulator-min-microvolt = <1800000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         ldo4_reg: LDO4 {
 206                                 regulator-name = "ldo4";
 207                                 regulator-min-microvolt = <900000>;
 208                                 regulator-max-microvolt = <1800000>;
 209                                 regulator-boot-on;
 210                                 regulator-always-on;
 211                         };
 212
 213                         ldo6_reg: LDO6 {
 214                                 regulator-name = "ldo6";
 215                                 regulator-min-microvolt = <900000>;
 216                                 regulator-max-microvolt = <1800000>;
 217                                 regulator-boot-on;
 218                                 regulator-always-on;
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &i2c3 {
 225         clock-frequency = <400000>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_i2c3>;
 228         status = "okay";
 229
 230         eeprom@50 {
 231                 compatible = "microchip,24c64", "atmel,24c64";
 232                 pagesize = <32>;
 233                 read-only;      /* Manufacturing EEPROM programmed at factory */
 234                 reg = <0x50>;
 235         };
 236
 237         rtc: rtc@51 {
 238                 compatible = "nxp,pcf85263";
 239                 reg = <0x51>;
 240         };
 241 };
 242
 243 &uart1 {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_uart1>;
 246         assigned-clocks = <&clk IMX8MN_CLK_UART1>;
 247         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 248         uart-has-rtscts;
 249         status = "okay";
 250
 251         bluetooth {
 252                 compatible = "brcm,bcm43438-bt";
 253                 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 254                 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 255                 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 256                 clocks = <&osc_32k>;
 257                 max-speed = <4000000>;
 258                 clock-names = "extclk";
 259         };
 260 };
 261
 262 &usdhc1 {
 263         #address-cells = <1>;
 264         #size-cells = <0>;
 265         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 266         pinctrl-0 = <&pinctrl_usdhc1>;
 267         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 268         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 269         vmmc-supply = <&buck4_reg>;
 270         vqmmc-supply = <&buck5_reg>;
 271         bus-width = <4>;
 272         non-removable;
 273         cap-power-off-card;
 274         pm-ignore-notify;
 275         keep-power-in-suspend;
 276         mmc-pwrseq = <&usdhc1_pwrseq>;
 277         status = "okay";
 278
 279         brcmf: bcrmf@1 {
 280                 reg = <1>;
 281                 compatible = "brcm,bcm4329-fmac";
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&pinctrl_wlan>;
 284                 interrupt-parent = <&gpio2>;
 285                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 286                 interrupt-names = "host-wake";
 287         };
 288 };
 289
 290 &usdhc3 {
 291         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 292         pinctrl-0 = <&pinctrl_usdhc3>;
 293         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 294         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 295         bus-width = <8>;
 296         non-removable;
 297         status = "okay";
 298 };
 299
 300 &wdog1 {
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_wdog>;
 303         fsl,ext-reset-output;
 304         status = "okay";
 305 };
 306
 307 &iomuxc {
 308         pinctrl_fec1: fec1grp {
 309                 fsl,pins = <
 310                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 311                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 312                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 313                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 314                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 315                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 316                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 317                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 318                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 319                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 320                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 321                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 322                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 323                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 324                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 325                 >;
 326         };
 327
 328         pinctrl_i2c1: i2c1grp {
 329                 fsl,pins = <
 330                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 331                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 332                 >;
 333         };
 334
 335         pinctrl_i2c3: i2c3grp {
 336                 fsl,pins = <
 337                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 338                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 339                 >;
 340         };
 341
 342         pinctrl_flexspi: flexspigrp {
 343                 fsl,pins = <
 344                         MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
 345                         MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
 346                         MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
 347                         MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
 348                         MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
 349                         MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
 350                 >;
 351         };
 352
 353         pinctrl_pmic: pmicirqgrp {
 354                 fsl,pins = <
 355                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x141
 356                 >;
 357         };
 358
 359         pinctrl_uart1: uart1grp {
 360                 fsl,pins = <
 361                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 362                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 363                         MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 364                         MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 365                         MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
 366                         MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
 367                         MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
 368                         MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
 369                 >;
 370         };
 371
 372         pinctrl_usdhc1_gpio: usdhc1gpiogrp {
 373                 fsl,pins = <
 374                         MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
 375                 >;
 376         };
 377
 378         pinctrl_usdhc1: usdhc1grp {
 379                 fsl,pins = <
 380                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 381                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 382                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 383                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 384                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 385                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 386                 >;
 387         };
 388
 389         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 390                 fsl,pins = <
 391                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 392                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 393                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 394                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 395                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 396                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 397                 >;
 398         };
 399
 400         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 401                 fsl,pins = <
 402                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 403                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 404                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 405                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 406                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 407                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 408                 >;
 409         };
 410
 411         pinctrl_usdhc3: usdhc3grp {
 412                 fsl,pins = <
 413                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 414                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 415                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 416                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 417                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 418                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 419                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 420                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 421                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 422                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 423                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 424                 >;
 425         };
 426
 427         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 428                 fsl,pins = <
 429                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
 430                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 431                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 432                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 433                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 434                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 435                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 436                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 437                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 438                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 439                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 440                 >;
 441         };
 442
 443         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 444                 fsl,pins = <
 445                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
 446                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 447                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 448                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 449                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 450                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 451                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 452                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 453                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 454                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 455                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 456                 >;
 457         };
 458
 459         pinctrl_wdog: wdoggrp {
 460                 fsl,pins = <
 461                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 462                 >;
 463         };
 464
 465         pinctrl_wlan: wlangrp {
 466                 fsl,pins = <
 467                         MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
 468                 >;
 469         };
 470 };