arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2020 Compass Electronics Group, LLC
   4  */
   5
   6 #include "imx8mn-overdrive.dtsi"
   7
   8 / {
   9         aliases {
  10                 rtc0 = &rtc;
  11                 rtc1 = &snvs_rtc;
  12                 spi0 = &flexspi;
  13         };
  14
  15         usdhc1_pwrseq: usdhc1_pwrseq {
  16                 compatible = "mmc-pwrseq-simple";
  17                 pinctrl-names = "default";
  18                 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  19                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  20                 clocks = <&osc_32k>;
  21                 clock-names = "ext_clock";
  22                 post-power-on-delay-ms = <80>;
  23         };
  24
  25         memory@40000000 {
  26                 device_type = "memory";
  27                 reg = <0x0 0x40000000 0 0x80000000>;
  28         };
  29 };
  30
  31 &A53_0 {
  32         cpu-supply = <&buck2_reg>;
  33 };
  34
  35 &A53_1 {
  36         cpu-supply = <&buck2_reg>;
  37 };
  38
  39 &A53_2 {
  40         cpu-supply = <&buck2_reg>;
  41 };
  42
  43 &A53_3 {
  44         cpu-supply = <&buck2_reg>;
  45 };
  46
  47 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
  48 &a53_opp_table {
  49         opp-1200000000 {
  50                 opp-microvolt = <950000>;
  51         };
  52 };
  53
  54 &ddrc {
  55         operating-points-v2 = <&ddrc_opp_table>;
  56
  57         ddrc_opp_table: opp-table {
  58                 compatible = "operating-points-v2";
  59
  60                 opp-25000000 {
  61                         opp-hz = /bits/ 64 <25000000>;
  62                 };
  63
  64                 opp-100000000 {
  65                         opp-hz = /bits/ 64 <100000000>;
  66                 };
  67
  68                 opp-800000000 {
  69                         opp-hz = /bits/ 64 <800000000>;
  70                 };
  71         };
  72 };
  73
  74 &fec1 {
  75         pinctrl-names = "default";
  76         pinctrl-0 = <&pinctrl_fec1>;
  77         phy-mode = "rgmii-id";
  78         phy-handle = <&ethphy0>;
  79         phy-supply = <&buck6_reg>;
  80         phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  81         fsl,magic-packet;
  82         status = "okay";
  83
  84         mdio {
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87
  88                 ethphy0: ethernet-phy@0 {
  89                         compatible = "ethernet-phy-ieee802.3-c22";
  90                         reg = <0>;
  91                 };
  92         };
  93 };
  94
  95 &flexspi {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_flexspi>;
  98         status = "okay";
  99
 100         flash@0 {
 101                 reg = <0>;
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "jedec,spi-nor";
 105                 spi-max-frequency = <80000000>;
 106                 spi-tx-bus-width = <1>;
 107                 spi-rx-bus-width = <4>;
 108         };
 109 };
 110
 111 &i2c1 {
 112         clock-frequency = <400000>;
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_i2c1>;
 115         status = "okay";
 116
 117         pmic@4b {
 118                 compatible = "rohm,bd71847";
 119                 reg = <0x4b>;
 120                 pinctrl-names = "default";
 121                 pinctrl-0 = <&pinctrl_pmic>;
 122                 interrupt-parent = <&gpio1>;
 123                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 124                 rohm,reset-snvs-powered;
 125                 #clock-cells = <0>;
 126                 clocks = <&osc_32k>;
 127                 clock-output-names = "clk-32k-out";
 128
 129                 regulators {
 130                         buck1_reg: BUCK1 {
 131                                 regulator-name = "buck1";
 132                                 regulator-min-microvolt = <700000>;
 133                                 regulator-max-microvolt = <1300000>;
 134                                 regulator-boot-on;
 135                                 regulator-always-on;
 136                                 regulator-ramp-delay = <1250>;
 137                         };
 138
 139                         buck2_reg: BUCK2 {
 140                                 regulator-name = "buck2";
 141                                 regulator-min-microvolt = <700000>;
 142                                 regulator-max-microvolt = <1300000>;
 143                                 regulator-boot-on;
 144                                 regulator-always-on;
 145                                 regulator-ramp-delay = <1250>;
 146                                 rohm,dvs-run-voltage = <1000000>;
 147                                 rohm,dvs-idle-voltage = <900000>;
 148                         };
 149
 150                         buck3_reg: BUCK3 {
 151                                 // BUCK5 in datasheet
 152                                 regulator-name = "buck3";
 153                                 regulator-min-microvolt = <700000>;
 154                                 regulator-max-microvolt = <1350000>;
 155                                 regulator-boot-on;
 156                                 regulator-always-on;
 157                         };
 158
 159                         buck4_reg: BUCK4 {
 160                                 // BUCK6 in datasheet
 161                                 regulator-name = "buck4";
 162                                 regulator-min-microvolt = <3000000>;
 163                                 regulator-max-microvolt = <3300000>;
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                         };
 167
 168                         buck5_reg: BUCK5 {
 169                                 // BUCK7 in datasheet
 170                                 regulator-name = "buck5";
 171                                 regulator-min-microvolt = <1605000>;
 172                                 regulator-max-microvolt = <1995000>;
 173                                 regulator-boot-on;
 174                                 regulator-always-on;
 175                         };
 176
 177                         buck6_reg: BUCK6 {
 178                                 // BUCK8 in datasheet
 179                                 regulator-name = "buck6";
 180                                 regulator-min-microvolt = <800000>;
 181                                 regulator-max-microvolt = <1400000>;
 182                                 regulator-boot-on;
 183                                 regulator-always-on;
 184                         };
 185
 186                         ldo1_reg: LDO1 {
 187                                 regulator-name = "ldo1";
 188                                 regulator-min-microvolt = <1600000>;
 189                                 regulator-max-microvolt = <3300000>;
 190                                 regulator-boot-on;
 191                                 regulator-always-on;
 192                         };
 193
 194                         ldo2_reg: LDO2 {
 195                                 regulator-name = "ldo2";
 196                                 regulator-min-microvolt = <800000>;
 197                                 regulator-max-microvolt = <900000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         ldo3_reg: LDO3 {
 203                                 regulator-name = "ldo3";
 204                                 regulator-min-microvolt = <1800000>;
 205                                 regulator-max-microvolt = <3300000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         ldo4_reg: LDO4 {
 211                                 regulator-name = "ldo4";
 212                                 regulator-min-microvolt = <900000>;
 213                                 regulator-max-microvolt = <1800000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         ldo6_reg: LDO6 {
 219                                 regulator-name = "ldo6";
 220                                 regulator-min-microvolt = <900000>;
 221                                 regulator-max-microvolt = <1800000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225                 };
 226         };
 227 };
 228
 229 &i2c3 {
 230         clock-frequency = <400000>;
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_i2c3>;
 233         status = "okay";
 234
 235         eeprom@50 {
 236                 compatible = "microchip,24c64", "atmel,24c64";
 237                 pagesize = <32>;
 238                 read-only;      /* Manufacturing EEPROM programmed at factory */
 239                 reg = <0x50>;
 240         };
 241
 242         rtc: rtc@51 {
 243                 compatible = "nxp,pcf85263";
 244                 reg = <0x51>;
 245         };
 246 };
 247
 248 &uart1 {
 249         pinctrl-names = "default";
 250         pinctrl-0 = <&pinctrl_uart1>;
 251         assigned-clocks = <&clk IMX8MN_CLK_UART1>;
 252         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 253         uart-has-rtscts;
 254         status = "okay";
 255
 256         bluetooth {
 257                 compatible = "brcm,bcm43438-bt";
 258                 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 259                 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 260                 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 261                 clocks = <&osc_32k>;
 262                 max-speed = <4000000>;
 263                 clock-names = "extclk";
 264         };
 265 };
 266
 267 &usdhc1 {
 268         #address-cells = <1>;
 269         #size-cells = <0>;
 270         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 271         pinctrl-0 = <&pinctrl_usdhc1>;
 272         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 273         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 274         vmmc-supply = <&buck4_reg>;
 275         vqmmc-supply = <&buck5_reg>;
 276         bus-width = <4>;
 277         non-removable;
 278         cap-power-off-card;
 279         keep-power-in-suspend;
 280         mmc-pwrseq = <&usdhc1_pwrseq>;
 281         status = "okay";
 282
 283         brcmf: bcrmf@1 {
 284                 reg = <1>;
 285                 compatible = "brcm,bcm4329-fmac";
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&pinctrl_wlan>;
 288                 interrupt-parent = <&gpio2>;
 289                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 290                 interrupt-names = "host-wake";
 291         };
 292 };
 293
 294 &usdhc3 {
 295         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 296         pinctrl-0 = <&pinctrl_usdhc3>;
 297         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 298         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 299         bus-width = <8>;
 300         non-removable;
 301         status = "okay";
 302 };
 303
 304 &wdog1 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_wdog>;
 307         fsl,ext-reset-output;
 308         status = "okay";
 309 };
 310
 311 &iomuxc {
 312         pinctrl_fec1: fec1grp {
 313                 fsl,pins = <
 314                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 315                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 316                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 317                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 318                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 319                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 320                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 321                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 322                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 323                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 324                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 325                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 326                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 327                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 328                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 329                 >;
 330         };
 331
 332         pinctrl_i2c1: i2c1grp {
 333                 fsl,pins = <
 334                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 335                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 336                 >;
 337         };
 338
 339         pinctrl_i2c3: i2c3grp {
 340                 fsl,pins = <
 341                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 342                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 343                 >;
 344         };
 345
 346         pinctrl_flexspi: flexspigrp {
 347                 fsl,pins = <
 348                         MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
 349                         MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
 350                         MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
 351                         MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
 352                         MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
 353                         MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
 354                 >;
 355         };
 356
 357         pinctrl_pmic: pmicirqgrp {
 358                 fsl,pins = <
 359                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x141
 360                 >;
 361         };
 362
 363         pinctrl_uart1: uart1grp {
 364                 fsl,pins = <
 365                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 366                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 367                         MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 368                         MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 369                         MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
 370                         MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
 371                         MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
 372                         MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
 373                 >;
 374         };
 375
 376         pinctrl_usdhc1_gpio: usdhc1gpiogrp {
 377                 fsl,pins = <
 378                         MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
 379                 >;
 380         };
 381
 382         pinctrl_usdhc1: usdhc1grp {
 383                 fsl,pins = <
 384                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 385                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 386                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 387                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 388                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 389                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 390                 >;
 391         };
 392
 393         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 394                 fsl,pins = <
 395                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 396                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 397                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 398                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 399                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 400                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 401                 >;
 402         };
 403
 404         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 405                 fsl,pins = <
 406                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 407                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 408                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 409                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 410                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 411                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 412                 >;
 413         };
 414
 415         pinctrl_usdhc3: usdhc3grp {
 416                 fsl,pins = <
 417                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 418                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 419                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 420                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 421                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 422                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 423                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 424                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 425                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 426                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 427                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 428                 >;
 429         };
 430
 431         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 432                 fsl,pins = <
 433                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
 434                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 435                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 436                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 437                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 438                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 439                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 440                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 441                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 442                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 443                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 444                 >;
 445         };
 446
 447         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 448                 fsl,pins = <
 449                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
 450                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 451                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 452                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 453                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 454                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 455                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 456                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 457                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 458                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 459                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 460                 >;
 461         };
 462
 463         pinctrl_wdog: wdoggrp {
 464                 fsl,pins = <
 465                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 466                 >;
 467         };
 468
 469         pinctrl_wlan: wlangrp {
 470                 fsl,pins = <
 471                         MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
 472                 >;
 473         };
 474 };