arch/arm/boot/dts/rk3036.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3036-cru.h>
   8 #include <dt-bindings/soc/rockchip,boot-mode.h>
   9 #include <dt-bindings/power/rk3036-power.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         compatible = "rockchip,rk3036";
  16
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 mshc0 = &emmc;
  24                 mshc1 = &sdmmc;
  25                 mshc2 = &sdio;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 serial2 = &uart2;
  29                 spi = &spi;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 enable-method = "rockchip,rk3036-smp";
  36
  37                 cpu0: cpu@f00 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf00>;
  41                         resets = <&cru SRST_CORE0>;
  42                         operating-points = <
  43                                 /* KHz    uV */
  44                                  816000 1000000
  45                         >;
  46                         clock-latency = <40000>;
  47                         clocks = <&cru ARMCLK>;
  48                 };
  49
  50                 cpu1: cpu@f01 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0xf01>;
  54                         resets = <&cru SRST_CORE1>;
  55                 };
  56         };
  57
  58         arm-pmu {
  59                 compatible = "arm,cortex-a7-pmu";
  60                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  62                 interrupt-affinity = <&cpu0>, <&cpu1>;
  63         };
  64
  65         display-subsystem {
  66                 compatible = "rockchip,display-subsystem";
  67                 ports = <&vop_out>;
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 arm,cpu-registers-not-fw-configured;
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  77                 clock-frequency = <24000000>;
  78         };
  79
  80         xin24m: oscillator {
  81                 compatible = "fixed-clock";
  82                 clock-frequency = <24000000>;
  83                 clock-output-names = "xin24m";
  84                 #clock-cells = <0>;
  85         };
  86
  87         bus_intmem: sram@10080000 {
  88                 compatible = "mmio-sram";
  89                 reg = <0x10080000 0x2000>;
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges = <0 0x10080000 0x2000>;
  93
  94                 smp-sram@0 {
  95                         compatible = "rockchip,rk3066-smp-sram";
  96                         reg = <0x00 0x10>;
  97                 };
  98         };
  99
 100         gpu: gpu@10090000 {
 101                 compatible = "rockchip,rk3036-mali", "arm,mali-400";
 102                 reg = <0x10090000 0x10000>;
 103                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 107                 interrupt-names = "gp",
 108                                   "gpmmu",
 109                                   "pp0",
 110                                   "ppmmu0";
 111                 assigned-clocks = <&cru SCLK_GPU>;
 112                 assigned-clock-rates = <100000000>;
 113                 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 114                 clock-names = "bus", "core";
 115                 power-domains = <&power RK3036_PD_GPU>;
 116                 resets = <&cru SRST_GPU>;
 117                 status = "disabled";
 118         };
 119
 120         vop: vop@10118000 {
 121                 compatible = "rockchip,rk3036-vop";
 122                 reg = <0x10118000 0x19c>;
 123                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 124                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 125                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 126                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 127                 reset-names = "axi", "ahb", "dclk";
 128                 iommus = <&vop_mmu>;
 129                 power-domains = <&power RK3036_PD_VIO>;
 130                 status = "disabled";
 131
 132                 vop_out: port {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         vop_out_hdmi: endpoint@0 {
 136                                 reg = <0>;
 137                                 remote-endpoint = <&hdmi_in_vop>;
 138                         };
 139                 };
 140         };
 141
 142         vop_mmu: iommu@10118300 {
 143                 compatible = "rockchip,iommu";
 144                 reg = <0x10118300 0x100>;
 145                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 147                 clock-names = "aclk", "iface";
 148                 power-domains = <&power RK3036_PD_VIO>;
 149                 #iommu-cells = <0>;
 150                 status = "disabled";
 151         };
 152
 153         qos_gpu: qos@1012d000 {
 154                 compatible = "rockchip,rk3036-qos", "syscon";
 155                 reg = <0x1012d000 0x20>;
 156         };
 157
 158         qos_vpu: qos@1012e000 {
 159                 compatible = "rockchip,rk3036-qos", "syscon";
 160                 reg = <0x1012e000 0x20>;
 161         };
 162
 163         qos_vio: qos@1012f000 {
 164                 compatible = "rockchip,rk3036-qos", "syscon";
 165                 reg = <0x1012f000 0x20>;
 166         };
 167
 168         gic: interrupt-controller@10139000 {
 169                 compatible = "arm,gic-400";
 170                 interrupt-controller;
 171                 #interrupt-cells = <3>;
 172                 #address-cells = <0>;
 173
 174                 reg = <0x10139000 0x1000>,
 175                       <0x1013a000 0x2000>,
 176                       <0x1013c000 0x2000>,
 177                       <0x1013e000 0x2000>;
 178                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 179         };
 180
 181         usb_otg: usb@10180000 {
 182                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 183                                 "snps,dwc2";
 184                 reg = <0x10180000 0x40000>;
 185                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&cru HCLK_OTG0>;
 187                 clock-names = "otg";
 188                 dr_mode = "otg";
 189                 g-np-tx-fifo-size = <16>;
 190                 g-rx-fifo-size = <275>;
 191                 g-tx-fifo-size = <256 128 128 64 64 32>;
 192                 status = "disabled";
 193         };
 194
 195         usb_host: usb@101c0000 {
 196                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 197                                 "snps,dwc2";
 198                 reg = <0x101c0000 0x40000>;
 199                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru HCLK_OTG1>;
 201                 clock-names = "otg";
 202                 dr_mode = "host";
 203                 status = "disabled";
 204         };
 205
 206         emac: ethernet@10200000 {
 207                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 208                 reg = <0x10200000 0x4000>;
 209                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 rockchip,grf = <&grf>;
 213                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 214                 clock-names = "hclk", "macref", "macclk";
 215                 /*
 216                  * Fix the emac parent clock is DPLL instead of APLL.
 217                  * since that will cause some unstable things if the cpufreq
 218                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 219                  */
 220                 assigned-clocks = <&cru SCLK_MACPLL>;
 221                 assigned-clock-parents = <&cru PLL_DPLL>;
 222                 max-speed = <100>;
 223                 phy-mode = "rmii";
 224                 status = "disabled";
 225         };
 226
 227         sdmmc: mmc@10214000 {
 228                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 229                 reg = <0x10214000 0x4000>;
 230                 clock-frequency = <37500000>;
 231                 max-frequency = <37500000>;
 232                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 233                 clock-names = "biu", "ciu";
 234                 fifo-depth = <0x100>;
 235                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 236                 resets = <&cru SRST_MMC0>;
 237                 reset-names = "reset";
 238                 status = "disabled";
 239         };
 240
 241         sdio: mmc@10218000 {
 242                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 243                 reg = <0x10218000 0x4000>;
 244                 max-frequency = <37500000>;
 245                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 246                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 250                 resets = <&cru SRST_SDIO>;
 251                 reset-names = "reset";
 252                 status = "disabled";
 253         };
 254
 255         emmc: mmc@1021c000 {
 256                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 257                 reg = <0x1021c000 0x4000>;
 258                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 259                 bus-width = <8>;
 260                 cap-mmc-highspeed;
 261                 clock-frequency = <37500000>;
 262                 max-frequency = <37500000>;
 263                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 264                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 265                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 266                 rockchip,default-sample-phase = <158>;
 267                 disable-wp;
 268                 dmas = <&pdma 12>;
 269                 dma-names = "rx-tx";
 270                 fifo-depth = <0x100>;
 271                 mmc-ddr-1_8v;
 272                 non-removable;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 275                 resets = <&cru SRST_EMMC>;
 276                 reset-names = "reset";
 277                 status = "disabled";
 278         };
 279
 280         i2s: i2s@10220000 {
 281                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 282                 reg = <0x10220000 0x4000>;
 283                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 284                 clock-names = "i2s_clk", "i2s_hclk";
 285                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 286                 dmas = <&pdma 0>, <&pdma 1>;
 287                 dma-names = "tx", "rx";
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&i2s_bus>;
 290                 #sound-dai-cells = <0>;
 291                 status = "disabled";
 292         };
 293
 294         nfc: nand-controller@10500000 {
 295                 compatible = "rockchip,rk3036-nfc",
 296                              "rockchip,rk2928-nfc";
 297                 reg = <0x10500000 0x4000>;
 298                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 300                 clock-names = "ahb", "nfc";
 301                 assigned-clocks = <&cru SCLK_NANDC>;
 302                 assigned-clock-rates = <150000000>;
 303                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 304                              &flash_rdn &flash_rdy &flash_wrn>;
 305                 pinctrl-names = "default";
 306                 status = "disabled";
 307         };
 308
 309         cru: clock-controller@20000000 {
 310                 compatible = "rockchip,rk3036-cru";
 311                 reg = <0x20000000 0x1000>;
 312                 rockchip,grf = <&grf>;
 313                 #clock-cells = <1>;
 314                 #reset-cells = <1>;
 315                 assigned-clocks = <&cru PLL_GPLL>;
 316                 assigned-clock-rates = <594000000>;
 317         };
 318
 319         grf: syscon@20008000 {
 320                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 321                 reg = <0x20008000 0x1000>;
 322
 323                 power: power-controller {
 324                         compatible = "rockchip,rk3036-power-controller";
 325                         #power-domain-cells = <1>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328
 329                         power-domain@RK3036_PD_VIO {
 330                                 reg = <RK3036_PD_VIO>;
 331                                 clocks = <&cru ACLK_LCDC>,
 332                                          <&cru HCLK_LCDC>,
 333                                          <&cru SCLK_LCDC>;
 334                                 pm_qos = <&qos_vio>;
 335                                 #power-domain-cells = <0>;
 336                         };
 337
 338                         power-domain@RK3036_PD_VPU {
 339                                 reg = <RK3036_PD_VPU>;
 340                                 clocks = <&cru ACLK_VCODEC>,
 341                                          <&cru HCLK_VCODEC>;
 342                                 pm_qos = <&qos_vpu>;
 343                                 #power-domain-cells = <0>;
 344                         };
 345
 346                         power-domain@RK3036_PD_GPU {
 347                                 reg = <RK3036_PD_GPU>;
 348                                 clocks = <&cru SCLK_GPU>;
 349                                 pm_qos = <&qos_gpu>;
 350                                 #power-domain-cells = <0>;
 351                         };
 352                 };
 353
 354                 reboot-mode {
 355                         compatible = "syscon-reboot-mode";
 356                         offset = <0x1d8>;
 357                         mode-normal = <BOOT_NORMAL>;
 358                         mode-recovery = <BOOT_RECOVERY>;
 359                         mode-bootloader = <BOOT_FASTBOOT>;
 360                         mode-loader = <BOOT_BL_DOWNLOAD>;
 361                 };
 362         };
 363
 364         acodec: acodec-ana@20030000 {
 365                 compatible = "rk3036-codec";
 366                 reg = <0x20030000 0x4000>;
 367                 rockchip,grf = <&grf>;
 368                 clock-names = "acodec_pclk";
 369                 clocks = <&cru PCLK_ACODEC>;
 370                 status = "disabled";
 371         };
 372
 373         hdmi: hdmi@20034000 {
 374                 compatible = "rockchip,rk3036-inno-hdmi";
 375                 reg = <0x20034000 0x4000>;
 376                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&cru  PCLK_HDMI>;
 378                 clock-names = "pclk";
 379                 rockchip,grf = <&grf>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&hdmi_ctl>;
 382                 status = "disabled";
 383
 384                 hdmi_in: port {
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         hdmi_in_vop: endpoint@0 {
 388                                 reg = <0>;
 389                                 remote-endpoint = <&vop_out_hdmi>;
 390                         };
 391                 };
 392         };
 393
 394         timer: timer@20044000 {
 395                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 396                 reg = <0x20044000 0x20>;
 397                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 399                 clock-names = "timer", "pclk";
 400         };
 401
 402         pwm0: pwm@20050000 {
 403                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 404                 reg = <0x20050000 0x10>;
 405                 #pwm-cells = <3>;
 406                 clocks = <&cru PCLK_PWM>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&pwm0_pin>;
 409                 status = "disabled";
 410         };
 411
 412         pwm1: pwm@20050010 {
 413                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 414                 reg = <0x20050010 0x10>;
 415                 #pwm-cells = <3>;
 416                 clocks = <&cru PCLK_PWM>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&pwm1_pin>;
 419                 status = "disabled";
 420         };
 421
 422         pwm2: pwm@20050020 {
 423                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 424                 reg = <0x20050020 0x10>;
 425                 #pwm-cells = <3>;
 426                 clocks = <&cru PCLK_PWM>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&pwm2_pin>;
 429                 status = "disabled";
 430         };
 431
 432         pwm3: pwm@20050030 {
 433                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 434                 reg = <0x20050030 0x10>;
 435                 #pwm-cells = <2>;
 436                 clocks = <&cru PCLK_PWM>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&pwm3_pin>;
 439                 status = "disabled";
 440         };
 441
 442         i2c1: i2c@20056000 {
 443                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 444                 reg = <0x20056000 0x1000>;
 445                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clock-names = "i2c";
 449                 clocks = <&cru PCLK_I2C1>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&i2c1_xfer>;
 452                 status = "disabled";
 453         };
 454
 455         i2c2: i2c@2005a000 {
 456                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 457                 reg = <0x2005a000 0x1000>;
 458                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clock-names = "i2c";
 462                 clocks = <&cru PCLK_I2C2>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&i2c2_xfer>;
 465                 status = "disabled";
 466         };
 467
 468         uart0: serial@20060000 {
 469                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 470                 reg = <0x20060000 0x100>;
 471                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 472                 reg-shift = <2>;
 473                 reg-io-width = <4>;
 474                 clock-frequency = <24000000>;
 475                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 476                 clock-names = "baudclk", "apb_pclk";
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 479                 status = "disabled";
 480         };
 481
 482         uart1: serial@20064000 {
 483                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 484                 reg = <0x20064000 0x100>;
 485                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 486                 reg-shift = <2>;
 487                 reg-io-width = <4>;
 488                 clock-frequency = <24000000>;
 489                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 490                 clock-names = "baudclk", "apb_pclk";
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&uart1_xfer>;
 493                 status = "disabled";
 494         };
 495
 496         uart2: serial@20068000 {
 497                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 498                 reg = <0x20068000 0x100>;
 499                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 500                 reg-shift = <2>;
 501                 reg-io-width = <4>;
 502                 clock-frequency = <24000000>;
 503                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 504                 clock-names = "baudclk", "apb_pclk";
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&uart2_xfer>;
 507                 status = "disabled";
 508         };
 509
 510         i2c0: i2c@20072000 {
 511                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 512                 reg = <0x20072000 0x1000>;
 513                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 clock-names = "i2c";
 517                 clocks = <&cru PCLK_I2C0>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&i2c0_xfer>;
 520                 status = "disabled";
 521         };
 522
 523         spi: spi@20074000 {
 524                 compatible = "rockchip,rockchip-spi";
 525                 reg = <0x20074000 0x1000>;
 526                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
 528                 clock-names = "apb-pclk","spi_pclk";
 529                 dmas = <&pdma 8>, <&pdma 9>;
 530                 dma-names = "tx", "rx";
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         pdma: pdma@20078000 {
 539                 compatible = "arm,pl330", "arm,primecell";
 540                 reg = <0x20078000 0x4000>;
 541                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 542                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 543                 #dma-cells = <1>;
 544                 arm,pl330-broken-no-flushp;
 545                 arm,pl330-periph-burst;
 546                 clocks = <&cru ACLK_DMAC2>;
 547                 clock-names = "apb_pclk";
 548         };
 549
 550         pinctrl: pinctrl {
 551                 compatible = "rockchip,rk3036-pinctrl";
 552                 rockchip,grf = <&grf>;
 553                 #address-cells = <1>;
 554                 #size-cells = <1>;
 555                 ranges;
 556
 557                 gpio0: gpio0@2007c000 {
 558                         compatible = "rockchip,gpio-bank";
 559                         reg = <0x2007c000 0x100>;
 560                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&cru PCLK_GPIO0>;
 562
 563                         gpio-controller;
 564                         #gpio-cells = <2>;
 565
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                 };
 569
 570                 gpio1: gpio1@20080000 {
 571                         compatible = "rockchip,gpio-bank";
 572                         reg = <0x20080000 0x100>;
 573                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&cru PCLK_GPIO1>;
 575
 576                         gpio-controller;
 577                         #gpio-cells = <2>;
 578
 579                         interrupt-controller;
 580                         #interrupt-cells = <2>;
 581                 };
 582
 583                 gpio2: gpio2@20084000 {
 584                         compatible = "rockchip,gpio-bank";
 585                         reg = <0x20084000 0x100>;
 586                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&cru PCLK_GPIO2>;
 588
 589                         gpio-controller;
 590                         #gpio-cells = <2>;
 591
 592                         interrupt-controller;
 593                         #interrupt-cells = <2>;
 594                 };
 595
 596                 pcfg_pull_default: pcfg_pull_default {
 597                         bias-pull-pin-default;
 598                 };
 599
 600                 pcfg_pull_none: pcfg-pull-none {
 601                         bias-disable;
 602                 };
 603
 604                 pwm0 {
 605                         pwm0_pin: pwm0-pin {
 606                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 607                         };
 608                 };
 609
 610                 pwm1 {
 611                         pwm1_pin: pwm1-pin {
 612                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 613                         };
 614                 };
 615
 616                 pwm2 {
 617                         pwm2_pin: pwm2-pin {
 618                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 pwm3 {
 623                         pwm3_pin: pwm3-pin {
 624                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 625                         };
 626                 };
 627
 628                 sdmmc {
 629                         sdmmc_clk: sdmmc-clk {
 630                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 631                         };
 632
 633                         sdmmc_cmd: sdmmc-cmd {
 634                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
 635                         };
 636
 637                         sdmmc_cd: sdmmc-cd {
 638                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
 639                         };
 640
 641                         sdmmc_bus1: sdmmc-bus1 {
 642                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
 643                         };
 644
 645                         sdmmc_bus4: sdmmc-bus4 {
 646                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
 647                                                 <1 RK_PC3 1 &pcfg_pull_default>,
 648                                                 <1 RK_PC4 1 &pcfg_pull_default>,
 649                                                 <1 RK_PC5 1 &pcfg_pull_default>;
 650                         };
 651                 };
 652
 653                 sdio {
 654                         sdio_bus1: sdio-bus1 {
 655                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
 656                         };
 657
 658                         sdio_bus4: sdio-bus4 {
 659                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
 660                                                 <0 RK_PB4 1 &pcfg_pull_default>,
 661                                                 <0 RK_PB5 1 &pcfg_pull_default>,
 662                                                 <0 RK_PB6 1 &pcfg_pull_default>;
 663                         };
 664
 665                         sdio_cmd: sdio-cmd {
 666                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
 667                         };
 668
 669                         sdio_clk: sdio-clk {
 670                                 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
 671                         };
 672                 };
 673
 674                 emmc {
 675                         /*
 676                          * We run eMMC at max speed; bump up drive strength.
 677                          * We also have external pulls, so disable the internal ones.
 678                          */
 679                         emmc_clk: emmc-clk {
 680                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 681                         };
 682
 683                         emmc_cmd: emmc-cmd {
 684                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
 685                         };
 686
 687                         emmc_bus8: emmc-bus8 {
 688                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 689                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 690                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 691                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 692                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 693                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 694                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 695                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 696                         };
 697                 };
 698
 699                 nfc {
 700                         flash_ale: flash-ale {
 701                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
 702                         };
 703
 704                         flash_bus8: flash-bus8 {
 705                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
 706                                                 <1 RK_PD1 1 &pcfg_pull_default>,
 707                                                 <1 RK_PD2 1 &pcfg_pull_default>,
 708                                                 <1 RK_PD3 1 &pcfg_pull_default>,
 709                                                 <1 RK_PD4 1 &pcfg_pull_default>,
 710                                                 <1 RK_PD5 1 &pcfg_pull_default>,
 711                                                 <1 RK_PD6 1 &pcfg_pull_default>,
 712                                                 <1 RK_PD7 1 &pcfg_pull_default>;
 713                         };
 714
 715                         flash_cle: flash-cle {
 716                                 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
 717                         };
 718
 719                         flash_csn0: flash-csn0 {
 720                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
 721                         };
 722
 723                         flash_rdn: flash-rdn {
 724                                 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
 725                         };
 726
 727                         flash_rdy: flash-rdy {
 728                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
 729                         };
 730
 731                         flash_wrn: flash-wrn {
 732                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
 733                         };
 734                 };
 735
 736                 emac {
 737                         emac_xfer: emac-xfer {
 738                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
 739                                                 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
 740                                                 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
 741                                                 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
 742                                                 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
 743                                                 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
 744                                                 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
 745                                                 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
 746                         };
 747
 748                         emac_mdio: emac-mdio {
 749                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
 750                                                 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
 751                         };
 752                 };
 753
 754                 i2c0 {
 755                         i2c0_xfer: i2c0-xfer {
 756                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 757                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 758                         };
 759                 };
 760
 761                 i2c1 {
 762                         i2c1_xfer: i2c1-xfer {
 763                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 764                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 765                         };
 766                 };
 767
 768                 i2c2 {
 769                         i2c2_xfer: i2c2-xfer {
 770                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
 771                                                 <2 RK_PC5 1 &pcfg_pull_none>;
 772                         };
 773                 };
 774
 775                 i2s {
 776                         i2s_bus: i2s-bus {
 777                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
 778                                                 <1 RK_PA1 1 &pcfg_pull_default>,
 779                                                 <1 RK_PA2 1 &pcfg_pull_default>,
 780                                                 <1 RK_PA3 1 &pcfg_pull_default>,
 781                                                 <1 RK_PA4 1 &pcfg_pull_default>,
 782                                                 <1 RK_PA5 1 &pcfg_pull_default>;
 783                         };
 784                 };
 785
 786                 hdmi {
 787                         hdmi_ctl: hdmi-ctl {
 788                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
 789                                                 <1 RK_PB1 1 &pcfg_pull_none>,
 790                                                 <1 RK_PB2 1 &pcfg_pull_none>,
 791                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 792                         };
 793                 };
 794
 795                 uart0 {
 796                         uart0_xfer: uart0-xfer {
 797                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
 798                                                 <0 RK_PC1 1 &pcfg_pull_none>;
 799                         };
 800
 801                         uart0_cts: uart0-cts {
 802                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
 803                         };
 804
 805                         uart0_rts: uart0-rts {
 806                                 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
 807                         };
 808                 };
 809
 810                 uart1 {
 811                         uart1_xfer: uart1-xfer {
 812                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
 813                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 814                         };
 815                         /* no rts / cts for uart1 */
 816                 };
 817
 818                 uart2 {
 819                         uart2_xfer: uart2-xfer {
 820                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
 821                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 822                         };
 823                         /* no rts / cts for uart2 */
 824                 };
 825
 826                 spi-pins {
 827                         spi_txd:spi-txd {
 828                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
 829                         };
 830
 831                         spi_rxd:spi-rxd {
 832                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
 833                         };
 834
 835                         spi_clk:spi-clk {
 836                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
 837                         };
 838
 839                         spi_cs0:spi-cs0 {
 840                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 841
 842                         };
 843
 844                         spi_cs1:spi-cs1 {
 845                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 846
 847                         };
 848                 };
 849         };
 850 };