ARM: dts: rockchip: add power controller for RK3036

Add the power controller node and the correspondending qos nodes for
RK3036.
Also add the power-domain property to the nodes that are already
present.
Note: Since the regiser offsets of the axi interconnect QoS are missing
in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210527154455.358869-9-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 9ccefa8..33019d2 100644 (file)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3036-cru.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/power/rk3036-power.h>
 
 / {
        #address-cells = <1>;
@@ -111,6 +112,7 @@
                assigned-clock-rates = <100000000>;
                clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
                clock-names = "bus", "core";
+               power-domains = <&power RK3036_PD_GPU>;
                resets = <&cru SRST_GPU>;
                status = "disabled";
        };
@@ -124,6 +126,7 @@
                resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
                reset-names = "axi", "ahb", "dclk";
                iommus = <&vop_mmu>;
+               power-domains = <&power RK3036_PD_VIO>;
                status = "disabled";
 
                vop_out: port {
@@ -142,10 +145,26 @@
                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3036_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
        };
 
+       qos_gpu: qos@1012d000 {
+               compatible = "rockchip,rk3036-qos", "syscon";
+               reg = <0x1012d000 0x20>;
+       };
+
+       qos_vpu: qos@1012e000 {
+               compatible = "rockchip,rk3036-qos", "syscon";
+               reg = <0x1012e000 0x20>;
+       };
+
+       qos_vio: qos@1012f000 {
+               compatible = "rockchip,rk3036-qos", "syscon";
+               reg = <0x1012f000 0x20>;
+       };
+
        gic: interrupt-controller@10139000 {
                compatible = "arm,gic-400";
                interrupt-controller;
@@ -301,6 +320,37 @@
                compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
                reg = <0x20008000 0x1000>;
 
+               power: power-controller {
+                       compatible = "rockchip,rk3036-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       power-domain@RK3036_PD_VIO {
+                               reg = <RK3036_PD_VIO>;
+                               clocks = <&cru ACLK_LCDC>,
+                                        <&cru HCLK_LCDC>,
+                                        <&cru SCLK_LCDC>;
+                               pm_qos = <&qos_vio>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3036_PD_VPU {
+                               reg = <RK3036_PD_VPU>;
+                               clocks = <&cru ACLK_VCODEC>,
+                                        <&cru HCLK_VCODEC>;
+                               pm_qos = <&qos_vpu>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3036_PD_GPU {
+                               reg = <RK3036_PD_GPU>;
+                               clocks = <&cru SCLK_GPU>;
+                               pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+
                reboot-mode {
                        compatible = "syscon-reboot-mode";
                        offset = <0x1d8>;