1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
13 - $ref: can-controller.yaml#
20 - renesas,r8a774a1-canfd # RZ/G2M
21 - renesas,r8a774b1-canfd # RZ/G2N
22 - renesas,r8a774c0-canfd # RZ/G2E
23 - renesas,r8a774e1-canfd # RZ/G2H
24 - renesas,r8a7795-canfd # R-Car H3
25 - renesas,r8a7796-canfd # R-Car M3-W
26 - renesas,r8a77965-canfd # R-Car M3-N
27 - renesas,r8a77970-canfd # R-Car V3M
28 - renesas,r8a77980-canfd # R-Car V3H
29 - renesas,r8a77990-canfd # R-Car E3
30 - renesas,r8a77995-canfd # R-Car D3
31 - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2
38 - description: Channel interrupt
39 - description: Global interrupt
57 $ref: /schemas/types.yaml#/definitions/flag
59 The controller can operate in either CAN FD only mode (default) or
60 Classical CAN only mode. The mode is global to both the channels.
61 Specify this property to put the controller in Classical CAN only mode.
65 Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
66 used by both CAN (if present) and CAN FD controllers at the same time.
67 It needs to be scaled to maximum frequency if any of these controllers
71 description: Maximum frequency of the CANFD clock.
77 The controller supports two channels and each is represented as a child
78 node. Each child node supports the "status" property only, which
79 is used to enable/disable the respective channel.
90 - assigned-clock-rates
94 unevaluatedProperties: false
98 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
99 #include <dt-bindings/interrupt-controller/arm-gic.h>
100 #include <dt-bindings/power/r8a7795-sysc.h>
102 canfd: can@e66c0000 {
103 compatible = "renesas,r8a7795-canfd",
104 "renesas,rcar-gen3-canfd";
105 reg = <0xe66c0000 0x8000>;
106 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&cpg CPG_MOD 914>,
109 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
111 clock-names = "fck", "canfd", "can_clk";
112 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
113 assigned-clock-rates = <40000000>;
114 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;