1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: mediatek DPI Controller Device Tree Bindings
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek DPI function block is a sink of the display subsystem and
15 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
34 - description: Pixel Clock
35 - description: Engine Clock
36 - description: DPI PLL
53 $ref: /schemas/graph.yaml#/properties/port
55 Output port node. This port should be connected to the input port of an
56 attached HDMI or LVDS encoder chip.
66 additionalProperties: false
70 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 #include <dt-bindings/clock/mt8173-clk.h>
72 #include <dt-bindings/interrupt-controller/arm-gic.h>
73 #include <dt-bindings/interrupt-controller/irq.h>
75 compatible = "mediatek,mt8173-dpi";
76 reg = <0x1401d000 0x1000>;
77 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
78 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
79 <&mmsys CLK_MM_DPI_ENGINE>,
80 <&apmixedsys CLK_APMIXED_TVDPLL>;
81 clock-names = "pixel", "engine", "pll";
82 pinctrl-names = "default", "sleep";
83 pinctrl-0 = <&dpi_pin_func>;
84 pinctrl-1 = <&dpi_pin_idle>;
88 remote-endpoint = <&hdmi0_in>;