1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DPI and DP_INTF Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The MediaTek DPI and DP_INTF function blocks are a sink of the display
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
27 - mediatek,mt8188-dp-intf
29 - mediatek,mt8195-dp-intf
33 - const: mediatek,mt8183-dpi
43 - description: Pixel Clock
44 - description: Engine Clock
45 - description: DPI PLL
62 $ref: /schemas/graph.yaml#/properties/port
64 Output port node. This port should be connected to the input port of an
65 attached HDMI, LVDS or DisplayPort encoder chip.
75 additionalProperties: false
79 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 #include <dt-bindings/clock/mt8173-clk.h>
83 compatible = "mediatek,mt8173-dpi";
84 reg = <0x1401d000 0x1000>;
85 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
86 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
87 <&mmsys CLK_MM_DPI_ENGINE>,
88 <&apmixedsys CLK_APMIXED_TVDPLL>;
89 clock-names = "pixel", "engine", "pll";
90 pinctrl-names = "default", "sleep";
91 pinctrl-0 = <&dpi_pin_func>;
92 pinctrl-1 = <&dpi_pin_idle>;
96 remote-endpoint = <&hdmi0_in>;