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drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
2022-01-11 Matt Roperdrm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220111051600.3429104-6-matthew.d.roper@intel.com
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2022-01-11 Matt Roperdrm/i915: Use RING_PSMI_CTL rather than per-engine...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220111051600.3429104-5-matthew.d.roper@intel.com
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2022-01-11 Matt Roperdrm/i915: Parameterize ECOSKPD
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220111051600.3429104-4-matthew.d.roper@intel.com
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2022-01-11 Matt Roperdrm/i915: Parameterize PWRCTX_MAXCNT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220111051600.3429104-3-matthew.d.roper@intel.com
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2022-01-11 Matt Roperdrm/i915: Use parameterized GPR register definitions...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220111051600.3429104-2-matthew.d.roper@intel.com
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2021-12-03 Matt Roperdrm/i915/dg2: Add Wa_14010547955
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20211116174818.2128062-3-matthew.d.roper@intel.com
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2021-12-03 Matt Roperdrm/i915/dg2: s/DISP_STEPPING/DISPLAY_STEPPING/
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20211116174818.2128062-2-matthew.d.roper@intel.com
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2021-10-15 Matt Roperdrm/i915/uapi: Add comment clarifying purpose of I915_TILING...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20211012221245.2609670-1-matthew.d.roper@intel.com
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2021-10-12 Matt Roperdrm/i915: Stop using I915_TILING_* in client blit selftest
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20211001005816.73330-1-matthew.d.roper@intel.com
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2021-09-23 Matt Roperdrm/i915/uncore: fwtable read handlers are now used...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210923003029.2194375-1-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/dg2: Add DG2-specific shadow register table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-7-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/uncore: Drop gen11 mmio read handlers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-6-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/uncore: Drop gen11/gen12 mmio write handlers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-5-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/uncore: Replace gen8 write functions with...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-4-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/uncore: Associate shadow table with uncore
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-3-matthew.d.roper@intel.com
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2021-09-22 Matt Roperdrm/i915/uncore: Convert gen6/gen7 read operations...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210910201030.3436066-2-matthew.d.roper@intel.com
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2021-09-21 Matt Roperdrm/i915: Check SFC fusing before recording/dumping...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210917161203.812251-3-matthew.d.roper@intel.com
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2021-09-21 Matt Roperdrm/i915/xehp: Check new fuse bits for SFC availability
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210917161203.812251-2-matthew.d.roper@intel.com
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2021-09-14 Matt Roperdrm/i915/dg2: Define MOCS table for DG2
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210904003544.2422282-3-matthew.d.roper@intel.com
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2021-08-27 Matt Roperdrm/i915: Ensure wa_init_finish() is called for ctx...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210826033559.1209020-1-matthew.d.roper@intel.com
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2021-08-25 Matt Roperdrm/i915/dg2: Memory latency values from pcode must...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210820225710.401136-1-matthew.d.roper@intel.com
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2021-08-24 Matt Roperdrm/i915/adl_p: Also disable underrun recovery with MSO
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210816204112.2960624-1-matthew.d.roper@intel.com
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2021-08-18 Matt Roperdrm/i915/dg2: Maintain backward-compatible nested batch...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210805163647.801064-9-matthew.d.roper@intel.com
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2021-08-18 Matt Roperdrm/i915/adl_p: Also disable underrun recovery with MSO
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210816204112.2960624-1-matthew.d.roper@intel.com
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2021-08-12 Matt Roperdrm/i915/xehpsdv: Read correct RP_STATE_CAP register
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210805163647.801064-7-matthew.d.roper@intel.com
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2021-08-12 Matt Roperdrm/i915: Only access SFC_DONE when media domain is...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210806174130.1058960-1-matthew.d.roper@intel.com
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2021-08-11 Matt Roperdrm/i915: Only access SFC_DONE when media domain is...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210806174130.1058960-1-matthew.d.roper@intel.com
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2021-08-11 Matt Roperdrm/i915/dg2: Report INSTDONE_GEOM values in error...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210805163647.801064-4-matthew.d.roper@intel.com
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2021-08-11 Matt Roperdrm/i915/xehp: Loop over all gslices for INSTDONE processing
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210805163647.801064-3-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915/xehp: Xe_HP shadowed registers are a strict...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729054118.2458523-7-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915/gen12: Update shadowed register table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729054118.2458523-6-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915/gen11: Update shadowed register table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729054118.2458523-5-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915: Make shadow tables range-based
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729152158.2646246-1-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915: Re-use gen11 forcewake read functions on...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729054118.2458523-3-matthew.d.roper@intel.com
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2021-08-10 Matt Roperdrm/i915: correct name of GT forcewake domain in error...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729054118.2458523-2-matthew.d.roper@intel.com
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2021-08-06 Matt Roperdrm/i915/dg2: Add support for new DG2-G11 revid 0x5
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210805163647.801064-2-matthew.d.roper@intel.com
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2021-08-05 Matt Roperdrm/i915/dg2: Add SQIDI steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-6-matthew.d.roper@intel.com
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2021-08-05 Matt Roperdrm/i915/dg2: Update steering tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-5-matthew.d.roper@intel.com
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2021-08-05 Matt Roperdrm/i915/xehpsdv: Define steering tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-3-matthew.d.roper@intel.com
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2021-08-04 Matt Roperdrm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-12-matthew.d.roper@intel.com
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2021-08-04 Matt Roperdrm/i915/xehpsdv: Add maximum sseu limits
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-10-matthew.d.roper@intel.com
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2021-08-04 Matt Roperdrm/i915/dg2: Add forcewake table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210729170008.2836648-4-matthew.d.roper@intel.com
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2021-08-03 Matt Roperdrm/i915: Correct SFC_DONE register offset
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210728233411.2365788-1-matthew.d.roper@intel.com
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2021-08-02 Matt Roperdrm/i915: Correct SFC_DONE register offset
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210728233411.2365788-1-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/dg2: Wait for SNPS PHY calibration during...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-28-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/dg2: Update modeset sequences
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-27-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/dg2: Add vswing programming for SNPS phys
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-26-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/dg2: Add MPLLB programming for HDMI
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-25-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/dg2: Add MPLLB programming for SNPS PHY
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-24-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/adl_p: Add ddi buf translation tables for...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210728221045.2363614-2-matthew.d.roper@intel.com
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2021-07-29 Matt Roperdrm/i915/adl_s: Update ddi buf translation tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210728221045.2363614-1-matthew.d.roper@intel.com
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2021-07-28 Matt Roperdrm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-2-matthew.d.roper@intel.com
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2021-07-28 Matt Roperdrm/i915/adl_p: Allow underrun recovery when possible
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210727145056.2049720-1-matthew.d.roper@intel.com
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2021-07-24 Matt Roperdrm/i915/xehp: Xe_HP forcewake support
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723174239.1551352-6-matthew.d.roper@intel.com
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2021-07-24 Matt Roperdrm/i915: Program chicken bit during DP MST sequence...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210723170618.1477415-1-matthew.d.roper@intel.com
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2021-07-23 Matt Roperdrm/i915/dg2: Classify DG2 PHY types
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210714031540.3539704-46-matthew.d.roper@intel.com
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2021-07-23 Matt Roperdrm/i915/xehp: Define multicast register ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210714031540.3539704-11-matthew.d.roper@intel.com
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2021-07-22 Matt RoperMerge branch 'topic/xehp-dg2-definitions-2021-07-21...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-22 Matt Roperdrm/i915/dg2: DG2 has fixed memory bandwidth
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-19-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Don't read DRAM info
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-18-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Don't program BW_BUDDY registers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-17-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Add dbuf programming
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-16-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Setup display outputs
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-15-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Don't wait for AUX power well enable...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-14-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Skip shared DPLL handling
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-13-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Add cdclk table and reference clock
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-12-matthew.d.roper@intel.com
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2021-07-22 Matt Roperdrm/i915/dg2: Add fake PCH
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-11-matthew.d.roper@intel.com
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2021-07-22 Matt RoperMerge branch 'topic/xehp-dg2-definitions-2021-07-21...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-22 Matt Roperdrm/i915/dg2: add DG2 platform info
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210721223043.834562-4-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915: Make display workaround upper bounds exclusive
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-8-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915: Make GT workaround upper bounds exclusive
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-8-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915/rkl: Wa_1408330847 no longer applies to RKL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-7-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915/rkl: Wa_1409767108 also applies to RKL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-6-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915/adl_s: Wa_14011765242 is also needed on A1...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-5-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915: Program DFR enable/disable as a GT workaround
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-4-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915/icl: Drop a couple unnecessary workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-3-matthew.d.roper@intel.com
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2021-07-21 Matt Roperdrm/i915: Fix application of WaInPlaceDecompressionHang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210717051426.4120328-2-matthew.d.roper@intel.com
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2021-07-15 Matt RoperMerge branch 'topic/revid_steppings' into drm-intel...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt RoperMerge branch 'topic/revid_steppings' into drm-intel...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/icl: Drop workarounds that only apply to pre...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-13-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/cnl: Drop all workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-12-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/dg1: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-11-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/rkl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-10-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/jsl_ehl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-9-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/icl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-8-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/glk: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-7-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/bxt: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-6-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/kbl: Drop pre-production revision from stepping...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-5-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915/skl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-4-matthew.d.roper@intel.com
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2021-07-15 Matt Roperdrm/i915: Make pre-production detection use direct...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210713193635.3390052-3-matthew.d.roper@intel.com
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2021-07-08 Matt Roperdrm/i915: Handle cdclk crawling flag in standard manner
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210707234206.2002849-1-matthew.d.roper@intel.com
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2021-06-18 Matt Roperdrm/i915: Add support for explicit L3BANK steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210617211425.1943662-4-matthew.d.roper@intel.com
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2021-06-18 Matt Roperdrm/i915: Add GT support for multiple types of multicast...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210617211425.1943662-3-matthew.d.roper@intel.com
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2021-05-26 Matt Roperdrm/i915/xelpd: Enhanced pipe underrun reporting
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210526000656.3060314-2-matthew.d.roper@intel.com
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2021-05-20 Matt Roperdrm/i915/adl_p: Add dedicated SAGV watermarks
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Matt Roperdrm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-8-matthew.d.roper@intel.com
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2021-05-15 Matt Roperdrm/i915/xelpd: Increase maximum watermark lines to 255
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-3-matthew.d.roper@intel.com
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2021-05-15 Matt Roperdrm/i915/xelpd: Handle new location of outputs D and E
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-2-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Add Wa_14011503030
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-6-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Required bandwidth increases when VT...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-5-matthew.d.roper@intel.com
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