clk: fsl-flexspi: new driver

Add support for the FlexSPI clock on Freescale Layerscape SoCs. The
clock is a simple divider based one and is located inside the device
configuration space (DCFG).

This will allow switching the SCK frequencies for the FlexSPI interface
on the LS1028A and the LX2160A.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201108185113.31377-8-michael@walle.cc
[sboyd@kernel.org: Drop modalias, add module table]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9690804..85856cf 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -188,6 +188,14 @@ config COMMON_CLK_CS2000_CP
        help
          If you say yes here you get support for the CS2000 clock multiplier.
 
+config COMMON_CLK_FSL_FLEXSPI
+       tristate "Clock driver for FlexSPI on Layerscape SoCs"
+       depends on ARCH_LAYERSCAPE || COMPILE_TEST
+       default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
+       help
+         On Layerscape SoCs there is a special clock for the FlexSPI
+         interface.
+
 config COMMON_CLK_FSL_SAI
        bool "Clock driver for BCLK of Freescale SAI cores"
        depends on ARCH_LAYERSCAPE || COMPILE_TEST

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf1..dbdc590 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP)    += clk-cs2000-cp.o
 obj-$(CONFIG_ARCH_EFM32)               += clk-efm32gg.o
 obj-$(CONFIG_ARCH_SPARX5)              += clk-sparx5.o
 obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)    += clk-fixed-mmio.o
+obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI)   += clk-fsl-flexspi.o
 obj-$(CONFIG_COMMON_CLK_FSL_SAI)       += clk-fsl-sai.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)                += clk-gemini.o
 obj-$(CONFIG_COMMON_CLK_ASPEED)                += clk-aspeed.o

diff --git a/drivers/clk/clk-fsl-flexspi.c b/drivers/clk/clk-fsl-flexspi.c
new file mode 100644 (file)
index 0000000..8432d68
--- /dev/null
+++ b/drivers/clk/clk-fsl-flexspi.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Layerscape FlexSPI clock driver
+ *
+ * Copyright 2020 Michael Walle <michael@walle.cc>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+static const struct clk_div_table ls1028a_flexspi_divs[] = {
+       { .val = 0, .div = 1, },
+       { .val = 1, .div = 2, },
+       { .val = 2, .div = 3, },
+       { .val = 3, .div = 4, },
+       { .val = 4, .div = 5, },
+       { .val = 5, .div = 6, },
+       { .val = 6, .div = 7, },
+       { .val = 7, .div = 8, },
+       { .val = 11, .div = 12, },
+       { .val = 15, .div = 16, },
+       { .val = 16, .div = 20, },
+       { .val = 17, .div = 24, },
+       { .val = 18, .div = 28, },
+       { .val = 19, .div = 32, },
+       { .val = 20, .div = 80, },
+       {}
+};
+
+static const struct clk_div_table lx2160a_flexspi_divs[] = {
+       { .val = 1, .div = 2, },
+       { .val = 3, .div = 4, },
+       { .val = 5, .div = 6, },
+       { .val = 7, .div = 8, },
+       { .val = 11, .div = 12, },
+       { .val = 15, .div = 16, },
+       { .val = 16, .div = 20, },
+       { .val = 17, .div = 24, },
+       { .val = 18, .div = 28, },
+       { .val = 19, .div = 32, },
+       { .val = 20, .div = 80, },
+       {}
+};
+
+static int fsl_flexspi_clk_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct device_node *np = dev->of_node;
+       const char *clk_name = np->name;
+       const char *clk_parent;
+       struct resource *res;
+       void __iomem *reg;
+       struct clk_hw *hw;
+       const struct clk_div_table *divs;
+
+       divs = device_get_match_data(dev);
+       if (!divs)
+               return -ENOENT;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res)
+               return -ENOENT;
+
+       /*
+        * Can't use devm_ioremap_resource() or devm_of_iomap() because the
+        * resource might already be taken by the parent device.
+        */
+       reg = devm_ioremap(dev, res->start, resource_size(res));
+       if (!reg)
+               return -ENOMEM;
+
+       clk_parent = of_clk_get_parent_name(np, 0);
+       if (!clk_parent)
+               return -EINVAL;
+
+       of_property_read_string(np, "clock-output-names", &clk_name);
+
+       hw = devm_clk_hw_register_divider_table(dev, clk_name, clk_parent, 0,
+                                               reg, 0, 5, 0, divs, NULL);
+       if (IS_ERR(hw))
+               return PTR_ERR(hw);
+
+       return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static const struct of_device_id fsl_flexspi_clk_dt_ids[] = {
+       { .compatible = "fsl,ls1028a-flexspi-clk", .data = &ls1028a_flexspi_divs },
+       { .compatible = "fsl,lx2160a-flexspi-clk", .data = &lx2160a_flexspi_divs },
+       {}
+};
+MODULE_DEVICE_TABLE(of, fsl_flexspi_clk_dt_ids);
+
+static struct platform_driver fsl_flexspi_clk_driver = {
+       .driver = {
+               .name = "fsl-flexspi-clk",
+               .of_match_table = fsl_flexspi_clk_dt_ids,
+       },
+       .probe = fsl_flexspi_clk_probe,
+};
+module_platform_driver(fsl_flexspi_clk_driver);
+
+MODULE_DESCRIPTION("FlexSPI clock driver for Layerscape SoCs");
+MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
+MODULE_LICENSE("GPL");