Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit...

* clk-ingenic:
  clk: ingenic: Remove set but not used variable 'enable'
  clk: ingenic: Fix doc of ingenic_cgu_div_info
  clk: ingenic: Fix round_rate misbehaving with non-integer dividers
  clk: ingenic: jz4740: Fix gating of UDC clock

* clk-mtk-mux:
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2

* clk-qcom-sdm845-pcie:
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

* clk-mtk-crit:
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro

* clk-mtk:
  clk: mediatek: correct cpu clock name for MT8173 SoC

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 5ef7d9b..510b685 100644 (file)
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        const struct ingenic_cgu_clk_info *clk_info;
        const struct ingenic_cgu_pll_info *pll_info;
        unsigned m, n, od_enc, od;
-       bool bypass, enable;
+       bool bypass;
        unsigned long flags;
        u32 ctl;
 
@@ -103,7 +103,6 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        od_enc &= GENMASK(pll_info->od_bits - 1, 0);
        bypass = !pll_info->no_bypass_bit &&
                 !!(ctl & BIT(pll_info->bypass_bit));
-       enable = !!(ctl & BIT(pll_info->enable_bit));
 
        if (bypass)
                return parent_rate;
@@ -426,16 +425,16 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
        struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
        struct ingenic_cgu *cgu = ingenic_clk->cgu;
        const struct ingenic_cgu_clk_info *clk_info;
-       long rate = *parent_rate;
+       unsigned int div = 1;
 
        clk_info = &cgu->clock_info[ingenic_clk->idx];
 
        if (clk_info->type & CGU_CLK_DIV)
-               rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
+               div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
        else if (clk_info->type & CGU_CLK_FIXDIV)
-               rate /= clk_info->fixdiv.div;
+               div = clk_info->fixdiv.div;
 
-       return rate;
+       return DIV_ROUND_UP(*parent_rate, div);
 }
 
 static int
@@ -455,7 +454,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
 
        if (clk_info->type & CGU_CLK_DIV) {
                div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
-               rate = parent_rate / div;
+               rate = DIV_ROUND_UP(parent_rate, div);
 
                if (rate != req_rate)
                        return -EINVAL;

diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 502bcbb..e12716d 100644 (file)
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -80,7 +80,7 @@ struct ingenic_cgu_mux_info {
  * @reg: offset of the divider control register within the CGU
  * @shift: number of bits to left shift the divide value by (ie. the index of
  *         the lowest bit of the divide value within its control register)
- * @div: number of bits to divide the divider value by (i.e. if the
+ * @div: number to divide the divider value by (i.e. if the
  *      effective divider value is the value written to the register
  *      multiplied by some constant)
  * @bits: the size of the divide value in bits

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4479c10..b86edd3 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
                .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
                .mux = { CGU_REG_CPCCR, 29, 1 },
                .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-               .gate = { CGU_REG_SCR, 6 },
+               .gate = { CGU_REG_SCR, 6, true },
        },
 
        /* Gate-only clocks */

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 934bf0e..9628d4e 100644 (file)
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
                int clr_ofs,
                int sta_ofs,
                u8 bit,
-               const struct clk_ops *ops)
+               const struct clk_ops *ops,
+               unsigned long flags)
 {
        struct mtk_clk_gate *cg;
        struct clk *clk;
@@ -172,6 +173,7 @@ struct clk *mtk_clk_register_gate(
        init.parent_names = parent_name ? &parent_name : NULL;
        init.num_parents = parent_name ? 1 : 0;
        init.ops = ops;
+       init.flags = flags;
 
        cg->regmap = regmap;
        cg->set_ofs = set_ofs;

diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 72ef89b..9f766df 100644 (file)
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
                int clr_ofs,
                int sta_ofs,
                u8 bit,
-               const struct clk_ops *ops);
+               const struct clk_ops *ops,
+               unsigned long flags);
 
 #endif /* __DRV_CLK_GATE_H */

diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index ab6ab07..905a231 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = {
                0x0080, 8, 2, 15),
        MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
                0x0080, 16, 3, 23),
-       MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
-               0x0080, 24, 2, 31),
+       MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
+               0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
 
        MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
                0x0090, 0, 3, 7),

diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc9..c2b46b1 100644 (file)
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -324,6 +324,10 @@ static const char * const anc_md32_parents[] = {
        "univpll_d5",
 };
 
+/*
+ * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
+ * critical as otherwise the system will hang after boot.
+ */
 static const struct mtk_composite top_muxes[] = {
        MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
            ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
@@ -331,8 +335,8 @@ static const struct mtk_composite top_muxes[] = {
            ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
        MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
            0x0040, 0, 2),
-       MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
-           0x0040, 16, 2),
+       MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+                 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
        MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
            0x0040, 24, 2),
        MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,33 +428,45 @@ static const struct mtk_gate_regs infra2_cg_regs = {
        .sta_ofs = 0x00b0,
 };
 
-#define GATE_ICG0(_id, _name, _parent, _shift) {       \
-       .id = _id,                                      \
-       .name = _name,                                  \
-       .parent_name = _parent,                         \
-       .regs = &infra0_cg_regs,                        \
-       .shift = _shift,                                \
-       .ops = &mtk_clk_gate_ops_setclr,                \
+#define GATE_ICG0(_id, _name, _parent, _shift) {               \
+       .id = _id,                                              \
+       .name = _name,                                          \
+       .parent_name = _parent,                                 \
+       .regs = &infra0_cg_regs,                                \
+       .shift = _shift,                                        \
+       .ops = &mtk_clk_gate_ops_setclr,                        \
 }
 
-#define GATE_ICG1(_id, _name, _parent, _shift) {       \
-       .id = _id,                                      \
-       .name = _name,                                  \
-       .parent_name = _parent,                         \
-       .regs = &infra1_cg_regs,                        \
-       .shift = _shift,                                \
-       .ops = &mtk_clk_gate_ops_setclr,                \
+#define GATE_ICG1(_id, _name, _parent, _shift)                 \
+       GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
+       .id = _id,                                              \
+       .name = _name,                                          \
+       .parent_name = _parent,                                 \
+       .regs = &infra1_cg_regs,                                \
+       .shift = _shift,                                        \
+       .ops = &mtk_clk_gate_ops_setclr,                        \
+       .flags = _flags,                                        \
 }
 
-#define GATE_ICG2(_id, _name, _parent, _shift) {       \
-       .id = _id,                                      \
-       .name = _name,                                  \
-       .parent_name = _parent,                         \
-       .regs = &infra2_cg_regs,                        \
-       .shift = _shift,                                \
-       .ops = &mtk_clk_gate_ops_setclr,                \
+#define GATE_ICG2(_id, _name, _parent, _shift)                 \
+       GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
+       .id = _id,                                              \
+       .name = _name,                                          \
+       .parent_name = _parent,                                 \
+       .regs = &infra2_cg_regs,                                \
+       .shift = _shift,                                        \
+       .ops = &mtk_clk_gate_ops_setclr,                        \
+       .flags = _flags,                                        \
 }
 
+/*
+ * Clock gates dramc and dramc_b are needed by the DRAM controller.
+ * We mark them as critical as otherwise the system will hang after boot.
+ */
 static const struct mtk_gate infra_clks[] = {
        GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
        GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
@@ -505,7 +521,8 @@ static const struct mtk_gate infra_clks[] = {
        GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
        GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
        GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
-       GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+       GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+                       "clk26m", 31, CLK_IS_CRITICAL),
        GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
        GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
        GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
@@ -516,7 +533,8 @@ static const struct mtk_gate infra_clks[] = {
        GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
        GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
        GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
-       GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
+       GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
+                       "clk26m", 11, CLK_IS_CRITICAL),
        GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
        GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
        GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 96c292c..deedeb3 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = {
        "univpll"
 };
 
-static const char * const ca57_parents[] __initconst = {
+static const char * const ca72_parents[] __initconst = {
        "clk26m",
        "armca15pll",
        "mainpll",
@@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = {
 
 static const struct mtk_composite cpu_muxes[] __initconst = {
        MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
-       MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
+       MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
 };
 
 static const struct mtk_composite top_muxes[] __initconst = {

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9c0ae42..5531dd2 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -130,7 +130,7 @@ int mtk_clk_register_gates(struct device_node *node,
                                gate->regs->set_ofs,
                                gate->regs->clr_ofs,
                                gate->regs->sta_ofs,
-                               gate->shift, gate->ops);
+                               gate->shift, gate->ops, gate->flags);
 
                if (IS_ERR(clk)) {
                        pr_err("Failed to register clk %s: %ld\n",
@@ -167,7 +167,7 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
                mux->mask = BIT(mc->mux_width) - 1;
                mux->shift = mc->mux_shift;
                mux->lock = lock;
-
+               mux->flags = mc->mux_flags;
                mux_hw = &mux->hw;
                mux_ops = &clk_mux_ops;
 

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f83c2bb..fb27b5b 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -81,15 +81,13 @@ struct mtk_composite {
        signed char divider_shift;
        signed char divider_width;
 
+       u8 mux_flags;
+
        signed char num_parents;
 };
 
-/*
- * In case the rate change propagation to parent clocks is undesirable,
- * this macro allows to specify the clock flags manually.
- */
-#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,     \
-                       _gate, _flags) {                                \
+#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift,           \
+                               _width, _gate, _flags, _muxflags) {     \
                .id = _id,                                              \
                .name = _name,                                          \
                .mux_reg = _reg,                                        \
@@ -101,8 +99,18 @@ struct mtk_composite {
                .parent_names = _parents,                               \
                .num_parents = ARRAY_SIZE(_parents),                    \
                .flags = _flags,                                        \
+               .mux_flags = _muxflags,                                 \
        }
 
+/*
+ * In case the rate change propagation to parent clocks is undesirable,
+ * this macro allows to specify the clock flags manually.
+ */
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,     \
+                       _gate, _flags)                                  \
+               MUX_GATE_FLAGS_2(_id, _name, _parents, _reg,            \
+                                       _shift, _width, _gate, _flags, 0)
+
 /*
  * Unless necessary, all MUX_GATE clocks propagate rate changes to their
  * parent clock by default.
@@ -111,7 +119,11 @@ struct mtk_composite {
        MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
                _gate, CLK_SET_RATE_PARENT)
 
-#define MUX(_id, _name, _parents, _reg, _shift, _width) {              \
+#define MUX(_id, _name, _parents, _reg, _shift, _width)                        \
+       MUX_FLAGS(_id, _name, _parents, _reg,                           \
+                 _shift, _width, CLK_SET_RATE_PARENT)
+
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) {        \
                .id = _id,                                              \
                .name = _name,                                          \
                .mux_reg = _reg,                                        \
@@ -121,7 +133,7 @@ struct mtk_composite {
                .divider_shift = -1,                                    \
                .parent_names = _parents,                               \
                .num_parents = ARRAY_SIZE(_parents),                    \
-               .flags = CLK_SET_RATE_PARENT,                           \
+               .flags = _flags,                                \
        }
 
 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,        \
@@ -158,6 +170,7 @@ struct mtk_gate {
        const struct mtk_gate_regs *regs;
        int shift;
        const struct clk_ops *ops;
+       unsigned long flags;
 };
 
 int mtk_clk_register_gates(struct device_node *node,

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 58fa5c2..7131dcf 100644 (file)
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1703,6 +1703,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
                .enable_mask = BIT(4),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_0_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1802,6 +1805,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
                .enable_mask = BIT(30),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_1_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
+                       .num_parents = 1,
                        .ops = &clk_branch2_ops,
                },
        },

diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 8aea623..76e4e5b 100644 (file)
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -194,7 +194,8 @@
 #define CLK_INFRA_PMICWRAP             11
 #define CLK_INFRA_CLK_13M              12
 #define CLK_INFRA_CA53SEL               13
-#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_CA57SEL               14 /* Deprecated. Don't use it. */
+#define CLK_INFRA_CA72SEL               14
 #define CLK_INFRA_NR_CLK                15
 
 /* PERI_SYS */