Merge branch 'clk-pm-runtime' into clk-next

* clk-pm-runtime:
  clk: samsung: exynos-audss: Add support for runtime PM
  clk: samsung: exynos-audss: Use local variable for controller's device
  clk: samsung: exynos5433: Add support for runtime PM
  clk: samsung: Add support for runtime PM
  clk: Add support for runtime PM

diff --cc Documentation/devicetree/bindings/clock/exynos5433-clock.txt
Simple merge

diff --cc drivers/clk/clk.c
Simple merge

diff --cc drivers/clk/samsung/clk-exynos-audss.c
index b117783,ab494c1..5bfc92e
--- 1/drivers/clk/samsung/clk-exynos-audss.c
--- 2/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@@ -178,13 -178,24 +178,24 @@@ static int exynos_audss_clk_probe(struc
                        }
                }
        }
-       clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
+ 
+       /*
+        * Enable runtime PM here to allow the clock core using runtime PM
+        * for the registered clocks. Additionally, we increase the runtime
+        * PM usage count before registering the clocks, to prevent the
+        * clock core from runtime suspending the device.
+        */
+       pm_runtime_get_noresume(dev);
+       pm_runtime_set_active(dev);
+       pm_runtime_enable(dev);
+ 
+       clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
                                mout_audss_p, ARRAY_SIZE(mout_audss_p),
 -                              CLK_SET_RATE_NO_REPARENT,
 +                              CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
                                reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
  
-       cdclk = devm_clk_get(&pdev->dev, "cdclk");
-       sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
+       cdclk = devm_clk_get(dev, "cdclk");
+       sclk_audio = devm_clk_get(dev, "sclk_audio");
        if (!IS_ERR(cdclk))
                mout_i2s_p[1] = __clk_get_name(cdclk);
        if (!IS_ERR(sclk_audio))
@@@ -194,15 -205,15 +205,15 @@@
                                CLK_SET_RATE_NO_REPARENT,
                                reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
  
-       clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
+       clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
 -                              "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
 -                              0, &lock);
 +                              "mout_audss", CLK_SET_RATE_PARENT,
 +                              reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
  
-       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
+       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
 -                              "dout_aud_bus", "dout_srp", 0,
 +                              "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
                                reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
  
-       clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
+       clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
                                "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
                                &lock);