drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 30 Mar 2022 05:09:48 +0000 (01:09 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Apr 2022 21:47:43 +0000 (17:47 -0400)
This data has no dependencies, so encapsulate it all within
amdgpu_discovery.c.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
drivers/gpu/drm/amd/amdgpu/soc15.c

index 94666c2..9485b6b 100644 (file)
@@ -1926,11 +1926,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
        adev->firmware.gpu_info_fw = NULL;
 
        if (adev->mman.discovery_bin) {
-               amdgpu_discovery_get_gfx_info(adev);
-
                /*
                 * FIXME: The bounding box is still needed by Navi12, so
-                * temporarily read it from gpu_info firmware. Should be droped
+                * temporarily read it from gpu_info firmware. Should be dropped
                 * when DAL no longer needs it.
                 */
                if (adev->asic_type != CHIP_NAVI12)
index a676685..0c359ad 100644 (file)
@@ -1046,7 +1046,7 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 
 /* ================================================== */
 
-int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
+static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
        struct ip_discovery_header *ihdr;
@@ -1212,7 +1212,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
        return -EINVAL;
 }
 
-void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
+static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 {
        int vcn_harvest_count = 0;
        int umc_harvest_count = 0;
@@ -1257,7 +1257,7 @@ union gc_info {
        struct gc_info_v2_0 v2;
 };
 
-int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
+static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
        union gc_info *gc_info;
@@ -1271,10 +1271,8 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
        bhdr = (struct binary_header *)adev->mman.discovery_bin;
        offset = le16_to_cpu(bhdr->table_list[GC].offset);
 
-       if (!offset) {
-               dev_err(adev->dev, "invalid GC table offset\n");
-               return -EINVAL;
-       }
+       if (!offset)
+               return 0;
 
        gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
 
@@ -1363,10 +1361,8 @@ int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
        bhdr = (struct binary_header *)adev->mman.discovery_bin;
        offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
 
-       if (!offset) {
-               dev_err(adev->dev, "invalid mall table offset\n");
-               return -EINVAL;
-       }
+       if (!offset)
+               return 0;
 
        mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
 
@@ -1400,7 +1396,7 @@ union vcn_info {
        struct vcn_info_v1_0 v1;
 };
 
-int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
+static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
        union vcn_info *vcn_info;
@@ -1420,10 +1416,8 @@ int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
        bhdr = (struct binary_header *)adev->mman.discovery_bin;
        offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
 
-       if (!offset) {
-               dev_err(adev->dev, "invalid vcn table offset\n");
-               return -EINVAL;
-       }
+       if (!offset)
+               return 0;
 
        vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
 
@@ -2037,6 +2031,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
                        return -EINVAL;
 
                amdgpu_discovery_harvest_ip(adev);
+               amdgpu_discovery_get_gfx_info(adev);
+               amdgpu_discovery_get_mall_info(adev);
+               amdgpu_discovery_get_vcn_info(adev);
                break;
        }
 
index 3735c53..8563dd4 100644 (file)
 #define DISCOVERY_TMR_OFFSET    (64 << 10)
 
 void amdgpu_discovery_fini(struct amdgpu_device *adev);
-int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
-void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
                                     int *major, int *minor, int *revision);
-
-int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
-int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev);
-int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev);
 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev);
 
 #endif /* __AMDGPU_DISCOVERY__ */
index 3ee7322..fde6154 100644 (file)
@@ -701,25 +701,12 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 
 static void soc15_reg_base_init(struct amdgpu_device *adev)
 {
-       int r;
-
        /* Set IP register base before any HW register access */
        switch (adev->asic_type) {
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_RAVEN:
-               vega10_reg_base_init(adev);
-               break;
        case CHIP_RENOIR:
-               /* It's safe to do ip discovery here for Renoir,
-                * it doesn't support SRIOV. */
-               if (amdgpu_discovery) {
-                       r = amdgpu_discovery_reg_base_init(adev);
-                       if (r == 0)
-                               break;
-                       DRM_WARN("failed to init reg base from ip discovery table, "
-                                "fallback to legacy init method\n");
-               }
                vega10_reg_base_init(adev);
                break;
        case CHIP_VEGA20: