{
unsigned long mask = SCU_PM_POWEROFF << (cpu * 8);
- if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
+ if ((readl(shmobile_scu_base + 8) & mask) == mask)
return 1;
return 0;
irqchip_init();
/* route all interrupts to ARM */
- __raw_writel(0x73ffffff, base + INT2NTSR0);
- __raw_writel(0xffffffff, base + INT2NTSR1);
+ writel(0x73ffffff, base + INT2NTSR0);
+ writel(0xffffffff, base + INT2NTSR1);
/* unmask all known interrupts in INTCS2 */
- __raw_writel(0x08330773, base + INT2SMSKCR0);
- __raw_writel(0x00311110, base + INT2SMSKCR1);
+ writel(0x08330773, base + INT2SMSKCR0);
+ writel(0x00311110, base + INT2SMSKCR1);
iounmap(base);
}
irqchip_init();
/* route all interrupts to ARM */
- __raw_writel(0xffffffff, base + INT2NTSR0);
- __raw_writel(0x3fffffff, base + INT2NTSR1);
+ writel(0xffffffff, base + INT2NTSR0);
+ writel(0x3fffffff, base + INT2NTSR1);
/* unmask all known interrupts in INTCS2 */
- __raw_writel(0xfffffff0, base + INT2SMSKCR0);
- __raw_writel(0xfff7ffff, base + INT2SMSKCR1);
- __raw_writel(0xfffbffdf, base + INT2SMSKCR2);
- __raw_writel(0xbffffffc, base + INT2SMSKCR3);
- __raw_writel(0x003fee3f, base + INT2SMSKCR4);
+ writel(0xfffffff0, base + INT2SMSKCR0);
+ writel(0xfff7ffff, base + INT2SMSKCR1);
+ writel(0xfffbffdf, base + INT2SMSKCR2);
+ writel(0xbffffffc, base + INT2SMSKCR3);
+ writel(0x003fee3f, base + INT2SMSKCR4);
iounmap(base);
}
void __iomem *base = ioremap(HPBREG_BASE, 0x1000);
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
- __raw_writel(__pa(shmobile_boot_vector), base + AVECR);
+ writel(__pa(shmobile_boot_vector), base + AVECR);
/* setup r8a7779 specific SCU bits */
shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus);
unsigned int lcpu = cpu_logical_map(cpu);
void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE);
- if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3)
- __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */
+ if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3)
+ writel(1 << lcpu, cpg2 + WUPCR); /* wake up */
else
- __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */
+ writel(1 << lcpu, cpg2 + SRESCR); /* reset */
iounmap(cpg2);
return 0;
}
void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE);
/* Map the reset vector (in headsmp.S) */
- __raw_writel(0, ap + APARMBAREA); /* 4k */
- __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR);
+ writel(0, ap + APARMBAREA); /* 4k */
+ writel(__pa(shmobile_boot_vector), sysc + SBAR);
iounmap(sysc);
iounmap(ap);