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perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids
author
Kan Liang
<kan.liang@linux.intel.com>
Fri, 18 Jun 2021 15:12:53 +0000
(08:12 -0700)
committer
Peter Zijlstra
<peterz@infradead.org>
Wed, 23 Jun 2021 16:30:55 +0000
(18:30 +0200)
On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.
Update intel_spr_extra_regs[] to support them.
Fixes:
61b985e3e775
("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link:
https://lore.kernel.org/r/1624029174-122219-3-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/core.c
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diff --git
a/arch/x86/events/intel/core.c
b/arch/x86/events/intel/core.c
index
d39991b
..
e442b55
100644
(file)
--- a/
arch/x86/events/intel/core.c
+++ b/
arch/x86/events/intel/core.c
@@
-280,6
+280,8
@@
static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
+ INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
+ INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
EVENT_EXTRA_END
};