drm/amd/display: Optimize passive update planes.

[Why]
passive update planes still spends a litte more
time on some cases.

[How]
Remove unnecessary trace which involving in some register read.
Disable debug output for release build.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3a71049..5fd5209 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1570,9 +1570,6 @@ static void commit_planes_for_stream(struct dc *dc,
                }
        }
 
-       if (update_type == UPDATE_TYPE_FULL)
-               context_timing_trace(dc, &context->res_ctx);
-
        // Update Type FAST, Surface updates
        if (update_type == UPDATE_TYPE_FAST) {
                /* Lock the top pipe while updating plane addrs, since freesync requires