drm/amdgpu: Fix consecutive DPC recovery failures.
authorAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Mon, 24 Aug 2020 16:30:47 +0000 (12:30 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Sep 2020 21:25:04 +0000 (17:25 -0400)
Cache the PCI state on boot and before each case where we might
loose it.

v2: Add pci_restore_state while caching the PCI state to avoid
breaking PCI core logic for stuff like suspend/resume.

v3: Extract pci_restore_state from amdgpu_device_cache_pci_state
to avoid superflous restores during GPU resets and suspend/resumes.

v4: Style fixes.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/soc15.c

index 207eba0..6125ba9 100644 (file)
@@ -989,7 +989,9 @@ struct amdgpu_device {
        atomic_t                        throttling_logging_enabled;
        struct ratelimit_state          throttling_logging_rs;
        uint32_t                        ras_features;
+
        bool                            in_pci_err_recovery;
+       struct pci_saved_state          *pci_state;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1269,6 +1271,9 @@ pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
 void amdgpu_pci_resume(struct pci_dev *pdev);
 
+bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
+bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
+
 #include "amdgpu_object.h"
 
 /* used by df_v3_6.c and amdgpu_pmu.c */
index 36a8f12..9be9355 100644 (file)
@@ -1292,7 +1292,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
                dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
                pci_set_power_state(dev->pdev, PCI_D0);
-               pci_restore_state(dev->pdev);
+               amdgpu_device_load_pci_state(dev->pdev);
                r = pci_enable_device(dev->pdev);
                if (r)
                        DRM_WARN("pci_enable_device failed (%d)\n", r);
@@ -1305,7 +1305,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
                drm_kms_helper_poll_disable(dev);
                dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
                amdgpu_device_suspend(dev, true);
-               pci_save_state(dev->pdev);
+               amdgpu_device_cache_pci_state(dev->pdev);
                /* Shut down the device */
                pci_disable_device(dev->pdev);
                pci_set_power_state(dev->pdev, PCI_D3cold);
@@ -3408,6 +3408,10 @@ fence_driver_init:
        if (r)
                dev_err(adev->dev, "amdgpu_pmu_init failed\n");
 
+       /* Have stored pci confspace at hand for restore in sudden PCI error */
+       if (amdgpu_device_cache_pci_state(adev->pdev))
+               pci_restore_state(pdev);
+
        return 0;
 
 failed:
@@ -3432,6 +3436,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
        flush_delayed_work(&adev->delayed_init_work);
        adev->shutdown = true;
 
+       kfree(adev->pci_state);
+
        /* make sure IB test finished before entering exclusive mode
         * to avoid preemption on IB test
         * */
@@ -4852,7 +4858,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
        /* wait for asic to come out of reset */
        msleep(500);
 
-       pci_restore_state(pdev);
+       amdgpu_device_load_pci_state(pdev);
 
        /* confirm  ASIC came out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
@@ -4932,6 +4938,9 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
 out:
 
        if (!r) {
+               if (amdgpu_device_cache_pci_state(adev->pdev))
+                       pci_restore_state(adev->pdev);
+
                DRM_INFO("PCIe error recovery succeeded\n");
        } else {
                DRM_ERROR("PCIe error recovery failed, err:%d", r);
@@ -4971,3 +4980,50 @@ void amdgpu_pci_resume(struct pci_dev *pdev)
 
        amdgpu_device_unlock_adev(adev);
 }
+
+bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
+{
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       struct amdgpu_device *adev = drm_to_adev(dev);
+       int r;
+
+       r = pci_save_state(pdev);
+       if (!r) {
+               kfree(adev->pci_state);
+
+               adev->pci_state = pci_store_saved_state(pdev);
+
+               if (!adev->pci_state) {
+                       DRM_ERROR("Failed to store PCI saved state");
+                       return false;
+               }
+       } else {
+               DRM_WARN("Failed to save PCI state, err:%d\n", r);
+               return false;
+       }
+
+       return true;
+}
+
+bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
+{
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       struct amdgpu_device *adev = drm_to_adev(dev);
+       int r;
+
+       if (!adev->pci_state)
+               return false;
+
+       r = pci_load_saved_state(pdev, adev->pci_state);
+
+       if (!r) {
+               pci_restore_state(pdev);
+       } else {
+               DRM_WARN("Failed to load PCI state, err:%d\n", r);
+               return false;
+       }
+
+       return true;
+}
+
+
index e9daab1..5fafb3d 100644 (file)
@@ -1315,7 +1315,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
                if (amdgpu_is_atpx_hybrid()) {
                        pci_ignore_hotplug(pdev);
                } else {
-                       pci_save_state(pdev);
+                       amdgpu_device_cache_pci_state(pdev);
                        pci_disable_device(pdev);
                        pci_ignore_hotplug(pdev);
                        pci_set_power_state(pdev, PCI_D3cold);
@@ -1348,7 +1348,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
                        pci_set_master(pdev);
                } else {
                        pci_set_power_state(pdev, PCI_D0);
-                       pci_restore_state(pdev);
+                       amdgpu_device_load_pci_state(pdev);
                        ret = pci_enable_device(pdev);
                        if (ret)
                                return ret;
index 4d14023..0ec6603 100644 (file)
@@ -311,7 +311,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
        /* disable BM */
        pci_clear_master(adev->pdev);
 
-       pci_save_state(adev->pdev);
+       amdgpu_device_cache_pci_state(adev->pdev);
 
        if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
                dev_info(adev->dev, "GPU smu mode1 reset\n");
@@ -323,7 +323,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 
        if (ret)
                dev_err(adev->dev, "GPU mode1 reset failed\n");
-       pci_restore_state(adev->pdev);
+       amdgpu_device_load_pci_state(adev->pdev);
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
index 2f93c47..ddd55e3 100644 (file)
@@ -484,13 +484,13 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
        /* disable BM */
        pci_clear_master(adev->pdev);
 
-       pci_save_state(adev->pdev);
+       amdgpu_device_cache_pci_state(adev->pdev);
 
        ret = psp_gpu_reset(adev);
        if (ret)
                dev_err(adev->dev, "GPU mode1 reset failed\n");
 
-       pci_restore_state(adev->pdev);
+       amdgpu_device_load_pci_state(adev->pdev);
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {