arm64: dts: renesas: rzg2l: Drop WDT2 nodes

On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU.  Using it from a Cortex-A55 CPU
would result in unexpected behaviour.  Hence drop all WDT2 nodes and
their references from the affected SoC and SoM DTSI files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4b..c1fb29d 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -820,21 +820,6 @@
                        status = "disabled";
                };
 
-               wdt2: watchdog@12800400 {
-                       compatible = "renesas,r9a07g043-wdt",
-                                    "renesas,rzg2l-wdt";
-                       reg = <0 0x12800400 0 0x400>;
-                       clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
-                                <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
-                       clock-names = "pclk", "oscclk";
-                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "wdt", "perrout";
-                       resets = <&cpg R9A07G043_WDT2_PRESETN>;
-                       power-domains = <&cpg>;
-                       status = "disabled";
-               };
-
                ostm0: timer@12801000 {
                        compatible = "renesas,r9a07g043-ostm",
                                     "renesas,ostm";

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2283d4f..c606d9e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -994,21 +994,6 @@
                        status = "disabled";
                };
 
-               wdt2: watchdog@12800400 {
-                       compatible = "renesas,r9a07g044-wdt",
-                                    "renesas,rzg2l-wdt";
-                       reg = <0 0x12800400 0 0x400>;
-                       clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
-                                <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
-                       clock-names = "pclk", "oscclk";
-                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "wdt", "perrout";
-                       resets = <&cpg R9A07G044_WDT2_PRESETN>;
-                       power-domains = <&cpg>;
-                       status = "disabled";
-               };
-
                ostm0: timer@12801000 {
                        compatible = "renesas,r9a07g044-ostm",
                                     "renesas,ostm";

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 358d4c3..7c7bbe3 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1000,21 +1000,6 @@
                        status = "disabled";
                };
 
-               wdt2: watchdog@12800400 {
-                       compatible = "renesas,r9a07g054-wdt",
-                                    "renesas,rzg2l-wdt";
-                       reg = <0 0x12800400 0 0x400>;
-                       clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
-                                <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
-                       clock-names = "pclk", "oscclk";
-                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "wdt", "perrout";
-                       resets = <&cpg R9A07G054_WDT2_PRESETN>;
-                       power-domains = <&cpg>;
-                       status = "disabled";
-               };
-
                ostm0: timer@12801000 {
                        compatible = "renesas,r9a07g054-ostm",
                                     "renesas,ostm";

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index c4faff0..fbbb4f0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -351,8 +351,3 @@
        status = "okay";
        timeout-sec = <60>;
 };
-
-&wdt2 {
-       status = "okay";
-       timeout-sec = <60>;
-};

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 78e6e23..8a0d568 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -276,8 +276,3 @@
        status = "okay";
        timeout-sec = <60>;
 };
-
-&wdt2 {
-       status = "okay";
-       timeout-sec = <60>;
-};