arm64: errata: Add detection for TRBE overwrite in FILL mode

Arm Neoverse-N2 and the Cortex-A710 cores are affected
by a CPU erratum where the TRBE will overwrite the trace buffer
in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
when it reaches the limit and wraps to the base to continue
writing upto 3 cache lines. This will overwrite any trace that
was written previously.

Add the Neoverse-N2 erratum(#2139208) and Cortex-A710 erratum
(#2119858) to the detection logic.

This will be used by the TRBE driver in later patches to work
around the issue. The detection has been kept with the core
arm64 errata framework list to make sure :
  - We don't duplicate the framework in TRBE driver
  - The errata detection is advertised like the rest
    of the CPU errata.

Note that the Kconfig entries are not fully active until the
TRBE driver implements the work around.

Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
cc: Leo Yan <leo.yan@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20211019163153.3692640-3-suzuki.poulose@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index d410a47..2f99229 100644 (file)
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -92,12 +92,16 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-N1     | #1349291        | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-500         | #841119,826419  | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5c7ae4c..26bd128 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -666,6 +666,47 @@ config ARM64_ERRATUM_1508412
 
          If unsure, say Y.
 
+config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       bool
+
+config ARM64_ERRATUM_2119858
+       bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
+       default y
+       depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
+       depends on CORESIGHT_TRBE
+       select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       help
+         This option adds the workaround for ARM Cortex-A710 erratum 2119858.
+
+         Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
+         data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
+         the event of a WRAP event.
+
+         Work around the issue by always making sure we move the TRBPTR_EL1 by
+         256 bytes before enabling the buffer and filling the first 256 bytes of
+         the buffer with ETM ignore packets upon disabling.
+
+         If unsure, say Y.
+
+config ARM64_ERRATUM_2139208
+       bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
+       default y
+       depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
+       depends on CORESIGHT_TRBE
+       select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       help
+         This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
+
+         Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
+         data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
+         the event of a WRAP event.
+
+         Work around the issue by always making sure we move the TRBPTR_EL1 by
+         256 bytes before enabling the buffer and filling the first 256 bytes of
+         the buffer with ETM ignore packets upon disabling.
+
+         If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e2c20c0..ccd7573 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -340,6 +340,18 @@ static const struct midr_range erratum_1463225[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
+#ifdef CONFIG_ARM64_ERRATUM_2139208
+       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_2119858
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+#endif
+       {},
+};
+#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
        {
@@ -533,6 +545,19 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
                ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
        },
+#endif
+#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       {
+               /*
+                * The erratum work around is handled within the TRBE
+                * driver and can be applied per-cpu. So, we can allow
+                * a late CPU to come online with this erratum.
+                */
+               .desc = "ARM erratum 2119858 or 2139208",
+               .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
+               .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
+               CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
+       },
 #endif
        {
        }

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 49305c2..1ccb921 100644 (file)
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -53,6 +53,7 @@ WORKAROUND_1418040
 WORKAROUND_1463225
 WORKAROUND_1508412
 WORKAROUND_1542419
+WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 WORKAROUND_CAVIUM_23154
 WORKAROUND_CAVIUM_27456
 WORKAROUND_CAVIUM_30115