Merge tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...

Pull char/misc driver updates from Greg KH:
 "Here is the large set of char/misc driver patches for 5.8-rc1

  Included in here are:

   - habanalabs driver updates, loads

   - mhi bus driver updates

   - extcon driver updates

   - clk driver updates (approved by the clock maintainer)

   - firmware driver updates

   - fpga driver updates

   - gnss driver updates

   - coresight driver updates

   - interconnect driver updates

   - parport driver updates (it's still alive!)

   - nvmem driver updates

   - soundwire driver updates

   - visorbus driver updates

   - w1 driver updates

   - various misc driver updates

  In short, loads of different driver subsystem updates along with the
  drivers as well.

  All have been in linux-next for a while with no reported issues"

* tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (233 commits)
  habanalabs: correctly cast u64 to void*
  habanalabs: initialize variable to default value
  extcon: arizona: Fix runtime PM imbalance on error
  extcon: max14577: Add proper dt-compatible strings
  extcon: adc-jack: Fix an error handling path in 'adc_jack_probe()'
  extcon: remove redundant assignment to variable idx
  w1: omap-hdq: print dev_err if irq flags are not cleared
  w1: omap-hdq: fix interrupt handling which did show spurious timeouts
  w1: omap-hdq: fix return value to be -1 if there is a timeout
  w1: omap-hdq: cleanup to add missing newline for some dev_dbg
  /dev/mem: Revoke mappings when a driver claims the region
  misc: xilinx-sdfec: convert get_user_pages() --> pin_user_pages()
  misc: xilinx-sdfec: cleanup return value in xsdfec_table_write()
  misc: xilinx-sdfec: improve get_user_pages_fast() error handling
  nvmem: qfprom: remove incorrect write support
  habanalabs: handle MMU cache invalidation timeout
  habanalabs: don't allow hard reset with open processes
  habanalabs: GAUDI does not support soft-reset
  habanalabs: add print for soft reset due to event
  habanalabs: improve MMU cache invalidation code
  ...

diff --cc drivers/bus/mhi/core/init.c
Simple merge

diff --cc drivers/fpga/dfl-afu-dma-region.c
Simple merge

diff --cc drivers/hwtracing/coresight/coresight-cti-platform.c
Simple merge

diff --cc drivers/misc/cardreader/rtsx_pcr.c
Simple merge

diff --cc drivers/mmc/host/sdhci-of-arasan.c
index 2a4c8a2,d01f762..db9b544
--- 1/drivers/mmc/host/sdhci-of-arasan.c
--- 2/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@@ -123,13 -98,8 +123,9 @@@ struct sdhci_arasan_clk_data 
        void            *clk_of_data;
  };
  
- struct sdhci_arasan_zynqmp_clk_data {
-       const struct zynqmp_eemi_ops *eemi_ops;
- };
- 
  /**
 - * struct sdhci_arasan_data
 + * struct sdhci_arasan_data - Arasan Controller Data
 + *
   * @host:             Pointer to the main SDHCI host structure.
   * @clk_ahb:          Pointer to the AHB clock
   * @phy:              Pointer to the generic phy
@@@ -726,159 -745,8 +714,154 @@@ static const struct clk_ops zynqmp_samp
        .set_phase = sdhci_zynqmp_sampleclk_set_phase,
  };
  
 +/**
 + * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 + *
 + * @hw:                       Pointer to the hardware clock structure.
 + * @degrees:          The clock phase shift between 0 - 359.
 + *
 + * Set the SD Output Clock Tap Delays for Output path
 + *
 + * Return: 0 on success and error value on error
 + */
 +static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
 +{
 +      struct sdhci_arasan_clk_data *clk_data =
 +              container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
 +      struct sdhci_arasan_data *sdhci_arasan =
 +              container_of(clk_data, struct sdhci_arasan_data, clk_data);
 +      struct sdhci_host *host = sdhci_arasan->host;
 +      u8 tap_delay, tap_max = 0;
 +
 +      /*
 +       * This is applicable for SDHCI_SPEC_300 and above
 +       * Versal does not set phase for <=25MHz clock.
 +       * If degrees is zero, no need to do anything.
 +       */
 +      if (host->version < SDHCI_SPEC_300 ||
 +          host->timing == MMC_TIMING_LEGACY ||
 +          host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
 +              return 0;
 +
 +      switch (host->timing) {
 +      case MMC_TIMING_MMC_HS:
 +      case MMC_TIMING_SD_HS:
 +      case MMC_TIMING_UHS_SDR25:
 +      case MMC_TIMING_UHS_DDR50:
 +      case MMC_TIMING_MMC_DDR52:
 +              /* For 50MHz clock, 30 Taps are available */
 +              tap_max = 30;
 +              break;
 +      case MMC_TIMING_UHS_SDR50:
 +              /* For 100MHz clock, 15 Taps are available */
 +              tap_max = 15;
 +              break;
 +      case MMC_TIMING_UHS_SDR104:
 +      case MMC_TIMING_MMC_HS200:
 +              /* For 200MHz clock, 8 Taps are available */
 +              tap_max = 8;
 +      default:
 +              break;
 +      }
 +
 +      tap_delay = (degrees * tap_max) / 360;
 +
 +      /* Set the Clock Phase */
 +      if (tap_delay) {
 +              u32 regval;
 +
 +              regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 +              regval |= SDHCI_OTAPDLY_ENABLE;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 +              regval |= tap_delay;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 +      }
 +
 +      return 0;
 +}
 +
 +static const struct clk_ops versal_sdcardclk_ops = {
 +      .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 +      .set_phase = sdhci_versal_sdcardclk_set_phase,
 +};
 +
 +/**
 + * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 + *
 + * @hw:                       Pointer to the hardware clock structure.
 + * @degrees:          The clock phase shift between 0 - 359.
 + *
 + * Set the SD Input Clock Tap Delays for Input path
 + *
 + * Return: 0 on success and error value on error
 + */
 +static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
 +{
 +      struct sdhci_arasan_clk_data *clk_data =
 +              container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
 +      struct sdhci_arasan_data *sdhci_arasan =
 +              container_of(clk_data, struct sdhci_arasan_data, clk_data);
 +      struct sdhci_host *host = sdhci_arasan->host;
 +      u8 tap_delay, tap_max = 0;
 +
 +      /*
 +       * This is applicable for SDHCI_SPEC_300 and above
 +       * Versal does not set phase for <=25MHz clock.
 +       * If degrees is zero, no need to do anything.
 +       */
 +      if (host->version < SDHCI_SPEC_300 ||
 +          host->timing == MMC_TIMING_LEGACY ||
 +          host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
 +              return 0;
 +
 +      switch (host->timing) {
 +      case MMC_TIMING_MMC_HS:
 +      case MMC_TIMING_SD_HS:
 +      case MMC_TIMING_UHS_SDR25:
 +      case MMC_TIMING_UHS_DDR50:
 +      case MMC_TIMING_MMC_DDR52:
 +              /* For 50MHz clock, 120 Taps are available */
 +              tap_max = 120;
 +              break;
 +      case MMC_TIMING_UHS_SDR50:
 +              /* For 100MHz clock, 60 Taps are available */
 +              tap_max = 60;
 +              break;
 +      case MMC_TIMING_UHS_SDR104:
 +      case MMC_TIMING_MMC_HS200:
 +              /* For 200MHz clock, 30 Taps are available */
 +              tap_max = 30;
 +      default:
 +              break;
 +      }
 +
 +      tap_delay = (degrees * tap_max) / 360;
 +
 +      /* Set the Clock Phase */
 +      if (tap_delay) {
 +              u32 regval;
 +
 +              regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 +              regval |= SDHCI_ITAPDLY_CHGWIN;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 +              regval |= SDHCI_ITAPDLY_ENABLE;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 +              regval |= tap_delay;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 +              regval &= ~SDHCI_ITAPDLY_CHGWIN;
 +              sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 +      }
 +
 +      return 0;
 +}
 +
 +static const struct clk_ops versal_sampleclk_ops = {
 +      .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
 +      .set_phase = sdhci_versal_sampleclk_set_phase,
 +};
 +
  static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
  {
-       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-       struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
-       struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
-               sdhci_arasan->clk_data.clk_of_data;
-       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
        u16 clk;
  
        clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

diff --cc drivers/parport/procfs.c
Simple merge

diff --cc include/linux/cpuhotplug.h
Simple merge

diff --cc include/linux/ioport.h
Simple merge