ARM: dts: rockchip: Fix power-controller node names for rk3288
authorElaine Zhang <zhangqing@rock-chips.com>
Sat, 17 Apr 2021 11:29:40 +0000 (13:29 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 10 May 2021 07:31:29 +0000 (09:31 +0200)
Use more generic names (as recommended in the device tree specification
or the binding documentation)

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-4-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3288.dtsi

index 1e6594f..d6dbfbd 100644 (file)
                         *      *_HDMI          HDMI
                         *      *_MIPI_*        MIPI
                         */
-                       pd_vio@RK3288_PD_VIO {
+                       power-domain@RK3288_PD_VIO {
                                reg = <RK3288_PD_VIO>;
                                clocks = <&cru ACLK_IEP>,
                                         <&cru ACLK_ISP>,
                         * Note: The following 3 are HEVC(H.265) clocks,
                         * and on the ACLK_HEVC_NIU (NOC).
                         */
-                       pd_hevc@RK3288_PD_HEVC {
+                       power-domain@RK3288_PD_HEVC {
                                reg = <RK3288_PD_HEVC>;
                                clocks = <&cru ACLK_HEVC>,
                                         <&cru SCLK_HEVC_CABAC>,
                         * (video endecoder & decoder) clocks that on the
                         * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
                         */
-                       pd_video@RK3288_PD_VIDEO {
+                       power-domain@RK3288_PD_VIDEO {
                                reg = <RK3288_PD_VIDEO>;
                                clocks = <&cru ACLK_VCODEC>,
                                         <&cru HCLK_VCODEC>;
                         * Note: ACLK_GPU is the GPU clock,
                         * and on the ACLK_GPU_NIU (NOC).
                         */
-                       pd_gpu@RK3288_PD_GPU {
+                       power-domain@RK3288_PD_GPU {
                                reg = <RK3288_PD_GPU>;
                                clocks = <&cru ACLK_GPU>;
                                pm_qos = <&qos_gpu_r>,