mtd: add DT bindings for the Intel IXP4xx Flash
authorLinus Walleij <linus.walleij@linaro.org>
Sun, 20 Oct 2019 23:00:41 +0000 (01:00 +0200)
committerMiquel Raynal <miquel.raynal@bootlin.com>
Tue, 29 Oct 2019 13:24:51 +0000 (14:24 +0100)
This adds device tree bindings for the Intel IXP4xx
flash controller, a simple physmap which however need a
specific big-endian or mixed-endian access pattern to the
memory.

Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt
new file mode 100644 (file)
index 0000000..4bdcb92
--- /dev/null
@@ -0,0 +1,22 @@
+Flash device on Intel IXP4xx SoC
+
+This flash is regular CFI compatible (Intel or AMD extended) flash chips with
+specific big-endian or mixed-endian memory access pattern.
+
+Required properties:
+- compatible : must be "intel,ixp4xx-flash", "cfi-flash";
+- reg : memory address for the flash chip
+- bank-width : width in bytes of flash interface, should be <2>
+
+For the rest of the properties, see mtd-physmap.txt.
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+flash@50000000 {
+       compatible = "intel,ixp4xx-flash", "cfi-flash";
+       reg = <0x50000000 0x01000000>;
+       bank-width = <2>;
+};