arm64: dts: renesas: Add support for M3ULCB with R-Car M3e-2G
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 19 Jul 2021 15:38:40 +0000 (17:38 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 30 Jul 2021 13:07:25 +0000 (15:07 +0200)
Add support for the Renesas R-Car Starter Kit Pro equipped with an R-Car
M3e-2G SiP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/c566dfa5f07605a467f8705c3a2f637ea445b1ff.1626708063.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/Makefile
arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts [new file with mode: 0644]

index 169c4f3..8a2bec8 100644 (file)
@@ -68,5 +68,6 @@ dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb
 
 dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb.dtb
 
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts
new file mode 100644 (file)
index 0000000..8f215a0
--- /dev/null
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) with R-Car M3e-2G
+ *
+ * Copyright (C) 2021 Glider bv
+ *
+ * Based on r8a77961-ulcb.dts
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779m3.dtsi"
+#include "ulcb.dtsi"
+
+/ {
+       model = "Renesas M3ULCB board based on r8a779m3";
+       compatible = "renesas,m3ulcb", "renesas,r8a779m3", "renesas,r8a77961";
+
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x0 0x78000000>;
+       };
+
+       memory@480000000 {
+               device_type = "memory";
+               reg = <0x4 0x80000000 0x0 0x80000000>;
+       };
+
+       memory@600000000 {
+               device_type = "memory";
+               reg = <0x6 0x00000000 0x1 0x00000000>;
+       };
+};
+
+&du {
+       clocks = <&cpg CPG_MOD 724>,
+                <&cpg CPG_MOD 723>,
+                <&cpg CPG_MOD 722>,
+                <&versaclock5 1>,
+                <&versaclock5 3>,
+                <&versaclock5 2>;
+       clock-names = "du.0", "du.1", "du.2",
+                     "dclkin.0", "dclkin.1", "dclkin.2";
+};