cpufreq: imx-cpufreq-dt: support i.MX7ULP

i.MX7ULP's ARM core clock design is totally different compared
with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs
get_intermediate and target_intermedate to configure clk MUX ready,
before let OPP configure ARM core clk.
                                          |---FIRC
     |------RUN---...---SCS(MUX2) --------|
ARM --(MUX1)                              |---SPLL_PFD0(CLK_SET_RATE_GATE)
     |------HSRUN--...--HSRUN_SCS(MUX3)---|
                                          |---SRIC

FIRC is step clk, SPLL_PFD0 is the normal clk driving ARM core.
MUX2 and MUX3 share same inputs. So if MUX2/MUX3 both sources from
SPLL_PFD0, both MUXes will lose input when configure SPLL_PFD0.
So the target_intermediate will configure MUX2/MUX3 to FIRC, to avoid
ARM core lose clk when configure SPLL_PFD0.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
index de206d2..3fe9125 100644 (file)
--- a/drivers/cpufreq/imx-cpufreq-dt.c
+++ b/drivers/cpufreq/imx-cpufreq-dt.c
@@ -3,7 +3,9 @@
  * Copyright 2019 NXP
  */
 
+#include <linux/clk.h>
 #include <linux/cpu.h>
+#include <linux/cpufreq.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -12,8 +14,11 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 
+#include "cpufreq-dt.h"
+
 #define OCOTP_CFG3_SPEED_GRADE_SHIFT   8
 #define OCOTP_CFG3_SPEED_GRADE_MASK    (0x3 << 8)
 #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK     (0xf << 8)
@@ -22,20 +27,92 @@
 #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT    5
 #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK     (0x3 << 5)
 
+#define IMX7ULP_MAX_RUN_FREQ   528000
+
 /* cpufreq-dt device registered by imx-cpufreq-dt */
 static struct platform_device *cpufreq_dt_pdev;
 static struct opp_table *cpufreq_opp_table;
+static struct device *cpu_dev;
+
+enum IMX7ULP_CPUFREQ_CLKS {
+       ARM,
+       CORE,
+       SCS_SEL,
+       HSRUN_CORE,
+       HSRUN_SCS_SEL,
+       FIRC,
+};
+
+static struct clk_bulk_data imx7ulp_clks[] = {
+       { .id = "arm" },
+       { .id = "core" },
+       { .id = "scs_sel" },
+       { .id = "hsrun_core" },
+       { .id = "hsrun_scs_sel" },
+       { .id = "firc" },
+};
+
+static unsigned int imx7ulp_get_intermediate(struct cpufreq_policy *policy,
+                                            unsigned int index)
+{
+       return clk_get_rate(imx7ulp_clks[FIRC].clk);
+}
+
+static int imx7ulp_target_intermediate(struct cpufreq_policy *policy,
+                                       unsigned int index)
+{
+       unsigned int newfreq = policy->freq_table[index].frequency;
+
+       clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
+       clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
+
+       if (newfreq > IMX7ULP_MAX_RUN_FREQ)
+               clk_set_parent(imx7ulp_clks[ARM].clk,
+                              imx7ulp_clks[HSRUN_CORE].clk);
+       else
+               clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
+
+       return 0;
+}
+
+static struct cpufreq_dt_platform_data imx7ulp_data = {
+       .target_intermediate = imx7ulp_target_intermediate,
+       .get_intermediate = imx7ulp_get_intermediate,
+};
 
 static int imx_cpufreq_dt_probe(struct platform_device *pdev)
 {
-       struct device *cpu_dev = get_cpu_device(0);
+       struct platform_device *dt_pdev;
        u32 cell_value, supported_hw[2];
        int speed_grade, mkt_segment;
        int ret;
 
+       cpu_dev = get_cpu_device(0);
+
        if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL))
                return -ENODEV;
 
+       if (of_machine_is_compatible("fsl,imx7ulp")) {
+               ret = clk_bulk_get(cpu_dev, ARRAY_SIZE(imx7ulp_clks),
+                                  imx7ulp_clks);
+               if (ret)
+                       return ret;
+
+               dt_pdev = platform_device_register_data(NULL, "cpufreq-dt",
+                                                       -1, &imx7ulp_data,
+                                                       sizeof(imx7ulp_data));
+               if (IS_ERR(dt_pdev)) {
+                       clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
+                       ret = PTR_ERR(dt_pdev);
+                       dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
+                       return ret;
+               }
+
+               cpufreq_dt_pdev = dt_pdev;
+
+               return 0;
+       }
+
        ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
        if (ret)
                return ret;
@@ -98,7 +175,10 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
 static int imx_cpufreq_dt_remove(struct platform_device *pdev)
 {
        platform_device_unregister(cpufreq_dt_pdev);
-       dev_pm_opp_put_supported_hw(cpufreq_opp_table);
+       if (!of_machine_is_compatible("fsl,imx7ulp"))
+               dev_pm_opp_put_supported_hw(cpufreq_opp_table);
+       else
+               clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
 
        return 0;
 }