drm/amd/pm: enable BACO support for SMU 13.0.0
authorEvan Quan <evan.quan@amd.com>
Mon, 25 Apr 2022 09:20:40 +0000 (17:20 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 10 May 2022 21:53:10 +0000 (17:53 -0400)
Enable SMU 13.0.0 BACO support.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

index 4a52ab7..013be82 100644 (file)
@@ -282,5 +282,16 @@ int smu_v13_0_deep_sleep_control(struct smu_context *smu,
 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement);
 
+bool smu_v13_0_baco_is_support(struct smu_context *smu);
+
+enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
+
+int smu_v13_0_baco_set_state(struct smu_context *smu,
+                            enum smu_baco_state state);
+
+int smu_v13_0_baco_enter(struct smu_context *smu);
+
+int smu_v13_0_baco_exit(struct smu_context *smu);
+
 #endif
 #endif
index 2c57bc5..d73deb3 100644 (file)
@@ -2206,3 +2206,78 @@ int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
 
        return ret;
 }
+
+bool smu_v13_0_baco_is_support(struct smu_context *smu)
+{
+       struct smu_baco_context *smu_baco = &smu->smu_baco;
+
+       if (amdgpu_sriov_vf(smu->adev) ||
+           !smu_baco->platform_support)
+               return false;
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
+           !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
+               return false;
+
+       return true;
+}
+
+enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
+{
+       struct smu_baco_context *smu_baco = &smu->smu_baco;
+
+       return smu_baco->state;
+}
+
+int smu_v13_0_baco_set_state(struct smu_context *smu,
+                            enum smu_baco_state state)
+{
+       struct smu_baco_context *smu_baco = &smu->smu_baco;
+       struct amdgpu_device *adev = smu->adev;
+       int ret = 0;
+
+       if (smu_v13_0_baco_get_state(smu) == state)
+               return 0;
+
+       if (state == SMU_BACO_STATE_ENTER) {
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_EnterBaco,
+                                                     0,
+                                                     NULL);
+       } else {
+               ret = smu_cmn_send_smc_msg(smu,
+                                          SMU_MSG_ExitBaco,
+                                          NULL);
+               if (ret)
+                       return ret;
+
+               /* clear vbios scratch 6 and 7 for coming asic reinit */
+               WREG32(adev->bios_scratch_reg_offset + 6, 0);
+               WREG32(adev->bios_scratch_reg_offset + 7, 0);
+       }
+
+       if (!ret)
+               smu_baco->state = state;
+
+       return ret;
+}
+
+int smu_v13_0_baco_enter(struct smu_context *smu)
+{
+       int ret = 0;
+
+       ret = smu_v13_0_baco_set_state(smu,
+                                      SMU_BACO_STATE_ENTER);
+       if (ret)
+               return ret;
+
+       msleep(10);
+
+       return ret;
+}
+
+int smu_v13_0_baco_exit(struct smu_context *smu)
+{
+       return smu_v13_0_baco_set_state(smu,
+                                       SMU_BACO_STATE_EXIT);
+}
index 71312ed..44da7e0 100644 (file)
@@ -95,6 +95,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
        MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
        MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
+       MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
        MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
        MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
        MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
@@ -150,6 +151,7 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
        [SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
        [SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
        [SMU_FEATURE_GFX_ULV_BIT] = {1, FEATURE_GFX_ULV_BIT},
+       [SMU_FEATURE_BACO_BIT] = {1, FEATURE_BACO_BIT},
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
@@ -1595,6 +1597,11 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
        .set_tool_table_location = smu_v13_0_set_tool_table_location,
        .deep_sleep_control = smu_v13_0_deep_sleep_control,
        .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
+       .baco_is_support = smu_v13_0_baco_is_support,
+       .baco_get_state = smu_v13_0_baco_get_state,
+       .baco_set_state = smu_v13_0_baco_set_state,
+       .baco_enter = smu_v13_0_baco_enter,
+       .baco_exit = smu_v13_0_baco_exit,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)