RISC-V: Add Sstc extension support

This series implements Sstc extension support which was ratified
recently.  Before the Sstc extension, an SBI call is necessary to
generate timer interrupts as only M-mode have access to the timecompare
registers. Thus, there is significant latency to generate timer
interrupts at kernel.  For virtualized enviornments, its even worse as
the KVM handles the SBI call and uses a software timer to emulate the
timecomapre register.

Sstc extension solves both these problems by defining a
stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to
program a timer and recieve interrupt without supervisor execution
enviornment (M-mode/HS mode) intervention.

* palmer/riscv-sstc:
  RISC-V: Prefer sstc extension if available
  RISC-V: Enable sstc extension parsing from DT
  RISC-V: Add SSTC extension CSR details

diff --cc arch/riscv/include/asm/csr.h
Simple merge

diff --cc arch/riscv/include/asm/hwcap.h
index 3c8a5ca,b186fff..6f59ec6
--- 1/arch/riscv/include/asm/hwcap.h
--- 2/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -55,8 -53,7 +55,9 @@@ extern unsigned long elf_hwcap
  enum riscv_isa_ext_id {
        RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
        RISCV_ISA_EXT_SVPBMT,
 +      RISCV_ISA_EXT_ZICBOM,
 +      RISCV_ISA_EXT_ZIHINTPAUSE,
+       RISCV_ISA_EXT_SSTC,
        RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
  };
  

diff --cc arch/riscv/kernel/cpu.c
index a77c380,0016d93..0be8a24
--- 1/arch/riscv/kernel/cpu.c
--- 2/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@@ -93,8 -89,7 +93,9 @@@ int riscv_of_parent_hartid(struct devic
  static struct riscv_isa_ext_data isa_ext_arr[] = {
        __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
        __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
 +      __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
 +      __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+       __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
        __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
  };
  

diff --cc arch/riscv/kernel/cpufeature.c
index c233fbc,d1d83cd..553d755
--- 1/arch/riscv/kernel/cpufeature.c
--- 2/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@@ -201,8 -199,7 +201,9 @@@ void __init riscv_fill_hwcap(void
                        } else {
                                SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
                                SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 +                              SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 +                              SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+                               SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
                        }
  #undef SET_ISA_EXT_MAP
                }

diff --cc drivers/clocksource/timer-riscv.c
Simple merge