#include "display/intel_de.h"
#include "display/intel_display_trace.h"
#include "display/intel_display_types.h"
+#include "display/intel_dp_aux.h"
#include "display/intel_fdi_regs.h"
#include "display/intel_fifo_underrun.h"
+#include "display/intel_gmbus.h"
#include "display/intel_hotplug.h"
#include "display/intel_lpe_audio.h"
#include "display/intel_psr.h"
return hotplug;
}
-static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
-{
- wake_up_all(&dev_priv->display.gmbus.wait_queue);
-}
-
-static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
-{
- wake_up_all(&dev_priv->display.gmbus.wait_queue);
-}
-
#if defined(CONFIG_DEBUG_FS)
static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe,
intel_opregion_asle_intr(dev_priv);
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
}
static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
}
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
}
static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
if ((IS_G4X(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
}
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
}
if (pch_iir & SDE_AUX_MASK)
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
if (pch_iir & SDE_GMBUS)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
if (pch_iir & SDE_AUDIO_HDCP_MASK)
drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
}
if (pch_iir & SDE_AUX_MASK_CPT)
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
if (pch_iir & SDE_GMBUS_CPT)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
}
if (trigger_aux)
- dp_aux_irq_handler(i915);
+ intel_dp_aux_irq_handler(i915);
if (!pin_mask && !trigger_aux)
drm_err(&i915->drm,
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_ICP)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
}
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_CPT)
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
}
static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
if (de_iir & DE_AUX_CHANNEL_A)
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
if (de_iir & DE_GSE)
intel_opregion_asle_intr(dev_priv);
ivb_err_int_handler(dev_priv);
if (de_iir & DE_AUX_CHANNEL_A_IVB)
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
if (de_iir & DE_GSE_IVB)
intel_opregion_asle_intr(dev_priv);
ret = IRQ_HANDLED;
if (iir & gen8_de_port_aux_mask(dev_priv)) {
- dp_aux_irq_handler(dev_priv);
+ intel_dp_aux_irq_handler(dev_priv);
found = true;
}
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
(iir & BXT_DE_PORT_GMBUS)) {
- gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(dev_priv);
found = true;
}