habanalabs: fix ETR security issue
authorOhad Sharabi <osharabi@habana.ai>
Thu, 21 Jan 2021 20:25:52 +0000 (22:25 +0200)
committerOded Gabbay <ogabbay@kernel.org>
Wed, 27 Jan 2021 19:03:51 +0000 (21:03 +0200)
ETR should always be non-secured as it is used by the users to record
profiling/trace data.
This patch fixes the configuration to match those requirements.

Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
drivers/misc/habanalabs/gaudi/gaudi_coresight.c
drivers/misc/habanalabs/goya/goya_coresight.c
drivers/misc/habanalabs/include/gaudi/gaudi_masks.h
drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h

index 88a09d4..6e56fa1 100644 (file)
@@ -634,9 +634,21 @@ static int gaudi_config_etr(struct hl_device *hdev,
                WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
                WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
                WREG32(mmPSOC_ETR_MODE, input->sink_mode);
-               /* Workaround for H3 #HW-2075 bug: use small data chunks */
-               WREG32(mmPSOC_ETR_AXICTL, (is_host ? 0 : 0x700) |
-                                       PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
+               if (hdev->asic_prop.fw_security_disabled) {
+                       /* make ETR not privileged */
+                       val = FIELD_PREP(
+                                       PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
+                       /* make ETR non-secured (inverted logic) */
+                       val |= FIELD_PREP(
+                                       PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
+                       /*
+                        * Workaround for H3 #HW-2075 bug: use small data
+                        * chunks
+                        */
+                       val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK,
+                                                       is_host ? 0 : 7);
+                       WREG32(mmPSOC_ETR_AXICTL, val);
+               }
                WREG32(mmPSOC_ETR_DBALO,
                                lower_32_bits(input->buffer_address));
                WREG32(mmPSOC_ETR_DBAHI,
index 6fa0393..6b7445c 100644 (file)
@@ -434,8 +434,15 @@ static int goya_config_etr(struct hl_device *hdev,
                WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
                WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
                WREG32(mmPSOC_ETR_MODE, input->sink_mode);
-               WREG32(mmPSOC_ETR_AXICTL,
-                               0x700 | PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
+               if (hdev->asic_prop.fw_security_disabled) {
+                       /* make ETR not privileged */
+                       val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
+                       /* make ETR non-secured (inverted logic) */
+                       val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
+                       /* burst size 8 */
+                       val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 7);
+                       WREG32(mmPSOC_ETR_AXICTL, val);
+               }
                WREG32(mmPSOC_ETR_DBALO,
                                lower_32_bits(input->buffer_address));
                WREG32(mmPSOC_ETR_DBAHI,
index b9b90d0..b53aeda 100644 (file)
@@ -388,7 +388,10 @@ enum axi_id {
 #define RAZWI_INITIATOR_ID_X_Y_TPC6            RAZWI_INITIATOR_ID_X_Y(7, 6)
 #define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5  RAZWI_INITIATOR_ID_X_Y(8, 6)
 
-#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT                           1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT     1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK      0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK      0x2
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK                0xF00
 
 /* STLB_CACHE_INV */
 #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT                          0
index 067489b..9ff3cb2 100644 (file)
 #define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 #define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 
-#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT                           1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT     1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK      0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK      0x2
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK                0xF00
 
 #endif /* ASIC_REG_GOYA_MASKS_H_ */