Merge tag 'hisi-arm32-dt-for-5.10-tag2' of git://github.com/hisilicon/linux-hisi...

ARM: DT: Hisilicon ARM32 SoCs DT updates for 5.10 (take two)

- Fix the system controller compatible for the hi3620 and hip04 SoCs
- Add the basic device tree for the hisilicon SD5203 SoC

* tag 'hisi-arm32-dt-for-5.10-tag2' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: hisilicon: add SD5203 dts
  ARM: dts: hisilicon: fix the system controller compatible nodes

Link: https://lore.kernel.org/r/5F742717.5080405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8f89515..a457dca 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -359,6 +359,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
        mps2-an399.dtb
 dtb-$(CONFIG_ARCH_MOXART) += \
        moxart-uc7112lx.dtb
+dtb-$(CONFIG_ARCH_SD5203) += \
+       sd5203.dtb
 dtb-$(CONFIG_SOC_IMX1) += \
        imx1-ads.dtb \
        imx1-apf9328.dtb

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 355175b..f683440 100644 (file)
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -89,7 +89,7 @@
                };
 
                sysctrl: system-controller@802000 {
-                       compatible = "hisilicon,sysctrl";
+                       compatible = "hisilicon,sysctrl", "syscon";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0 0x802000 0x1000>;

diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index f5871b1..555bc6b 100644 (file)
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -213,7 +213,7 @@
                };
 
                sysctrl: sysctrl {
-                       compatible = "hisilicon,sysctrl";
+                       compatible = "hisilicon,sysctrl", "syscon";
                        reg = <0x3e00000 0x00100000>;
                };
 

diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
new file mode 100644 (file)
index 0000000..3cc9a23
--- /dev/null
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 Hisilicon Limited.
+ *
+ * DTS file for Hisilicon SD5203 Board
+ */
+
+/dts-v1/;
+
+/ {
+       model = "Hisilicon SD5203";
+       compatible = "H836ASDJ", "hisilicon,sd5203";
+       interrupt-parent = <&vic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0 {
+                       device_type = "cpu";
+                       compatible = "arm,arm926ej-s";
+                       reg = <0x0>;
+               };
+       };
+
+       memory@30000000 {
+               device_type = "memory";
+               reg = <0x30000000 0x8000000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges;
+
+               vic: interrupt-controller@10130000 {
+                       compatible = "snps,dw-apb-ictl";
+                       reg = <0x10130000 0x1000>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
+               refclk125mhz: refclk125mhz {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <125000000>;
+               };
+
+               timer0: timer@16002000 {
+                       compatible = "arm,sp804", "arm,primecell";
+                       reg = <0x16002000 0x1000>;
+                       interrupts = <4>;
+                       clocks = <&refclk125mhz>;
+                       clock-names = "apb_pclk";
+               };
+
+               timer1: timer@16003000 {
+                       compatible = "arm,sp804", "arm,primecell";
+                       reg = <0x16003000 0x1000>;
+                       interrupts = <5>;
+                       clocks = <&refclk125mhz>;
+                       clock-names = "apb_pclk";
+               };
+
+               uart0: serial@1600d000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x1600d000 0x1000>;
+                       bus_id = "uart0";
+                       clocks = <&refclk125mhz>;
+                       clock-names = "baudclk", "apb_pclk";
+                       reg-shift = <2>;
+                       interrupts = <17>;
+               };
+
+               uart1: serial@1600c000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x1600c000 0x1000>;
+                       clocks = <&refclk125mhz>;
+                       clock-names = "baudclk", "apb_pclk";
+                       reg-shift = <2>;
+                       interrupts = <16>;
+                       status = "disabled";
+               };
+       };
+};