drm/amdgpu: update vcn1.0 Non-DPG suspend sequence

update suspend register settings in Non-DPG mode.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 51a773a..0c1beef 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1119,10 +1119,10 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
                UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
 
-       /* put VCPU into reset */
-       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
-               UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
-               ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+       /* stall UMC channel */
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
+               UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+               ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 
        tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
                UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
@@ -1141,6 +1141,11 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
                UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
                ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
 
+       /* put VCPU into reset */
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+               UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+               ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
        WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
 
        vcn_v1_0_enable_clock_gating(adev);