arm64: dts: qcom: ipq6018: correct TCSR block area

According to Bjorn Andersson[1], &tcsr_q6 base is 0x01937000 with size
0x21000. Adjust qcom,halt-regs offsets (add 0xe000) to match the new
syscon base.

Also, rename to just &tcsr as Kathiravan T suggested.

[1] https://lore.kernel.org/r/YLgO0Aj1d4w9EcPv@yoga

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Link: https://lore.kernel.org/r/889aae1b88f120cb6281919d27164a959fbe69d0.1626948070.git.baruch@tkos.co.il
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 1549c2c..66da336 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -258,9 +258,9 @@
                        reg = <0x0 0x01905000 0x0 0x8000>;
                };
 
-               tcsr_q6: syscon@1945000 {
+               tcsr: syscon@1937000 {
                        compatible = "syscon";
-                       reg = <0x0 0x01945000 0x0 0xe000>;
+                       reg = <0x0 0x01937000 0x0 0x21000>;
                };
 
                blsp_dma: dma-controller@7884000 {
@@ -504,7 +504,7 @@
                        clocks = <&gcc GCC_PRNG_AHB_CLK>;
                        clock-names = "prng";
 
-                       qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+                       qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 
                        qcom,smem-states = <&wcss_smp2p_out 0>,
                                           <&wcss_smp2p_out 1>;