Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto updates from Herbert Xu:
 "Here is the crypto update for 5.3:

  API:
   - Test shash interface directly in testmgr
   - cra_driver_name is now mandatory

  Algorithms:
   - Replace arc4 crypto_cipher with library helper
   - Implement 5 way interleave for ECB, CBC and CTR on arm64
   - Add xxhash
   - Add continuous self-test on noise source to drbg
   - Update jitter RNG

  Drivers:
   - Add support for SHA204A random number generator
   - Add support for 7211 in iproc-rng200
   - Fix fuzz test failures in inside-secure
   - Fix fuzz test failures in talitos
   - Fix fuzz test failures in qat"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (143 commits)
  crypto: stm32/hash - remove interruptible condition for dma
  crypto: stm32/hash - Fix hmac issue more than 256 bytes
  crypto: stm32/crc32 - rename driver file
  crypto: amcc - remove memset after dma_alloc_coherent
  crypto: ccp - Switch to SPDX license identifiers
  crypto: ccp - Validate the the error value used to index error messages
  crypto: doc - Fix formatting of new crypto engine content
  crypto: doc - Add parameter documentation
  crypto: arm64/aes-ce - implement 5 way interleave for ECB, CBC and CTR
  crypto: arm64/aes-ce - add 5 way interleave routines
  crypto: talitos - drop icv_ool
  crypto: talitos - fix hash on SEC1.
  crypto: talitos - move struct talitos_edesc into talitos.h
  lib/scatterlist: Fix mapping iterator when sg->offset is greater than PAGE_SIZE
  crypto/NX: Set receive window credits to max number of CRBs in RxFIFO
  crypto: asymmetric_keys - select CRYPTO_HASH where needed
  crypto: serpent - mark __serpent_setkey_sbox noinline
  crypto: testmgr - dynamically allocate crypto_shash
  crypto: testmgr - dynamically allocate testvec_config
  crypto: talitos - eliminate unneeded 'done' functions at build time
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/crypto/sha512-glue.c
Simple merge

diff --cc arch/arm64/crypto/aes-ce.S
Simple merge

diff --cc arch/arm64/crypto/aes-modes.S
Simple merge

diff --cc arch/arm64/crypto/aes-neon.S
Simple merge

diff --cc arch/arm64/crypto/sha1-ce-glue.c
Simple merge

diff --cc arch/arm64/crypto/sha2-ce-glue.c
Simple merge

diff --cc arch/x86/crypto/aesni-intel_glue.c
Simple merge

diff --cc arch/x86/crypto/chacha_glue.c
Simple merge

diff --cc crypto/aead.c
Simple merge

diff --cc crypto/algapi.c
Simple merge

diff --cc crypto/arc4.c
Simple merge

diff --cc crypto/chacha20poly1305.c
Simple merge

diff --cc crypto/chacha_generic.c
Simple merge

diff --cc crypto/cryptd.c
Simple merge

diff --cc crypto/crypto_null.c
Simple merge

diff --cc crypto/deflate.c
Simple merge

diff --cc crypto/ghash-generic.c
Simple merge

diff --cc crypto/lrw.c
Simple merge

diff --cc crypto/lz4.c
Simple merge

diff --cc crypto/lz4hc.c
Simple merge

diff --cc crypto/lzo-rle.c
Simple merge

diff --cc crypto/lzo.c
Simple merge

diff --cc crypto/michael_mic.c
Simple merge

diff --cc crypto/rmd128.c
Simple merge

diff --cc crypto/rmd160.c
Simple merge

diff --cc crypto/rmd256.c
Simple merge

diff --cc crypto/rmd320.c
Simple merge

diff --cc crypto/serpent_generic.c
Simple merge

diff --cc crypto/skcipher.c
Simple merge

diff --cc crypto/tea.c
Simple merge

diff --cc crypto/testmgr.c
Simple merge

diff --cc crypto/testmgr.h
Simple merge

diff --cc crypto/tgr192.c
Simple merge

diff --cc crypto/zstd.c
Simple merge

diff --cc drivers/crypto/Kconfig
Simple merge

diff --cc drivers/crypto/amcc/crypto4xx_alg.c
Simple merge

diff --cc drivers/crypto/amcc/crypto4xx_core.c
Simple merge

diff --cc drivers/crypto/amcc/crypto4xx_core.h
Simple merge

diff --cc drivers/crypto/bcm/cipher.c
Simple merge

diff --cc drivers/crypto/bcm/spu2.c
Simple merge

diff --cc drivers/crypto/cavium/cpt/cptvf_algs.c
Simple merge

diff --cc drivers/crypto/ccp/ccp-crypto-aes.c
Simple merge

diff --cc drivers/crypto/ccp/ccp-dev.c
Simple merge

diff --cc drivers/crypto/ccp/ccp-dev.h
Simple merge

diff --cc drivers/crypto/ccp/ccp-ops.c
Simple merge

diff --cc drivers/crypto/ixp4xx_crypto.c
Simple merge

diff --cc drivers/crypto/mxs-dcp.c
Simple merge

diff --cc drivers/crypto/nx/nx-842-powernv.c
Simple merge

diff --cc drivers/crypto/nx/nx.c
Simple merge

diff --cc drivers/crypto/nx/nx_debugfs.c
Simple merge

diff --cc drivers/crypto/sahara.c
Simple merge

diff --cc drivers/crypto/stm32/Makefile
index ce77e38,23ce3bc..518e0e0
--- 1/drivers/crypto/stm32/Makefile
--- 2/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@@ -1,4 -1,3 +1,4 @@@
- obj-$(CONFIG_CRYPTO_DEV_STM32_CRC) += stm32_crc32.o
 +# SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_CRYPTO_DEV_STM32_CRC) += stm32-crc32.o
  obj-$(CONFIG_CRYPTO_DEV_STM32_HASH) += stm32-hash.o
  obj-$(CONFIG_CRYPTO_DEV_STM32_CRYP) += stm32-cryp.o

diff --cc drivers/crypto/stm32/stm32-crc32.c
index 0000000,29d2095..440c9f1
mode 000000,100644..100644
--- /dev/null
--- 2/drivers/crypto/stm32/stm32-crc32.c
+++ b/drivers/crypto/stm32/stm32-crc32.c
@@@ -1,0 -1,387 +1,387 @@@
 - * License terms:  GNU General Public License (GPL), version 2
++// SPDX-License-Identifier: GPL-2.0-only
+ /*
+  * Copyright (C) STMicroelectronics SA 2017
+  * Author: Fabien Dessenne <fabien.dessenne@st.com>
+  */
+ 
+ #include <linux/bitrev.h>
+ #include <linux/clk.h>
+ #include <linux/crc32poly.h>
+ #include <linux/module.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ 
+ #include <crypto/internal/hash.h>
+ 
+ #include <asm/unaligned.h>
+ 
+ #define DRIVER_NAME             "stm32-crc32"
+ #define CHKSUM_DIGEST_SIZE      4
+ #define CHKSUM_BLOCK_SIZE       1
+ 
+ /* Registers */
+ #define CRC_DR                  0x00000000
+ #define CRC_CR                  0x00000008
+ #define CRC_INIT                0x00000010
+ #define CRC_POL                 0x00000014
+ 
+ /* Registers values */
+ #define CRC_CR_RESET            BIT(0)
+ #define CRC_CR_REVERSE          (BIT(7) | BIT(6) | BIT(5))
+ #define CRC_INIT_DEFAULT        0xFFFFFFFF
+ 
+ #define CRC_AUTOSUSPEND_DELAY 50
+ 
+ struct stm32_crc {
+       struct list_head list;
+       struct device    *dev;
+       void __iomem     *regs;
+       struct clk       *clk;
+       u8               pending_data[sizeof(u32)];
+       size_t           nb_pending_bytes;
+ };
+ 
+ struct stm32_crc_list {
+       struct list_head dev_list;
+       spinlock_t       lock; /* protect dev_list */
+ };
+ 
+ static struct stm32_crc_list crc_list = {
+       .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
+       .lock     = __SPIN_LOCK_UNLOCKED(crc_list.lock),
+ };
+ 
+ struct stm32_crc_ctx {
+       u32 key;
+       u32 poly;
+ };
+ 
+ struct stm32_crc_desc_ctx {
+       u32    partial; /* crc32c: partial in first 4 bytes of that struct */
+       struct stm32_crc *crc;
+ };
+ 
+ static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
+ {
+       struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+ 
+       mctx->key = CRC_INIT_DEFAULT;
+       mctx->poly = CRC32_POLY_LE;
+       return 0;
+ }
+ 
+ static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
+ {
+       struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+ 
+       mctx->key = CRC_INIT_DEFAULT;
+       mctx->poly = CRC32C_POLY_LE;
+       return 0;
+ }
+ 
+ static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
+                           unsigned int keylen)
+ {
+       struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
+ 
+       if (keylen != sizeof(u32)) {
+               crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+               return -EINVAL;
+       }
+ 
+       mctx->key = get_unaligned_le32(key);
+       return 0;
+ }
+ 
+ static int stm32_crc_init(struct shash_desc *desc)
+ {
+       struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
+       struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
+       struct stm32_crc *crc;
+ 
+       spin_lock_bh(&crc_list.lock);
+       list_for_each_entry(crc, &crc_list.dev_list, list) {
+               ctx->crc = crc;
+               break;
+       }
+       spin_unlock_bh(&crc_list.lock);
+ 
+       pm_runtime_get_sync(ctx->crc->dev);
+ 
+       /* Reset, set key, poly and configure in bit reverse mode */
+       writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+       writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+       writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ 
+       /* Store partial result */
+       ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
+       ctx->crc->nb_pending_bytes = 0;
+ 
+       pm_runtime_mark_last_busy(ctx->crc->dev);
+       pm_runtime_put_autosuspend(ctx->crc->dev);
+ 
+       return 0;
+ }
+ 
+ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
+                           unsigned int length)
+ {
+       struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
+       struct stm32_crc *crc = ctx->crc;
+       u32 *d32;
+       unsigned int i;
+ 
+       pm_runtime_get_sync(crc->dev);
+ 
+       if (unlikely(crc->nb_pending_bytes)) {
+               while (crc->nb_pending_bytes != sizeof(u32) && length) {
+                       /* Fill in pending data */
+                       crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
+                       length--;
+               }
+ 
+               if (crc->nb_pending_bytes == sizeof(u32)) {
+                       /* Process completed pending data */
+                       writel_relaxed(*(u32 *)crc->pending_data,
+                                      crc->regs + CRC_DR);
+                       crc->nb_pending_bytes = 0;
+               }
+       }
+ 
+       d32 = (u32 *)d8;
+       for (i = 0; i < length >> 2; i++)
+               /* Process 32 bits data */
+               writel_relaxed(*(d32++), crc->regs + CRC_DR);
+ 
+       /* Store partial result */
+       ctx->partial = readl_relaxed(crc->regs + CRC_DR);
+ 
+       pm_runtime_mark_last_busy(crc->dev);
+       pm_runtime_put_autosuspend(crc->dev);
+ 
+       /* Check for pending data (non 32 bits) */
+       length &= 3;
+       if (likely(!length))
+               return 0;
+ 
+       if ((crc->nb_pending_bytes + length) >= sizeof(u32)) {
+               /* Shall not happen */
+               dev_err(crc->dev, "Pending data overflow\n");
+               return -EINVAL;
+       }
+ 
+       d8 = (const u8 *)d32;
+       for (i = 0; i < length; i++)
+               /* Store pending data */
+               crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
+ 
+       return 0;
+ }
+ 
+ static int stm32_crc_final(struct shash_desc *desc, u8 *out)
+ {
+       struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
+       struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
+ 
+       /* Send computed CRC */
+       put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
+                          ~ctx->partial : ctx->partial, out);
+ 
+       return 0;
+ }
+ 
+ static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
+                          unsigned int length, u8 *out)
+ {
+       return stm32_crc_update(desc, data, length) ?:
+              stm32_crc_final(desc, out);
+ }
+ 
+ static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
+                           unsigned int length, u8 *out)
+ {
+       return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
+ }
+ 
+ static struct shash_alg algs[] = {
+       /* CRC-32 */
+       {
+               .setkey         = stm32_crc_setkey,
+               .init           = stm32_crc_init,
+               .update         = stm32_crc_update,
+               .final          = stm32_crc_final,
+               .finup          = stm32_crc_finup,
+               .digest         = stm32_crc_digest,
+               .descsize       = sizeof(struct stm32_crc_desc_ctx),
+               .digestsize     = CHKSUM_DIGEST_SIZE,
+               .base           = {
+                       .cra_name               = "crc32",
+                       .cra_driver_name        = DRIVER_NAME,
+                       .cra_priority           = 200,
+                       .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
+                       .cra_blocksize          = CHKSUM_BLOCK_SIZE,
+                       .cra_alignmask          = 3,
+                       .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
+                       .cra_module             = THIS_MODULE,
+                       .cra_init               = stm32_crc32_cra_init,
+               }
+       },
+       /* CRC-32Castagnoli */
+       {
+               .setkey         = stm32_crc_setkey,
+               .init           = stm32_crc_init,
+               .update         = stm32_crc_update,
+               .final          = stm32_crc_final,
+               .finup          = stm32_crc_finup,
+               .digest         = stm32_crc_digest,
+               .descsize       = sizeof(struct stm32_crc_desc_ctx),
+               .digestsize     = CHKSUM_DIGEST_SIZE,
+               .base           = {
+                       .cra_name               = "crc32c",
+                       .cra_driver_name        = DRIVER_NAME,
+                       .cra_priority           = 200,
+                       .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
+                       .cra_blocksize          = CHKSUM_BLOCK_SIZE,
+                       .cra_alignmask          = 3,
+                       .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
+                       .cra_module             = THIS_MODULE,
+                       .cra_init               = stm32_crc32c_cra_init,
+               }
+       }
+ };
+ 
+ static int stm32_crc_probe(struct platform_device *pdev)
+ {
+       struct device *dev = &pdev->dev;
+       struct stm32_crc *crc;
+       struct resource *res;
+       int ret;
+ 
+       crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
+       if (!crc)
+               return -ENOMEM;
+ 
+       crc->dev = dev;
+ 
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       crc->regs = devm_ioremap_resource(dev, res);
+       if (IS_ERR(crc->regs)) {
+               dev_err(dev, "Cannot map CRC IO\n");
+               return PTR_ERR(crc->regs);
+       }
+ 
+       crc->clk = devm_clk_get(dev, NULL);
+       if (IS_ERR(crc->clk)) {
+               dev_err(dev, "Could not get clock\n");
+               return PTR_ERR(crc->clk);
+       }
+ 
+       ret = clk_prepare_enable(crc->clk);
+       if (ret) {
+               dev_err(crc->dev, "Failed to enable clock\n");
+               return ret;
+       }
+ 
+       pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
+       pm_runtime_use_autosuspend(dev);
+ 
+       pm_runtime_get_noresume(dev);
+       pm_runtime_set_active(dev);
+       pm_runtime_enable(dev);
+ 
+       platform_set_drvdata(pdev, crc);
+ 
+       spin_lock(&crc_list.lock);
+       list_add(&crc->list, &crc_list.dev_list);
+       spin_unlock(&crc_list.lock);
+ 
+       ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+       if (ret) {
+               dev_err(dev, "Failed to register\n");
+               clk_disable_unprepare(crc->clk);
+               return ret;
+       }
+ 
+       dev_info(dev, "Initialized\n");
+ 
+       pm_runtime_put_sync(dev);
+ 
+       return 0;
+ }
+ 
+ static int stm32_crc_remove(struct platform_device *pdev)
+ {
+       struct stm32_crc *crc = platform_get_drvdata(pdev);
+       int ret = pm_runtime_get_sync(crc->dev);
+ 
+       if (ret < 0)
+               return ret;
+ 
+       spin_lock(&crc_list.lock);
+       list_del(&crc->list);
+       spin_unlock(&crc_list.lock);
+ 
+       crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
+ 
+       pm_runtime_disable(crc->dev);
+       pm_runtime_put_noidle(crc->dev);
+ 
+       clk_disable_unprepare(crc->clk);
+ 
+       return 0;
+ }
+ 
+ #ifdef CONFIG_PM
+ static int stm32_crc_runtime_suspend(struct device *dev)
+ {
+       struct stm32_crc *crc = dev_get_drvdata(dev);
+ 
+       clk_disable_unprepare(crc->clk);
+ 
+       return 0;
+ }
+ 
+ static int stm32_crc_runtime_resume(struct device *dev)
+ {
+       struct stm32_crc *crc = dev_get_drvdata(dev);
+       int ret;
+ 
+       ret = clk_prepare_enable(crc->clk);
+       if (ret) {
+               dev_err(crc->dev, "Failed to prepare_enable clock\n");
+               return ret;
+       }
+ 
+       return 0;
+ }
+ #endif
+ 
+ static const struct dev_pm_ops stm32_crc_pm_ops = {
+       SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+                               pm_runtime_force_resume)
+       SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
+                          stm32_crc_runtime_resume, NULL)
+ };
+ 
+ static const struct of_device_id stm32_dt_ids[] = {
+       { .compatible = "st,stm32f7-crc", },
+       {},
+ };
+ MODULE_DEVICE_TABLE(of, stm32_dt_ids);
+ 
+ static struct platform_driver stm32_crc_driver = {
+       .probe  = stm32_crc_probe,
+       .remove = stm32_crc_remove,
+       .driver = {
+               .name           = DRIVER_NAME,
+               .pm             = &stm32_crc_pm_ops,
+               .of_match_table = stm32_dt_ids,
+       },
+ };
+ 
+ module_platform_driver(stm32_crc_driver);
+ 
+ MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+ MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
+ MODULE_LICENSE("GPL");

diff --cc drivers/crypto/stm32/stm32-hash.c
Simple merge

diff --cc drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
Simple merge

diff --cc drivers/crypto/talitos.c
Simple merge

diff --cc drivers/crypto/vmx/aes_cbc.c
Simple merge

diff --cc drivers/crypto/vmx/aes_ctr.c
Simple merge

diff --cc drivers/crypto/vmx/aes_xts.c
Simple merge

diff --cc drivers/crypto/vmx/vmx.c
Simple merge

diff --cc drivers/i2c/i2c-core-acpi.c
Simple merge

diff --cc drivers/net/ppp/Kconfig
Simple merge

diff --cc drivers/net/ppp/ppp_mppe.c
index 66c8e65,de3b57d..bd3c80b
--- 1/drivers/net/ppp/ppp_mppe.c
--- 2/drivers/net/ppp/ppp_mppe.c
+++ b/drivers/net/ppp/ppp_mppe.c
@@@ -63,16 -64,8 +64,9 @@@ MODULE_AUTHOR("Frank Cusack <fcusack@fc
  MODULE_DESCRIPTION("Point-to-Point Protocol Microsoft Point-to-Point Encryption support");
  MODULE_LICENSE("Dual BSD/GPL");
  MODULE_ALIAS("ppp-compress-" __stringify(CI_MPPE));
 +MODULE_SOFTDEP("pre: arc4");
  MODULE_VERSION("1.0.2");
  
- static unsigned int
- setup_sg(struct scatterlist *sg, const void *address, unsigned int length)
- {
-       sg_set_buf(sg, address, length);
-       return length;
- }
- 
  #define SHA1_PAD_SIZE 40
  
  /*

diff --cc fs/cifs/Kconfig
Simple merge

diff --cc fs/cifs/cifsfs.c
Simple merge

diff --cc include/crypto/aead.h
Simple merge

diff --cc include/crypto/algapi.h
Simple merge

diff --cc include/crypto/internal/hash.h
Simple merge

diff --cc include/crypto/internal/skcipher.h
Simple merge

diff --cc include/crypto/skcipher.h
Simple merge

diff --cc include/linux/crypto.h
Simple merge

diff --cc lib/scatterlist.c
Simple merge

diff --cc net/mac80211/Kconfig
Simple merge

diff --cc net/mac80211/cfg.c
Simple merge

diff --cc net/mac80211/ieee80211_i.h
Simple merge

diff --cc net/mac80211/key.h
Simple merge

diff --cc net/mac80211/main.c
Simple merge

diff --cc net/mac80211/mlme.c
Simple merge

diff --cc net/mac80211/tkip.c
Simple merge

diff --cc net/mac80211/tkip.h
Simple merge

diff --cc net/mac80211/wep.c
Simple merge

diff --cc net/mac80211/wep.h
Simple merge

diff --cc net/mac80211/wpa.c
Simple merge

diff --cc net/wireless/Kconfig
Simple merge

diff --cc net/wireless/lib80211_crypt_tkip.c
Simple merge

diff --cc net/wireless/lib80211_crypt_wep.c
Simple merge