drm/i915/tgl+: Fix interrupt handling for DP AUX transactions

Unmask/enable AUX interrupts on all ports on TGL+. So far the interrupts
worked only on port A, which meant each transaction on other ports took
10ms.

Cc: <stable@vger.kernel.org> # v5.4+
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504075828.20348-1-imre.deak@intel.com
(cherry picked from commit 054318c7e35f1d7d06b216143fff5f32405047ee)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d91557d..8a2b838 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3361,7 +3361,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
                GEN8_PIPE_CDCLK_CRC_DONE;
        u32 de_pipe_enables;
-       u32 de_port_masked = GEN8_AUX_CHANNEL_A;
+       u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
        u32 de_port_enables;
        u32 de_misc_masked = GEN8_DE_EDP_PSR;
        enum pipe pipe;
@@ -3369,18 +3369,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        if (INTEL_GEN(dev_priv) <= 10)
                de_misc_masked |= GEN8_DE_MISC_GSE;
 
-       if (INTEL_GEN(dev_priv) >= 9) {
-               de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
-                                 GEN9_AUX_CHANNEL_D;
-               if (IS_GEN9_LP(dev_priv))
-                       de_port_masked |= BXT_DE_PORT_GMBUS;
-       }
-
-       if (INTEL_GEN(dev_priv) >= 11)
-               de_port_masked |= ICL_AUX_CHANNEL_E;
-
-       if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
-               de_port_masked |= CNL_AUX_CHANNEL_F;
+       if (IS_GEN9_LP(dev_priv))
+               de_port_masked |= BXT_DE_PORT_GMBUS;
 
        de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
                                           GEN8_PIPE_FIFO_UNDERRUN;