drm/amd/display: [FW Promotion] Release 0.0.34

[Header Changes]
       - Add new SCRATCH0 status bits for detecting restore state

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index bbcb8ed..0051b10 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b
+#define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 33
+#define DMUB_FW_VERSION_REVISION 34
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -170,7 +170,7 @@ union dmub_fw_boot_status {
                uint32_t dal_fw : 1;
                uint32_t mailbox_rdy : 1;
                uint32_t optimized_init_done : 1;
-               uint32_t reserved : 29;
+               uint32_t restore_required : 1;
        } bits;
        uint32_t all;
 };
@@ -179,6 +179,7 @@ enum dmub_fw_boot_status_bit {
        DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
        DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1),
        DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
+       DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3),
 };
 
 /* Register bit definition for SCRATCH15 */
@@ -301,6 +302,10 @@ enum dmub_cmd_type {
        DMUB_CMD__VBIOS = 128,
 };
 
+enum dmub_out_cmd_type {
+       DMUB_OUT_CMD__NULL = 0,
+};
+
 #pragma pack(push, 1)
 
 struct dmub_cmd_header {