ARM: dts: ixp4xx: Add Arcom Vulcan device tree

This adds a device tree for the Arcom Vulcan IXP42x board.

Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 86852e8..b08ae56 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -245,7 +245,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
        intel-ixp42x-iomega-nas100d.dtb \
        intel-ixp42x-dlink-dsm-g600.dtb \
        intel-ixp43x-gateworks-gw2358.dtb \
-       intel-ixp42x-netgear-wg302v2.dtb
+       intel-ixp42x-netgear-wg302v2.dtb \
+       intel-ixp42x-arcom-vulcan.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += \
        keystone-k2hk-evm.dtb \
        keystone-k2l-evm.dtb \

diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
new file mode 100644 (file)
index 0000000..7200126
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Arcom/Eurotech Vulcan board.
+ * This board is a single board computer in the PC/104 form factor based on
+ * IXP425, and was released around 2005. It previously had the name "Mercury".
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Arcom/Eurotech Vulcan";
+       compatible = "arcom,vulcan", "intel,ixp42x";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x4000000>;
+       };
+
+       chosen {
+               /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
+               bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
+               stdout-path = "uart0:115200n8";
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       onewire {
+               compatible = "w1-gpio";
+               gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+       };
+
+       soc {
+               bus@c4000000 {
+                       flash@0,0 {
+                               compatible = "intel,ixp4xx-flash", "cfi-flash";
+                               bank-width = <2>;
+                               /*
+                                * 32 MB of Flash in 0x20000 byte blocks
+                                * mapped in at CS0 and CS1.
+                                *
+                                * The documentation mentions the existence
+                                * of a 16MB version, which we conveniently
+                                * ignore. Shout if you own one!
+                                */
+                               reg = <0 0x00000000 0x2000000>;
+
+                               /* Expansion bus settings */
+                               intel,ixp4xx-eb-t3 = <3>;
+                               intel,ixp4xx-eb-byte-access-on-halfword = <1>;
+                               intel,ixp4xx-eb-write-enable = <1>;
+
+                               partitions {
+                                       compatible = "redboot-fis";
+                                       fis-index-block = <0x1ff>;
+                               };
+                       };
+                       sram@2,0 {
+                               /* 256 KB SDRAM memory at CS2 */
+                               compatible = "shared-dma-pool";
+                               device_type = "memory";
+                               reg = <2 0x00000000 0x40000>;
+                               no-map;
+                               /* Expansion bus settings */
+                               intel,ixp4xx-eb-t3 = <1>;
+                               intel,ixp4xx-eb-t4 = <2>;
+                               intel,ixp4xx-eb-ahb-split-transfers = <1>;
+                               intel,ixp4xx-eb-write-enable = <1>;
+                               intel,ixp4xx-eb-byte-access = <1>;
+                       };
+                       serial@3,0 {
+                               /*
+                                * 8250-compatible Exar XR16L2551 2 x UART
+                                *
+                                * CHECKME: if special tweaks are needed, then fix the
+                                * operating system to handle it.
+                                */
+                               compatible = "exar,xr16l2551", "ns8250";
+                               reg = <3 0x00000000 0x10>;
+                               interrupt-parent = <&gpio0>;
+                               interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                               clock-frequency = <1843200>;
+                               /* Expansion bus settings */
+                               intel,ixp4xx-eb-t3 = <3>;
+                               intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
+                               intel,ixp4xx-eb-write-enable = <1>;
+                               intel,ixp4xx-eb-byte-access = <1>;
+                       };
+                       gpio1: gpio@4,0 {
+                               /*
+                                * MMIO GPIO in one byte
+                                */
+                               compatible = "arcom,vulcan-gpio";
+                               reg = <4 0x00000000 0x1>;
+                               /* Expansion bus settings */
+                               intel,ixp4xx-eb-write-enable = <1>;
+                               intel,ixp4xx-eb-byte-access = <1>;
+                       };
+                       watchdog@5,0 {
+                               compatible = "maxim,max6369";
+                               reg = <5 0x00000000 0x1>;
+                               /* Expansion bus settings */
+                               intel,ixp4xx-eb-write-enable = <1>;
+                               intel,ixp4xx-eb-byte-access = <1>;
+                       };
+               };
+
+               pci@c0000000 {
+                       status = "ok";
+
+                       /*
+                        * Taken from Vulcan PCI boardfile.
+                        *
+                        * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
+                        * per slot. This interrupt is shared (OR:ed) by all four pins.
+                        */
+                       interrupt-map =
+                       /* IDSEL 1 */
+                       <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
+                       <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
+                       <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
+                       <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
+                       /* IDSEL 2 */
+                       <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
+                       <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
+                       <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
+                       <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
+               };
+
+               /* EthB */
+               ethernet@c8009000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 3>;
+                       queue-txready = <&qmgr 20>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy0>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               phy0: ethernet-phy@0 {
+                                       reg = <0>;
+                               };
+
+                               phy1: ethernet-phy@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               /* EthC */
+               ethernet@c800a000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 4>;
+                       queue-txready = <&qmgr 21>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy1>;
+               };
+       };
+};