drm/amdgpu: attr to control SS2.0 bias level (v2)
authorSathishkumar S <sathishkumar.sundararaju@amd.com>
Sun, 30 May 2021 05:17:16 +0000 (10:47 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 4 Jun 2021 16:40:00 +0000 (12:40 -0400)
add sysfs attr to read/write smartshift bias level.
document smartshift_bias sysfs attr.

V2: add attr to amdgpu_device_attrs and use attr_update (Lijo)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu/amdgpu.rst
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/pm/amdgpu_pm.c

index 6cce26b..364680c 100644 (file)
@@ -316,3 +316,9 @@ smartshift_dgpu_power
 
 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
    :doc: smartshift_dgpu_power
+
+smartshift_bias
+---------------
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+   :doc: smartshift_bias
index 267e9e1..2d044f7 100644 (file)
@@ -211,6 +211,7 @@ extern int amdgpu_discovery;
 extern int amdgpu_mes;
 extern int amdgpu_noretry;
 extern int amdgpu_force_asic_type;
+extern int amdgpu_smartshift_bias;
 #ifdef CONFIG_HSA_AMD
 extern int sched_policy;
 extern bool debug_evictions;
@@ -268,6 +269,10 @@ extern int amdgpu_num_kcq;
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 
+/* smasrt shift bias level limits */
+#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
+#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
+
 struct amdgpu_device;
 struct amdgpu_ib;
 struct amdgpu_cs_parser;
index 809aa76..c080ba1 100644 (file)
@@ -173,6 +173,7 @@ int amdgpu_tmz = -1; /* auto */
 uint amdgpu_freesync_vid_mode;
 int amdgpu_reset_method = -1; /* auto */
 int amdgpu_num_kcq = -1;
+int amdgpu_smartshift_bias;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 
index bf9da64..2e1286f 100644 (file)
@@ -1903,6 +1903,67 @@ out:
        return r;
 }
 
+/**
+ * DOC: smartshift_bias
+ *
+ * The amdgpu driver provides a sysfs API for reporting the
+ * smartshift(SS2.0) bias level. The value ranges from -100 to 100
+ * and the default is 0. -100 sets maximum preference to APU
+ * and 100 sets max perference to dGPU.
+ */
+
+static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
+                                         struct device_attribute *attr,
+                                         char *buf)
+{
+       int r = 0;
+
+       r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
+
+       return r;
+}
+
+static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
+                                         struct device_attribute *attr,
+                                         const char *buf, size_t count)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = drm_to_adev(ddev);
+       int r = 0;
+       int bias = 0;
+
+       if (amdgpu_in_reset(adev))
+               return -EPERM;
+       if (adev->in_suspend && !adev->in_runpm)
+               return -EPERM;
+
+       r = pm_runtime_get_sync(ddev->dev);
+       if (r < 0) {
+               pm_runtime_put_autosuspend(ddev->dev);
+               return r;
+       }
+
+       r = kstrtoint(buf, 10, &bias);
+       if (r)
+               goto out;
+
+       if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
+               bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
+       else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
+               bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
+
+       amdgpu_smartshift_bias = bias;
+       r = count;
+
+       /* TODO: upadte bias level with SMU message */
+
+out:
+       pm_runtime_mark_last_busy(ddev->dev);
+       pm_runtime_put_autosuspend(ddev->dev);
+       return r;
+}
+
+
 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
                                uint32_t mask, enum amdgpu_device_attr_states *states)
 {
@@ -1923,6 +1984,23 @@ static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device
        return 0;
 }
 
+static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
+                              uint32_t mask, enum amdgpu_device_attr_states *states)
+{
+       uint32_t ss_power, size;
+
+       if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+               *states = ATTR_STATE_UNSUPPORTED;
+       else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+                (void *)&ss_power, &size))
+               *states = ATTR_STATE_UNSUPPORTED;
+       else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+                (void *)&ss_power, &size))
+               *states = ATTR_STATE_UNSUPPORTED;
+
+       return 0;
+}
+
 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
        AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
        AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -1953,6 +2031,8 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
                              .attr_update = ss_power_attr_update),
        AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
                              .attr_update = ss_power_attr_update),
+       AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
+                             .attr_update = ss_bias_attr_update),
 };
 
 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,