ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger

The flash write protect pin is currently named 'FW_WP_AP', which is
how the signal is called in the schematics. The Chrome OS ABI
requires the pin to be named 'AP_FLASH_WP_L', which is also how
it is called on all other veyron devices. Rename the pin to match
the ABI.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200106135142.1.I3f99ac8399a564c88ff48ae6290cc691b47c16ae@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
index 7e7ef8e..6ece714 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
@@ -380,7 +380,11 @@
                          "PWR_LED1",
                          "TPM_INT_H",
                          "SPK_ON",
-                         "FW_WP_AP",
+                         /*
+                          * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
+                          * it FW_WP_AP.
+                          */
+                         "AP_FLASH_WP_L",
                          "",
 
                          "CPU_NMI",