i2c: mediatek: add i2c compatible for MT8188

Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.

Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 8e69853..bd8abba 100644 (file)
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
        [OFFSET_DCM_EN] = 0xf88,
 };
 
+static const u16 mt_i2c_regs_v3[] = {
+       [OFFSET_DATA_PORT] = 0x0,
+       [OFFSET_INTR_MASK] = 0x8,
+       [OFFSET_INTR_STAT] = 0xc,
+       [OFFSET_CONTROL] = 0x10,
+       [OFFSET_TRANSFER_LEN] = 0x14,
+       [OFFSET_TRANSAC_LEN] = 0x18,
+       [OFFSET_DELAY_LEN] = 0x1c,
+       [OFFSET_TIMING] = 0x20,
+       [OFFSET_START] = 0x24,
+       [OFFSET_EXT_CONF] = 0x28,
+       [OFFSET_LTIMING] = 0x2c,
+       [OFFSET_HS] = 0x30,
+       [OFFSET_IO_CONFIG] = 0x34,
+       [OFFSET_FIFO_ADDR_CLR] = 0x38,
+       [OFFSET_SDA_TIMING] = 0x3c,
+       [OFFSET_TRANSFER_LEN_AUX] = 0x44,
+       [OFFSET_CLOCK_DIV] = 0x48,
+       [OFFSET_SOFTRESET] = 0x50,
+       [OFFSET_MULTI_DMA] = 0x8c,
+       [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
+       [OFFSET_SLAVE_ADDR] = 0x94,
+       [OFFSET_DEBUGSTAT] = 0xe4,
+       [OFFSET_DEBUGCTRL] = 0xe8,
+       [OFFSET_FIFO_STAT] = 0xf4,
+       [OFFSET_FIFO_THRESH] = 0xf8,
+       [OFFSET_DCM_EN] = 0xf88,
+};
+
 struct mtk_i2c_compatible {
        const struct i2c_adapter_quirks *quirks;
        const u16 *regs;
@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible mt8186_compat = {
        .max_dma_support = 36,
 };
 
+static const struct mtk_i2c_compatible mt8188_compat = {
+       .regs = mt_i2c_regs_v3,
+       .pmic_i2c = 0,
+       .dcm = 0,
+       .auto_restart = 1,
+       .aux_len_reg = 1,
+       .timing_adjust = 1,
+       .dma_sync = 0,
+       .ltiming_adjust = 1,
+       .apdma_sync = 1,
+       .max_dma_support = 36,
+};
+
 static const struct mtk_i2c_compatible mt8192_compat = {
        .quirks = &mt8183_i2c_quirks,
        .regs = mt_i2c_regs_v2,
@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c_of_match[] = {
        { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
        { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
        { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
+       { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
        { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
        {}
 };